Wa1 Au Paper

Powerful things you can do with

Template-Based Power Network Synthesis combined with

Basic Polygon Operations in IC Compiler

Johnie Au

Cypress Semiconductor

San Jose, USA

www.cypress.com

ABSTRACT

Template-based power network synthesis provides the means & flexibility to quickly tune-up the

power grid by turning some parametric knobs of the templates to adapt to on-going placement

and routing changes during floorplan exploration phase. It is extremely crucial for Low Power

System-On-a-Chip (SOC) to have precise power grid design to minimize multivoltage supply

variations for optimum performance due to on chip voltage variations. By specifying coordinates

of desired rectilinear power plan regions for the template, different favors of power network can

be built accordingly to the power requirement. As power network is mostly driven by placement

of I/O, macros and standard cells, clock tree and signal congestion, rectilinear power plan re-

inates can be calculated from the bounding box of any cells or features on the chip

with respect to the core area. By using the basic polygon operating functions in IC Compiler,

complex power plan regions serving various purposes can then be derived quickly and easily

without too much effort. The paper will attempt to discuss a few examples and illustrate their

applications.

SNUG 2012 2 Templated-based PNS with Basic Polygon Ops

Table of Contents

1. Introduction ........................................................................................................................... 3

2. Low Power Integrated Circuits demand adaptive power nework design ............................ 3

3. Template-based Power Netowrk Synthesis with polygon operations ................................... 5

4. Flow Advantages and Results ............................................................................................. 13

5. Conclusions ......................................................................................................................... 13

6. References ........................................................................................................................... 13

Table of Figures

Figure 1. Simple Design with Single Power Domain ..................................................................... 3

Figure 2. Multiple Power domain and Voltage Area. ..................................................................... 4

Figure 3. Power swtich array in Shutdown Domains .................................................................... 4

Figure 4. Dynamic IRdrop with package RLC .............................................................................. 5

Figure 5. Template-based PNS Flow Chart .................................................................................... 5

Figure 6. Simple Power Plan Region .............................................................................................. 6

Figure 7. Complex Power Plan Regions ......................................................................................... 6

Figure 8. Using "compute_polygon " inline with "create_power_plan_regions" ........................... 7

Figure 9. Template for Top Metal Layer N, N-1 ............................................................................ 8

Figure 10. 2 top layers (N) versus Single top layer (N) with jumpers (N-1) ................................. 8

Figure 11. Application for XOR and RESIZE ............................................................................... 9

Figure 12. Overlapping irregular shaped macros ......................................................................... 10

Figure 13. Resized then OR before power plan region creation ................................................... 10

Figure 14. Column of MTCMOS in a power domain ................................................................... 11

Figure 15. create_power_plan_regions ... get_cells *mtcmos* .................................................... 11

Figure 16. MTCMOS power strapping ........................................................................................ 12

Figure 17. Centroid of a polygon ................................................................................................. 12


1. Introduction

This paper reviews the usage of Template-based power network synthesis and explore the pos-

sible application with the help of basic polygon operations supported in ICC. The Template-

based power network synthesis flow was first introduced in 2010 SNUG. As described in the

paper and application notes, this flow helps to automate multivoltage power network design for

bound dedicated power network based on voltage area, polygon list, group of macros or the core.

The flow works perfectly with simple rectilinear shaped features and polygons but sometimes

stumbles on multivoltage design with irregular shaped or overlapping features. Luckily, the flow

can be enhanced as the irregular shaped features can be pre-processed and reshaped all within IC

Compiler using the supported

2. Low Power Integrated Circuits demand adaptive power network design

. The design usually needs to support a

set of power supplies feeding into different power domain and voltage areas alongside with

power management cells. Traditionally, a decent amount of time was spent in power grid design

during floor planning edes-

domain and voltage areas as shown in Fig.2, is extremely time consuming to explore new power

grid as the grid is not programmable nor parameterized.

Figure 1. Simple Design with Single Power Domain


Figure 2. Multiple Power domain and Voltage Area.

Advanced low power design may also have on-chip power switches of different type (Fig.3) to

control power supply in the shutdown power domain to conserve power when the block is dis-

abled. The number of power switches must be sufficient to support functional as well as scan

switching current requirement.

Figure 3. Power switch array in Shutdown Domains

Low power SoC feature sets are evolving quickly as the mobile market and touch screen market

are expanding. As complex power grid plays an important role in floor planning, being able to

rapidly generate a prototype power network is advantageous in speeding up the entire place and

route process. Traditional power design approach is to layout a general power grid manually and

modify and enhance as needed, mostly due to design change, voltage area change, ir drop feed-

back and others. Neve

placement quite often especially with power management cells like power switches, level shifters

and isolation cells. Any change in power management cells triggers power grid ECO. Worst of

all, static and dynamic voltage drop final feedback also come at the end close to tapeout. Any IR


drop surprises (Fig.4) which requires power grid enhancement would definitely stall tapeout.

Figure 4. Dynamic IRdrop with package RLC

Only if we can better predict the low power architecture, the cell placement, the potential buffers

or repeaters needed, the power consumption profiles, that we can design and build a bullet proof

power grid sitting on the shelf waiting for tapeout.

3. Template-based Power Network Synthesis with polygon operations

Template-

path to rapid power network prototyping. presentation, Tem-

plate-based power network synthesis is based on predefined templates which describe the dimen-

sions and characteristics of the physical implementation of the power network per layer for each

power net. Figure 5. Shows the Flow recommended by Synopsys (see references)

Figure 5. Template-based PNS Flow Chart

As shown in (Fig.5), the template-based flow allows user to create new regions, so call power

plan regions, on the floorplan. These regions are solely for power grid creation guided by the

m for creating complex multivoltage power grid. In other

words, power plan regions are physical regions which are defined to bound the implementation

of the selected template. With a set of predefined templates, of which dictates the metal strap-


ping specifications, the power plan strategies then select the appropriate templates for each

power plan region for specific power net and further re-shaping of the region. Power plan regions

are simply rectilinear physical regions. Simple power plan regions could be just a group of volt-

age areas, including or excluding a selected set of hard macros like I/O or memories (see Fig. 6).

Figure 6. Simple Power Plan Region

For multvoltage design, the power plan regions would look a little busy (see Fig.7).

Figure 7. Complex Power Plan Regions


As shown in Fig.7, complex power plans consist of many groups of irregular shapes of hard mac-

ros; disjoint voltage areas, always-on regions all over the chip. One example to automate the

generation of all necessary power_plan_regions, without stretching them manually, is to use a

foreach loop on the voltage_areas collection. Nevertheless, voltage areas often do have the op-

timal shape for laying down power ring and power grid as its purpose is for cell placement only.

polygon coordinates must be re-shaped for the automation to be usable. e-

options to remove notch and jog and expand but

lagging options to merge polygons and does any AND, OR, NOT, XOR functions. Nevertheless,

as described in reference.2, IC Compiler(s) can perform the basic polygon operations. And to

streamline the polygon merging, for example, before running the create_power_plan command,

once can run the polygon operation inline with the command as shown in Fig.8.

Figure 8. Using "compute_polygon " inline with "create_power_plan_regions"

As power plan regions can be derived from any existing floorplanning features. With the help of

basic polygon operations supported by IC Compiler , complex power plan regions can then be

derived automatically and react instantly to any floorplan/macro placement updates along the

entire design cycle m-

e


Another application of pre-processing e-

llows. Generating top level power grid with top metal layer N

and Layer N-1 is straight forward using the template for the 2 layers as shown in Fig.9.

Figure 9. Template for Top Metal Layer N, N-1

However, to generate a top level power grid with only the Layer Metal N, allowing only jumper

in Layer Metal N-1 is tricky.

Figure 10. 2 top layers (N) versus Single top layer (N) with jumpers (N-1)

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