w5 2004-10-14 BF533 Peripheral v4 - Access IC Lab (Prof. …access.ee.ntu.edu.tw/course/DSP_Lab/slides/w5 2004-10-14... · 2010-07-14 · Lab: Blink Reference Appendix[3] ... Peripheral

ACCESS IC LAB

Graduate Institute of Electronics Engineering, NTU

ADSPADSP--BF533 PeripheralsBF533 Peripherals

Advisor: Prof. Andy Wu2004/10/14

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

P2

OutlineOutline

IntroductionBF533 Peripherals[1]Using Peripherals

Lab: Blink

ReferenceAppendix[3]

DMA


P3

IntroductionIntroduction

Peripheral --The ADSP-BF533 (HS) processor contains a rich set of peripherals connected to the core via several high bandwidth buses, providing flexibility in system configuration as well as excellent overall system performance.


P4


P5

OutlineOutline


Lab: Blink


DMA


P6

ADSPADSP--BF533 Peripherals[1]BF533 Peripherals[1]1. DMA Controllers2. SPI3. PPI/GPIO4. SPORTS5. UART6. Timer/Counters

Real-Time Clock (RTC)Watchdog TimerCore Timer

7. OthersDebug/JTAG InterfaceEvent HandlerOn-Chip PLL Capable of 1x To 63x Frequency Multiplication


P7

DMA -- Direct Memory AccessDMA controllers features:

Multiple, independent, and automated data transfers.DMA transfers occur between:

Internal memories and any of its DMA-capable peripherals.Any of the DMA-capable peripherals and external devices connected to the external memory interfaces, including the SDRAM controller and the asynchronous memory controller.

DMA-capable peripherals include:PPI , SPORTs, SPI port, and UART.

Each individual DMA-capable peripheral has at least one dedicated DMA channel.


P8

DMA controller supports:1-dimensional (1D) DMA transfers.2-dimensional (2D) DMA transfers.

DMA transfer initialization can be implemented from:RegistersSets of parameters called descriptor blocks.

There are two memory DMA channels:Provided for transfers between the various memories, including external SDRAM, ROM, SRAM, and flash memory.

Memory DMA transfers can be controlled by:Descriptor-based methodology (flexible).Register-based auto-buffer mechanism (standard).


P9

Examples of DMA types supported by the DMA controller include:

A single, linear buffer that stops upon completion.A circular, auto-refreshing buffer that interrupts on each full or fractionally full buffer.1-D or 2-D DMA using a linked list of descriptors.2-D DMA using an array of descriptors, specifying only the base DMA address within a common page.


P10

Example: MemDMA (descriptor-base)

More readingSee Appendix -- DMA

Setup I/O buffers

Setup descriptor

Start DMA

framework

move

source destination


P11

SPI -- Serial Peripheral InterfaceFull-duplex, synchronous serial interface

Three pins for transferring data:two data pins

Master Output-Slave Input (MOSI)Master Input-Slave Output (MISO)

clock pinSerial Clock (SCK)

DMA controllerUnidirectional


P12

PPI -- Parallel Peripheral InterfaceCan connect directly to:

Parallel A/D and D/A convertersITU-R 601/656 video encoders and decodersOther general-purpose peripherals.

Dedicated input clock pinUp to 3 frame synchronization pinsUp to 16 data pins. The input clock supports parallel data rates up to half the system clock rate.


P13

SPORTS -- Serial portsTwo dual-channel synchronous serial ports

SPORT0 and SPORT1Serial and multiprocessor communications

The SPORTs support the following features:I2S capable operation.Bidirectional operation Each SPORT has two sets of independent transmit and receive pins, enabling eight channels of I2S stereo audio.More


P14

UART --Universal Asynchronous Receiver/Transmitter

Supportfull-duplexasynchronous transfers of serial data

DMA-supportedtwo dedicated DMA channels, one for transmit and one for receivelower default priority than most DMA channels

low service rates


P15

Timer*3Real-Time ClockWatchdog TimerCore Timer


P16

Event HandlerDebug/JTAG InterfaceOn-Chip PLL Capable of 1x To 63x Frequency Multiplication


P17

OutlineOutline


Lab: Blink


DMA


P18

Using PeripheralsUsing Peripherals

./Analog Devices/VisualDSP 3.5 16-Bit/EZ-Kits/ADSP-BF533/Examples

readme.txt

Ex: #include<defBF533.h>, startup.asm

Help IndexEx: EVTx, RTS, lsetup()


P19

LAB: BlinkLAB: Blink

GoalAccess LEDLearn about I/O, interrupts, and timer

Filesmain.cInitialisation.cISRs.cBF533 Flags.hreadme.txt


P20

Initialisation.cInitialisation.c

Init_Flags()switch connected to PF8 (SW4)

Init_Timers()Timer0 for PWM mode

Init_EBIU()EBIU setup (External Bus Interface Unit)

Init_Flash()sets the pin direction of Port B in Flash A

Init_Interrupts()Interrupt configuration

Help ^_^Ex: FIO_INEN

TIMERx_CONFIGEBIU_AMBCTL SIC_IARxregister_handler( )Flash General-Purpose IO


P21

ISRs.cISRs.c

EX_INTERRUPT_HANDLER(Timer0_ISR)timer interrupt

LED ( !)

EX_INTERRUPT_HANDLER(FlagA_ISR)SW4

FIO clear (SW !)LED ( or !)


P22

Turn on switch SW9_1 [2](p1-6, p3-10)Build & RunPush button SW4 and see the change

Example:SW4 SW5

(SW9 !)

void Init_Flags(void){

*pFIO_INEN = 0x0200;*pFIO_DIR = 0x0000;*pFIO_EDGE = 0x0200;*pFIO_MASKA_D = 0x0200;

}EX_INTERRUPT_HANDLER(FlagA_ISR){

*pFIO_FLAG_C = 0x0200;

}


P23

SW4 SW7 LEDtime, direction, others

BlinkI/O, interrupt, timer

Any other things


P24

OutlineOutline


Lab: Blink


DMA (p25~p48)


P25

ReferenceReference[1] Analog Devices, Inc. ADSP-BF533_HiSpeed_pra.pdf , 2004.[2] Analog Devices, Inc. ADSP-BF533 EZ-Kit Lite Evaluation System Manual , Revision 1.0, April 2003.[3] Analog Devices, Inc. ADSP-BF533 BlackfinR Processor Hardware Reference , Revision 1.0, December 2003.

[4] Analog Devices, Inc. Analog Devices_ Embedded Processing & DSP [Online] . Available: http://www.analog.com/dsp


P26

OutlineOutline


Lab: Blink


DMA (p25~p48)


P27

Appendix Appendix DMA [3]DMA [3]

RegisterFlow chartExampleExercise (optional)

MemDMARegister BasedDescriptor Based


P28

Register (1/2)Register (1/2)1. Generic DMA register (Table 9-1)

Naming conventions for DMA MMRs (Table 9-2)Memory DMA register (Table 9-3)

2. Next descriptor pointer register (NEXT_DESC_PTR) (Table 9-4)3. Start address register (START_ADDR) (Table 9-5)4. DMA configuration register (DMA_CONFIG) (Table 9-6) !5. Loop count register

Inner loop count register (X_COUNT) (Table 9-7)Inner loop address increase register (X_MODIFY) (Table 9-8)Outer loop count register (Y_COUNT) (Table 9-9)Outer loop address increase register (Y_MODIFY) (Table 9-10)

6. Current registerCurrent descriptor pointer register (CURR_DESC_PTR) (Table 9-11)Current address register (CURR_ADDR) (Table 9-12)Current Inner loop count register (CURR_X_COUNT) (Table 9-13)Current outer loop count register (CURR_Y_COUNT) (Table 9-14)


P29

Register (2/2)Register (2/2)7. Peripheral map register (PERIPHERAL_MAP) (Table 9-15)

Binary peripheral map setting (Table 9-16)

8. Peripheral DMA IRQ status register (IRQ_STATUS) (Table 9-17)


P30

1. Generic DMA register (1/2)1. Generic DMA register (1/2)


P31

1. Generic DMA register (2/2)1. Generic DMA register (2/2)

Naming conventions for DMA MMRs (Table 9-2)Parameter registers, such as DMAx_CONFIG and DMAx_X_COUNTOnly parameter registers can be loaded directly from descriptor elementsThe letter x in DMAx represents a specific DMA-capable peripheral (Table 9-16)

Memory DMA register (Table 9-3)Cannot be reassigned to different channel


P32

2. Next descriptor pointer register2. Next descriptor pointer register

NEXT_DESC_PTR (Table 9-4) (Figure 9-1)Specify where to look for the start of the next descriptor block when the current descriptor block finished


P33

3. Start address register3. Start address register

START_ADDR (Table 9-5) (Figure 9-2)Start address of the data buffer currently targeted for DMA


P34

4. DMA configuration register4. DMA configuration register

DMA_CONFIG (Table 9-6) (Figure 9-3)Set up DMA parameters and operating modes

Peripheral DMA Configuration registersDetermines whether DMA is enabled and performs other essential DMA functions, including functions that are peripheral dependentDMA Enable bit

Begin loading a descriptor block from memoryOnly during DMA channel initialization and in activating or terminating auto-buffer mode

Buffer Clear bitClear the DMA bufferOnly when a DMA channel is not enabled


P35


P36


P37


P38


P39

5. Loop count register5. Loop count register

Inner loop count register (X_COUNT) (Table 9-7)Inner loop countSpecify the number of element to read in

Inner loop address increase register (X_MODIFY) (Table 9-8)Signed, two s-complement byte address increase

Outer loop count register (Y_COUNT) (Table 9-9)Outer loop address increase register (Y_MODIFY) (Table 9-10)


P40

6. Current register6. Current register

Current descriptor pointer register (CURR_DESC_PTR) (Table 9-11)Memory address for the next descriptor element to be loaded

Current address register (CURR_ADDR) (Table 9-12)Present DMA transfer address for a given DMA session

Current Inner loop count register (CURR_X_COUNT) (Table 9-13)Loaded by the X_COUNT register at the beginning of each DMA session

Current outer loop count register (CURR_Y_COUNT) (Table 9-14)Loaded by the Y_COUNT register at the beginning of each 2D DMA session


P41

7. Peripheral map register7. Peripheral map register

PERIPHERAL_MAP (Table 9-15) (Figure 9-12)Map the channel to a specific peripheralIdentify whether the channel is a peripheral DMA channel or a memory DMA channel

Binary peripheral map setting (Table 9-16)


P42


P43


P44

8. Peripheral DMA IRQ status register8. Peripheral DMA IRQ status register

Records the occurrence of any of its interrupt sourcesIRQ_STATUS (Table 9-17) (Figure 9-13)

contains bits that record whether the DMA channel: Is enabled and operating, enabled but stopped, or disabledIs fetching data or a DMA descriptorHas detected that a global DMA interrupt or a channel interrupt is being assertedHas logged occurrence of a DMA error

SupportData driven interrupts (Table 9-18)

Peripheral Error interrupts DMA Error interrupts (for example, Bad Descriptor or Bus Error)


P45


P46


P47

Flow ChartFlow Chart


P48

Example (1/2)Example (1/2)

Continuous transfers using auto-bufferingFor example

Two 512-word sub-buffers inside a 1K word buffer could be used to receive 16-bit peripheral data with these settings:

START_ADDR = buffer base addressDMA_CONFIG = 0x10D7 (FLOW = 1, DI_EN = 1, DI_SEL = 1,

DMA2D = 1, WDSIZE = 01, WNR = 1, DMA_EN = 1)X_COUNT = 512X_MODIFY = 2 for 16-bit dataY_COUNT = 2 for two sub-buffersY_MODIFY = 2, same as X_MODIFY for contiguous sub-buffers


P49

Example (2/2)Example (2/2)

Assume receive data needs to be processed in packets of sixteen 32-bit elements. A four-part 2D DMA buffer can be allocated where each of the four sub-buffers can hold one packet with these settings:

START_ADDR = buffer base addressDMA_CONFIG = 0x101B (FLOW = 1, DI_EN = 0,

DMA2D = 1, WDSIZE = 10, WNR = 1, DMA_EN = 1)X_COUNT = 16X_MODIFY = 4 for 32-bit dataY_COUNT = 4 for four sub-buffersY_MODIFY = 4, same as X_MODIFY for contiguous sub-buffers


P50

Exercise (optional)Exercise (optional)

MemDMARegister Based

Insert breakpointBlackfin memory: 0xff800000, 0xff800400

Descriptor BasedInsert breakpointBlackfin memory:output_frame_1Dto1D, output_frame_1Dto2D, output_frame_2Dto2D

./Analog Devices/VisualDSP 3.5 16-Bit/EZ-Kits/ADSP-BF533/Examples/MemDMA


P51


P52

ConclusionConclusion

DMA registers DMA

peripherals peripheralDMA controller

Help

Documents

w5 2004-10-14 BF533 Peripheral v4 - Access IC Lab (Prof. …access.ee.ntu.edu.tw/course/DSP_Lab/slides/w5 2004-10-14... · 2010-07-14 · Lab: Blink Reference Appendix[3] ... Peripheral