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Voice Enabled Speed Control of Single induction motor
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VOICE ENABLED SPEED CONTROL OF SINGLE PHASE INDUCTION MOTOR
A PROJECT REPORT
Submitted by
ABHISHEK PALIT (11604105001)T.ANAND BABU (11604105301)V.RAJASEKHAR GUPTA (11604105012)
in partial fulfillment for the award of the degree
of
BACHELOR OF ENGINEERING
in
ELECTRICAL & ELECTRONICS ENGINEERING
SRI VENKATESWARA COLLEGE OF ENGINEERING AND
TECHNOLOGY, TIRUPACHUR
ANNA UNIVERSITY:: CHENNAI 600025
ANNA UNIVERSITY: CHENNAI 600 025
BONAFIDE CERTIFICATE
This is to certify that this project report “AUTOMATIC BUS FARE
COLLECTION SYSTEM” is the bonafide work of “SARAVANAN.N,
SHIJU.K, SRINIVASAN.D, and THIRUPURANTHAGAN.V. who carried
out the project work under my supervision.
ACKNO
SIGNATURE
Mr. A.SENTHIL KUMAR M.E.,
HEAD OF THE DEPARTMENT
ELECTRONICS & COMMUNICATION ENGG.
SRI VENKATESWARA COLLEGE OF
ENGINEERING AND TECHNOLOGY
TIRUPACHUR – 631 203
SIGNATURE
Ms. P.ANANTHAVALLI M.E.,(PhD)
ASST.PROFESSOR
ELECTRONICS & COMMUNICATION ENGG.
SRI VENKATESWARA COLLEGE OF
ENGINEERING AND TECHNOLOGY
TIRUPACHUR – 631 203
CERTIFICATE OF EVALUATION
COLLEGE NAME : SRI VENKATESWARA COLLEGE OF
ENGINEERING AND TECHNOLOGY
BRANCH : Electronics &Communication Engg.
SEMESTER : VIII
PROJECT TITLE : AUTOMATIC BUSFARE COLLECTION
SYSTEM
S. No. Name of the student Register No Name of the
Supervicer
1 SARAVANAN.N 11604106055 Ms.P.ANANTHAVALLI
2 SHIJU.K 11604106062 M.E., (PhD)
3 SRINIVASAN.D 11604106067 ASST.PROFESSOR
4 THIRUPURANTHAGAN.V 11604106311 Dept.of.ECE
The report of the project are submitted by the above students in partial
fulfillment for the award of Bachelor of Engineering degree, in Electronics
and Communication Engineering of Anna University where enabled and
confirmed to be the report work done by the above students and then evaluated.
Internal Examiner External Examiner
MICROCONTROLLER
2.1 INTRODUCTION :
In modern electronics, all operations are to be very
precise and accurate. Moreover the usage of components should be simple,
economic, reliable and compact. In addition to all these, they should be more
user friendly. In previous days there were components, which do not provide
all these requirements. Later in the development of electronics brought into
field the Microprocessors. These Microprocessors were found to be simple,
cheap and so on. Further development introduced Micro-controllers in the
market.
The Micro-controllers are far far better and had all the
requirements of the user like, fast in operation, economic, small in size, user
friendly, etc., Since Micro-controller has advantages than Micro-processors
this has been used in the project. Programming Micro-controllers using
Embedded–C is easily understandable for those persons who has very little
knowledge about it. The C program can be easily converted into assembly
language using many assembler software available in the market. Due to all
these aspects of Micro-controller it has been used in the PMS module as one
of the control unit.
2.2 FEATURES:
• Compatible with MCS-51™ Products
• 8K Bytes of In-System Reprogrammable Flash Memory
• Endurance: 1,000 Write/Erase Cycles
• Fully Static Operation: 0 Hz to 24 MHz
• Three-level Program Memory Lock
• 256 x 8-Bit Internal RAM
• 32 Programmable I/O Lines
• Three 16-bit Timer/Counters
• Eight Interrupt Sources
• Programmable Serial Channel
• Low Power Idle and Power Down Modes
2.3 PIN DIAGRAM OF 89S52:
Fig 2.3.1
2.4 INTERNAL ARCHITECTURE OF 89S52:
Fig 2.4.12.5 DESCRIPTION: The AT89S52 is a low-power, high-performance CMOS
8-bit Microcomputer with 8K bytes of Flash programmable and erasable
read only memory (EPROM). The device is manufactured using Atmel’s
high-density non-volatile memory technology and is compatible with the
industry standard 80C51 and 80C52 instruction set and pin out. The on-chip
Flash allows the program memory to be reprogrammed in- system or by a
conventional non-volatile memory programmer by combining a versatile 8-
bit CPU with Flash on a monolithic chip, the Atmel AT89S52 is a powerful
microcomputer, which provides a highly flexible and cost effective solution
to many embedded control applications.
2.5.1 PORT 0:
Port 0 is an 8-bit open drain bi-directional I/O port. As an
output Port, each pin can sink eight TTL inputs. When 1s are written to Port
0 pins, the pins can be used as high-impedance inputs. Port 0 can also be
configured to be the multiplexed low-order address/data bus during accesses
to external pro-gram and data memory. In this mode, P0 has internal pull
ups. Port 0 also receives the code bytes during Flash programming and
outputs the code bytes during program verification. External pull-ups are
required during program verification.
2.5.2 PORT 1:
Port 1 is an 8-bit bi-directional I/O port with internal pull-ups.
The Port 1 output buffers can sink/source four TTL inputs. When 1s are
written to Port 1 pins, they are pulled high by the internal pull-ups and can
be used as inputs. As inputs, Port 1 pins that are externally being pulled low
will source current (I IL) because of the internal pull-ups. In addition, P1.0
and P1.1 can be configured to be the timer/counter 2 external count input
(P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively,
Port 1 also receives the low-order address bytes during Flash programming
and verification emits the contents of the P2 Special Function Register. Port
2 also receives the high-order address bits and some control signals during
Flash programming and verification.
2.5.3 PORT 2:
Port 2 is an 8-bit bi-directional I/O port with internal
pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When
1s are written to Port 2 pins, they are pulled high by the internal pull-ups and
can be used as inputs. As inputs Port 2 pins that are externally being pulled
low will source current (I IL) because of the internal pull-ups. Port 2 emits
the high-order address byte during fetches from external program memory
and during accesses to external data memory that use 16-bit addresses. In
this application, Port 2 uses strong internal pull-ups when emitting 1s.
During accesses to external data memory that use 8-bit addresses, Port 2
emits the contents of the P2 Special Function Register. Port 2 also receives
the high-order address bits and some control signals during Flash
programming and verification.
2.5.4 PORT 3:
Port 3 is an 8-bit bi-directional I/O port with internal pull-
ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are
written to Port 3 pins, they are pulled high by the internal pull-ups and can
be used as inputs. As inputs, Port 3 pins that are externally being pulled low
will source current (I IL) because of the pull-ups. Port 3 also receives some
control signals for Flash programming and verification.
2.5.5 PORT PIN ALTERNATE FUNCTIONS:
P3.0 RXD (serial input port)
P3.1 TXD (serial output port)
P3.2 INT0 (external interrupt 0)
P3.3 INT1 (external interrupt 1)
P3.4 T0 (timer 0 external input)
P3.5 T1 (timer 1 external input)
P3.6 WR (external data memory write strobe)
P3.7 RD (external data memory read strobe)
2.5.6 PIN FUNCTIONS:
RST:
Reset input. A high on this pin for two machine cycles while the
Oscillator is running resets the device.
ALE/PROG:
Address Latch Enable is an output pulse for latching
the low byte of the address during accesses to external memory. This pin is
also the program pulse input (PROG) during Flash programming .In normal
operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency
and may be used for external timing or clocking purposes. Note, however,
that one ALE pulse is skipped during each access to external data memory.
If desired, ALE operation can be disabled by setting bit 0 of SFR location
8EH. With the bit set, ALE is active only during a MOVX or MOVC
instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-
disable bit has no effect if the micro controller is in external execution mode.
PSEN:
Program Store Enable is the read strobe to external
program memory. When the AT89S52 is executing code from external pro-
gram memory, PSEN is activated twice each machine cycle, except that two
PSEN activations are skipped during each access to external data memory.
EA/V PP:
External Access Enable. EA must be strapped to GND in order
to enable the device to fetch code from external pro-gram memory locations
starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is
programmed, EA will be internally latched on reset. EA should be strapped
to V CC for internal program executions. This pin also receives the 12-volt
programming enable volt-age (V PP) during Flash programming when 12-
volt programming is selected.
XTAL1:
Input to the inverting oscillator amplifier and input to the internal
Clock operating circuit.
2.5.7 REGISTER’S DESCRIPTION:
SPECIAL FUNCTION REGISTER:
A map of the on-chip memory area called the Special Function
Register (SFR) Note that not all of the addresses are occupied, and
unoccupied addresses may not be implemented on the chip. Read accesses to
these addresses will in general return random data, and write accesses will
have an indeterminate effect. User software should not write 1s to these
unlisted locations, since they may be used in future products to invoke new
features. In that case, the reset or inactive values of the new bits will always
be 0. P0-P3. P0, P1, P2, P3 are the SFR latches of ports 0,1,2,3 respectively.
These parallel ports provide the 32 I/O lines. These registers reside as SFR
at locations 80H, 90H, 0A0H, and 0B0H respectively. Stack Pointer
This SFR indicates where the next value to be taken from the stack
will be read from, in internal RAM. This SFR is modified by all instructions,
which modify the stack and whenever the instructions are provoked by the
micro controller.
DATA POINTER:
The SFRs DPL and DPH work together to represent a 16-bit value
called the Data Pointer. These registers reside at locations 82H, 83H
respectively. The DPTR is used in operations regarding external RAM and
some instructions involving code memory. Since it is an unsigned two-byte
integer value, it can represent values from 0000H to FFFFH.
PCON (Power Control Register):
The power control SFR is used to control the 89S52’s Power control
modes. Certain operations of 89C52 allow it to go into a type of sleep mode.
TCON (Timer Counter Control Register):
The timer control SFR is used to configure and modify the way in
which the two timers operate. This SFR controls whether each of the two
timers is running or stopped and contains a flag to indicate that each timer
has overflowed. Additionally, some non-timer related bits are also located in
the TCON SFR which is used to configure the way in which the external
interrupts are activated and also contain the external interrupt flags, which
are set, when an external interrupt has occurred. TMOD (timer counter mode
control register)
The timer mode SFR is used to configure the mode of operation of
each of the two timers. Using this SFR program may configure each timer to
be a 16-bit timer, an 8-bit auto-reload timer, a 13-bit timer, or two separate
timers. Additionally, we may configure the timers to only count when an
external pin is activated or to count “events” that are indicated on an external
pin.
ACCUMULATOR:
The accumulator, as its name suggests is used as a general
register to accumulate the results of a large number of instructions. It can
hold an 8-bit value and it is the most versatile register. The accumulator
resides as SFR at E0H.
B Register:
The B register is very similar to the accumulator, in the sense that it
can hold an 8-bit value. It resides at F0H.The B register is commonly used
by programmers as an auxiliary register to store temporary values.
TIMER 0, 1:
Fig 2.5.1
SCON (Serial Port Control Register):
The serial control SFR is used to configure the behaviour of the
89S52 on board serial port. This SFR controls the baud rate of the serial
port, whether the serial port is activated to receive data and also contains
flag that are set when a byte is successfully sent are received.
SBUF (Serial Data Buffer):
This serial data buffer is actually two separate registers. A transmitter
buffer and receive buffer register.
IP (Interrupt Priority Register):
This SFR is used to specify the relative priority of each interrupt. An
interrupt may only interrupt interrupts of lower priority.
TIMER 2 REGISTER:
Control and status bits are contained in registers T2CON and 2MOD
for Timer 2. The register pair (RCAP2H, RCAP2L) is the Capture/Reload
registers for Timer 2 in 16-bit capture mode or 16-bit auto-reload mode.
INTERRUPT REGISTERS:
The individual interrupt enable bits are in the IE register. Two
Priorities can be set for each of the six-interrupt sources in the IP register.
DATA REGISTER:
The AT89S52 implements 256 bytes of on-chip RAM. The upper 128
bytes occupy a parallel address space to the Special Function Registers. That
means the upper 128 bytes have the same addresses as the SFR space but are
physically separate from SFR space. When an instruction accesses an
internal location above address 7FH, the address mode used in the
instruction specifies whether the CPU accesses the upper 128 bytes of RAM
or the SFR space. Instructions that use direct addressing access SFR space.
TIMER 0, 1:
TABLE 2.5.1
Timer 0 and Timer 1 in the AT89S52 operate the same way as
Timer 0 and Timer 1 in the AT89S52
TIMER 2:
Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an
event counter. The type of operation is selected by bit C/T2 in the SFR
T2CON Timer 2 has three operating modes: capture, auto-reload (up or
down counting), and baud rate generator. The modes are selected by bits in
T2CON; Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer
function, the TL2 register is incremented every machine cycle. Since a
machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the
oscillator frequency. Count is incremented.
The new count value appears in the register during S3P1 of the
cycle following the one in which the transition was detected. Since two
machine cycles (24 oscillator Periods) are required to recognize a 1 to-0
transition; the maximum count rate is 1/24 of the oscillator frequency. To
ensure that a given level is sampled at least once before it changes, the level
should be held for at least one full machine cycle.
PROGRAMMABLE CLOCK OUT:
A 50% duty cycle clock can be programmed to come out on P1.0 this
pin, besides being a regular I/O pin, has two alternate Functions. It can be
programmed to input the external clock for Timer/Counter 2 or to output a
50% duty cycle clock ranging from 61 Hz to 4 MHz at a 16 MHz operating
frequency. To configure the Timer/Counter 2 as a clock generator, bit C/T2
(T2CON.1) must be cleared and bit T2OE (T2MOD.1) must be set. Bit TR2
T2CON.2) starts and stops the timer. The clock-out frequency depends on
the oscillator frequency and the reload value of Timer 2 capture registers
(RCAP2H, RCAP2L), as shown in the following equation. In the clock-out
mode, Timer 2 rollovers will not generate an interrupt.
UART:
The UART in the AT89S52 operates the same way as the UART in the
AT89C52.
INTERRUPTS:
The AT89S52 has a total of six interrupt vectors: two external
Interrupts (INT0 and INT1), three timer interrupts (Timers 0, 1, and 2), and
the serial port interrupt. Each of these interrupt sources can be individually
enabled or disabled by setting or clearing a bit in Special Function Register
IE. IE also contains a global disable bit, EA, which disables all interrupts at
once. By setting this interrupt as high each interrupt is individually enabled
or disabled by setting or clearing its enable bit.
OSCILLATOR CHARECTERISTICS:
XTAL1 and XTAL2 are the input and output, respectively,
of an Inverting amplifier that can be configured for use as an on-chip
Oscillator; either a quartz crystal or ceramic resonator may be used. To drive
the device from an external clock source, XTAL2 should be left
unconnected while XTAL1 is driven; there are no requirements on the duty
cycle of the external clock signal, since the input to the internal clocking
circuitry is through a divide-by-two flip-flop, but minimum and maxi-mum
voltage high and low time specifications must be observed.
IDLE MODE:
In idle mode, the CPU puts itself to sleep while all the on-
chip peripherals remain active. The mode is invoked by software. The
content of the on-chip RAM and all the special functions registers remain
unchanged during this mode. The idle mode can be terminated by any
enabled interrupt or by a hardware reset.
Note that when idle mode is terminated by a hardware reset,
the device normally resumes program execution from where it left off, up to
two machine cycles before the internal reset algorithm takes control. On-
chip hardware inhibits access to internal RAM in this event, but access to the
port pins is not inhibited. To eliminate the possibility of an unexpected write
to a port pin when idle mode is terminated by a reset, the instruction
following the one that invokes idle mode should not write to a port pin or to
external memory.
POWER DOWN MODULE:
In the power down mode, the oscillator is stopped, and the
instruction that invokes power down is the last instruction executed. The on-
chip RAM and Special Function Registers retain their values until the power
down mode is terminated. The only exit from power down is a hardware
reset. Reset redefines the SFRs but does not change the on-chip RAM. The
reset should not be activated before V CC is restored to its normal operating
level and must be held active long enough to allow the oscillator to restart
and stabilize.
PROGRAM MEMORY LOCK BITS:
The AT89S52 has three lock bits that can be left un-programmed
(U) or can be programmed (P) to obtain the additional features
PROGRAMMING THE FLASH:
The AT89S52 is normally shipped with the on-chip Flash
memory array in the erased state (that is, contents = FFH) and ready to be
programmed. The programming interface accepts either a high-voltage (12-
volt) or a low-voltage (V CC) program enable signal. The low voltage-
programming mode provides a convenient way to program the AT89c51
inside the user’s system, while the high voltage programming mode is
compatible with conventional third- party Flash or EPROM programmers.
PROGRAMMING ALGORITHM:
To program the AT89S52, take the following steps.
1. Input the desired memory location on the address lines.
2. Input the appropriate data byte on the data lines.
3. Activate the correct combination of control signals.
4. Raise EA/V PP to 12V for the high-voltage programming
mode.
5. Pulse ALE/PROG once to program a byte in the Flash array or the
lock bits. The byte-write cycle is self-timed and typically takes no more than
1.5 Ms. Repeat steps 1 through 5, changing the address and data for the
entire array or until the end of the object file is reached.
DATA POLLING:
The AT89S52 features Data Polling to indicate the end
of a write cycle. During a write cycle, an attempted read of the last byte
written will result in the complement of the written data on PO.7. Once the
write cycle has been completed, true data is valid on all outputs, and the next
cycle may begin. Data Polling may begin any time after a write cycle has
been initiated.
READY/BUSY:
The progress of byte programming can also be monitored
by the RDY/BSY output signal. P3.4 is pulled low after ALE goes high
during programming to indicate BUSY. P3.4 is pulled high again when
programming is done to indicate READY.
PROGRAMS VERIFY:
If lock bits LB1 and LB2 have not been programmed, the
programmed code data can be read back via the address and data lines for
verification. The lock bits cannot be verified directly. Verification of the
lock bits is achieved by observing that their features are enabled.
CHIP ERASE:
The entire Flash array is erased electrically by using the proper
Combination of control signals and by holding ALE/PROG low for 10 Ms.
the code array is written with all 1s. The chip erase operation must be
executed before the code memory can be reprogrammed.
ABSOLUTE MAXIMUM RATINGS:
Operating Temperature.................................. -55°C to +125°C
Device reliability.
Storage Temperature ..................................... -65°C to +150°C
Voltage on Any Pin with Respect to Ground ...-1.0V to +7.0V
Maximum Operating Voltage.......................................... 6.6V
KEYBOARD
The AT keyboard was a keyboard with 84 keys introduced with the IBM
PC/AT computer. It succeeded the 83-key PC/XT keyboard and therefore
did not have many of the features seen on modern keyboards such as arrow
keys and dual ctrl and alt keys. It was later replaced with the 101-key
Enhanced keyboard. Nonetheless, "AT keyboard" remains a popular name
for any keyboard that uses the 5-pin DIN connector. Many Enhanced
keyboards used this, though it was eventually superseded by the PS/2
connector and many modern computers use Universal Serial Bus (USB)
connectors instead.
KEYBOARD COMMANDS
Besides Scan codes, commands can also be sent to and from the keyboard.
The following section details the function of these commands. By no means
is this a complete list. These are only some of the more common commands.
HOST COMMANDS
These commands are sent by the Host to the Keyboard. The most common
command would be the setting/resetting of the Status Indicators (i.e. the
Num lock, Caps Lock & Scroll Lock LEDs). The more common and useful
commands are shown below.
ED Set Status LED's - This command can be used to turn on and off the
Num Lock, Caps Lock & Scroll Lock LED's. After Sending ED, keyboard
will reply with ACK (FA) and wait for another byte which determines their
Status. Bit 0 controls the Scroll Lock, Bit 1 the Num Lock and Bit 2 the
Caps lock. Bits 3 to 7 are ignored.
EE Echo - Upon sending a Echo command to the Keyboard, the keyboard
should reply with a Echo (EE)
F0 Set Scan Code Set. Upon Sending F0, keyboard will reply with ACK
(FA) and wait for another byte, 01-03 which determines the Scan Code
Used. Sending 00 as the second byte will return the Scan Code Set currently
in Use
F3 Set Typematic Repeat Rate. Keyboard will Acknowledge command
with FA and wait for second byte, which determines the Typematic Repeat
Rate.
F4 Keyboard Enable - Clears the keyboards output buffer, enables
Keyboard Scanning and returns an Acknowledgment.
F5 Keyboard Disable - Resets the keyboard, disables Keyboard Scanning
and returns an Acknowledgment.
FE Resend - Upon receipt of the resend command the keyboard will re-
transmit the last byte sent.
FF Reset - Resets the Keyboard.
COMMANDS
Now if the Host Commands are send from the host to the keyboard,
then the keyboard commands must be sent from the keyboard to host. If you
think this way, you must be correct. Below details some of the commands
which the keyboard can send.
FA Acknowledge
AA Power On Self Test Passed (BAT Completed)
EE See Echo Command (Host Commands)
FE Resend - Upon receipt of the resend command the Host should re-
transmit the last byte sent.
00 Error or Buffer Overflow
FF Error or Buffer Overflow
SCON CODES
The diagram below shows the Scan Code assigned to the individual keys.
The Scan code is shown on the bottom of the key. E.g. The Scan Code for
ESC is 76. All the scan codes are shown in Hex. Codes
As you can see, the scan code assignments are quite random. In many cases
the easiest way to convert the scan code to ASCII would be to use a look up
table. Below is the scan codes for the extended keyboard & Numeric keypad
THE KEYBOARD'S CONNECTOR
The PC's AT Keyboard is connected to external equipment using four
wires. These wires are shown below for the 5 Pin DIN Male Plug & PS/2
Plug.
DIN Male Plug
1. KBD Clock
2. KBD Data
3. N/C
4. GND
5. +5V (VCC)
PS/2 PIN
1. KBD Clock
2. GND
3. KBD Data
4. N/C
5. +5V (VCC)
6. N/C
3.6 LIQUID CRYSTAL DISPLAY
3.6.1 GENERAL DESCRIPTION:
Liquid Crystal Display unit is interfaced with micro controller. It is 2
x 16 characters Dot Matrix LCD Controller Drive. LCD unit is low power
consumption. The calculated values like voltage, current, KW, frequency,
Maximum Demand etc. are displayed continuously in the LCD unit.
It is the LCD controller driver for up to 16-character 2-line display
with double height function. It contains microprocessor Interface circuits,
Instruction decoder controller and character generator ROM/RAM and
common and segment drivers. The bleeder resistance generates for LCD
Bias voltage internally.
The CR oscillator Incorporates C and R, therefore no external
components for oscillation are required. The microprocessor Interface
circuits which operate 2MHz frequency can be connected directly to 4/8bit
microprocessor.
The character generator consists of 9,600 bits ROM and 32 x 5
bits RAM. The standard version ROM is coded with 240 characters
including capital and small letter fonts. The 16-common and 80-segment
drive up to 16-character 2-line LCD panel which divided two common
electrode blocks. The rectangle outlook is very applicable to COG.
3.6.2 LCD FEATURES:
Display Data RAM :32 x 8 bits : Maximum 16-character 2line
Display
Character Generator ROM :9,600 bits ; 240 characters for 5 x 8 dots
Character Generator RAM :32 x 5 bits ; 4 Patterns( 5 x 8 dots)
Microprocessor direst accessing to Display Data RAM and Character
Generator RAM
High Voltage LCD Driver :16-common / 80-segment
Duty Ratio :1/16 Duty
Maximum Display Characters ; 32 Characters
Useful Instruction Set Clear Display, Returns Home, Display ON/OFF
Cont, Cursor ON/OFF Cont, Display Blink, Cursor Shift, Character
Shift, Double Height Function.
Power On Reset / Hardware Reset Function
Oscillation Circuit on chip
Bleeder Resistance on chip
Low Power Consumption
Operating Voltage --- +5V
Package Outline --- Bumped Chip
C-MOS Technology
3.1 POWER SUPPLY UNIT
The micro-controller and its other auxiliaries need supply for its
functioning. This is derived from the power supply unit. There are two
power supply terminals. One of them is for the micro-controller unit and the
other for driving the Sampling circuit. The output of this unit is 5V & 9V
respectively.
The circuit diagram is shown in Fig.3.1. Here it consists of a step-
down transformer of 230/12V rating. The 12V AC supply is then connected
to a full wave bridge rectifier. The bridge circuit is designed using the
diodes. The output of bridge rectifier is of pulsating nature. Hence to
smoothen these, a smoothing capacitor is provided.
Then this smoothed out supply is given to two general-purpose
regulator ICs – 7805 & 7809A. These two ICs provide a voltage of 5V to
micro-controller unit and 9V to sampling circuit. All these arrangements are
provided in case no DC source available. In case of its availability, a
separate terminal is provided to connect it directly to the voltage regulators.
9
CIRCUIT DIAGRAM FOR POWER SUPPLY UNIT
230/12 V
VOLTAGE REGULATORVOLTAGE REGULATOR
7805 7809A
TO MICROCONTROLLER
5V DC
9V DC
TO SAMPLING CKT
230V AC SUPPLY
TRANSFORMER
BRIDGE
- +VI G
ND
VO VI GN
D
VO
2200 uF,60 V
220uF, 30V
D0 (LCD)
BT1
3.6V BAT T ERY
12
U6B
4001
5
64
R/W (LCD)
U3
74LS373
3478
13141718
111
256912151619
2010
D0D1D2D3D4D5D6D7
OCG
Q0Q1Q2Q3Q4Q5Q6Q7
VCCGND
RS (LCD)
MEDI UM SPEED
D1 1N4007
U7
74LS373
3478
13141718
111
2569121516192010
D0D1D2D3D4D5D6D7
OCG
Q0Q1Q2Q3Q4Q5Q6Q7
VCCGND
HI GH SPEED
U6A
4001
1
23
147
C3 10ufd
C133pf
record det ect
U5
74LS138
123
645
15141312111097
168
ABC
G1G2AG2B
Y0Y1Y2Y3Y4Y5Y6Y7
VCCGND
U10
74LS373
3478
13141718
111
2569121516192010
D0D1D2D3D4D5D6D7
OCG
Q0Q1Q2Q3Q4Q5Q6Q7
VCCGND
J4
CON4
123456789101112
D7 (LCD)
D4 (LCD)
VCC
D5 (LCD)
Backlight (LCD)
Y111.0592Mhz
VCC(B)
D2 (LCD)D3 (LCD)
R2
10K
record det ect
R110K
RESISTO
R DIP 9
1 2 3 4 5 6 7 8 9
18 17 16 15 14 13 12 11 10
record
record
Enable (LCD)
VCC
D1 (LCD)
LOW SPEED
C233pf
VCC
D2
1N4007
U4
6264
109876543
25242123
2
20262722
1112131516171819
2814
A0A1A2A3A4A5A6A7A8A9A10A11A12
CS1CS2WEOE
D0D1D2D3D4D5D6D7
VCCGND
U1
AT89s529
18 1920
29
30
31
40
12345678
2122232425262728
1011
12
131415
1617
3938373635343332
RST
XTAL2
XTAL1
GND
PSEN
ALE/PROG
EA/VPP
VCC
P1. 0/ T2P1.1/T 2-EXP1.2P1.3P1.4P1.5P1.6P1.7
P2.0/ A8P2.1/ A9
P2.2/A10P2.3/A11P2.4/A12P2.5/A13P2.6/A14P2.7/A15
P3.0/RXDP3.1/T XD
P3.2/I NT O
P3. 3/ INT1P3.4/T OP3. 5/ T1
P3. 6/WRP3. 7/ RD
P0.0/AD0P0.1/AD1P0.2/AD2P0.3/AD3P0.4/AD4P0.5/AD5P0.6/AD6P0.7/AD7
JP1
Keyboard
1
2
3
4
56
D6 (LCD)
L O W S P E E D
P
1 K
1 0 0 K
F A N1 2
21
54
H I G H S P E E D
M C T 2 E2
1
54
1 K
1 M
1 K
1 K
N
6 8 K
56E
M E D I U M S P E E D
1 K
0 . 0 1 M F
1 K
B T1 3 42
1
54
6 8 K
S W 6
S W P U S H B U TTO N
la t c h E N
S W 1 0
S W P U S H B U TTO N
KEY PA
DV C C
S W 1 5
S W P U S H B U TTO N
R 2
2 5 K
V C C
S W 1 2
S W P U S H B U TTO N
S W 9
S W P U S H B U TTO N
U 5
M C M 6 2 6 4
1 09876543
2 52 42 12 3
2
2 02 62 72 2
1 11 21 31 51 61 71 81 9
A 0A 1A 2A 3A 4A 5A 6A 7A 8A 9A 1 0A 1 1A 1 2
C S 1C S 2W EO E
D 0D 1D 2D 3D 4D 5D 6D 7
S W 1 7
S W D P S T
1 3
2 4
R 61 0 kU 4
7 4 L S 3 7 3
3478
1 31 41 71 8
1
1 1
25691 21 51 61 9
2010
D 0D 1D 2D 3D 4D 5D 6D 7
OC
G
Q 0Q 1Q 2Q 3Q 4Q 5Q 6Q 7
VCC
GND
J 1
C O N 1 0
1234567891 0
MICROCONTROLLER INTERFACING WITH HM2007
C 3
0 . 1 m f d
la t c h E N
R 8
1 k
V C C
R 1 1
1 0 k
R 1 2
4 7 K
KEY PA
D
re c o rd
R 7
5 0 k13
2
S W 5
S W P U S H B U TTO N
S W 7
S W P U S H B U TTO N
U 3
H M 2 0 0 7
3 73 63 5
1 1
1 8
3 43 3
2 4
3 2
2 12 22 3
9
1
2345678
1 5
1 0
1 7
1 92 0
3 8
3 13 02 92 82 7
2625
1 6
1 2
1 4
3 94 04 14 24 34 44 54 6
47
4 8
1 3 D 1D O
M R / M W
K 4
S A 1
M EN C 1
S A 7
N C
S A 4S A 5S A 6
K 2
GND
X 2X 1S 1S 2S 3R D YK 1
W A I T
K 3
S A 0
S A 2S A 3
D 2
S A 1 2S A 1 1S A 1 0
S A 9S A 8
GND1
VDD1
D E N
TE S T
C P U M
D 3D 4D 5D 6D 7
V R E FL I N E
M I C I N
VDD A G N D
W L E N
R 3 3 . 9 K
J 4
C O N 4
1234567891 01 11 2
R 1 0
5 0 k13
2
re c o rd d e t e c t
V C C
re c o rd d e t e c t
R 91 k
S W 8
S W P U S H B U TTO N
V C CR 5
5 k
13
2
S W 1 4
S W P U S H B U TTO N
V C C
re c o rd
+
-
U 2 B
L M 3 2 4
5
67
V C C
S W 1 1
S W P U S H B U TTO N
D 3L E D
C 4
0 . 1 m f dQ 1
3.58M
hz
TO MIC
ROCO
NTRO
LLER
+
-
U 2 A
L M 3 2 4
3
21
411J 1
C O N 1 0
123456789
1 0
J 3
m ic
12R 4
1 0 k
S W 1 3
S W P U S H B U TTO N
LCD AND KEYBOARD:
V C C
R S
V C C
R D 3
E N
R D 2
J P 1K e y b o a rd
1
2
3
4
56
R D 5V C CR D 6
V E E G N D
R D 7
R D 0
R 1 3
5 6 0 E
R 1 4
1 K
V C C
R D 1
R E 3
V E E
J 5
C O N 1 6
1234567891 01 11 21 31 41 51 6
R D 4 R E 2
POWER SUPPLY
1
3
2V I N
GN
D
V O U T7 8 0 5
D C S O C K E T
12
0 .1 M F 1 0 M F4 7 0 M F
V C C
ABSTRACT:
Electric motors account for as much as 50% of the total energy use. Because
of the inefficient design and operation of the common fixed-speed motor,
much of this energy is actually wasted. Equipped with controls to vary their
speed and torque to match their workload, major energy savings would be
achieved.
Use of Induction motor in heating, ventilation, and air conditioning
(HVAC) systems has significantly reduced energy consumption and audible
noise while improving comfort and air quality. However, most efforts have
coupled new motors with digital controls, using complex, unit-specific
system designs to make the motor and controls compatible. These custom
digital solutions are not translatable for use with other motors and systems
and are often far more costly than the units they displace.
A new approach, using the optically programmable control, offers a
universal, simple, and low-cost solution for HVAC systems, including those
with 3phase-induction motors.
Cost associated with that directly or indirectly measure the motor speed
makes many existing control designs not production viable. In this project,
we study the challenging task of controlling the speed of induction motor.In
our project that voice will be recognize with in the frequency limit.
BLOCK DIAGRAM
HARDWARE COMPONENTS
Micro-controller
External memory
LCD display
Key pad
3 Phase Induction Motor
DSP HM 2007
Mike
Power supply(5v)