VM Switching Power

CMOS InverterCMOS InverterCMOS InverterCMOS Inverter

OutlineOutline

Quantification of Design Metrics of an inverter

Static (or SteadyStatic (or Steady--State) BehaviorState) Behavior

Dynamic (or Transient Response) BehaviorDynamic (or Transient Response) Behavior

Energy EfficiencyEnergy Efficiency

Nitin ChaturvediNitin Chaturvedi CMOS Inverter

Energy EfficiencyEnergy Efficiency

For velocity saturated deviceFor velocity saturated device


Estimation of NM USING Piecewise lin. approx.Estimation of NM USING Piecewise lin. approx.


Determine g at Vin~VmDetermine g at Vin~Vm


Switching ThresholdSwitching Threshold At VM where Vin = Vout, both PMOS and NMOS

transistors are in saturation (since VDS = VGS)

VVMM ≈≈≈≈≈≈≈≈ rVrVDDDD/(/(1 1 + + rr )) where rr = = kkppVVDSATpDSATp//kknnVVDSATnDSATn

Switching threshold set by the ratio rr , which compares the relative driving strengthsrelative driving strengthsof the


compares the relative driving strengthsrelative driving strengthsof the PMOS and NMOS transistors

GoalGoal:: To set To set VVMM = = VVDDDD//22 (to maximize noise margins), so r ≈ 1

W L( )p

W L( )n

=kn 'VDSAT,n VM −VT ,n −VDSAT,n /2( )

kp 'VDSAT,p VDD − VM −VT ,p −VDSAT,p /2( )[ ]

Switch Threshold ExampleSwitch Threshold Example In our generic 0.25 micron CMOS process, using the

process parameters from Table 3.2, at VVDDDD = = 22..55VV, and a minimum size NMOS device ((W/L)((W/L) nn of of 11..55))

VVTT00(V)(V) γγγγγγγγ(V(V 0.50.5)) VVDSATDSAT(V)(V) k’(A/Vk’(A/V 22)) λλλλλλλλ(V(V--11))

NMOS 0.43 0.4 0.63 115 x 10-6 0.06


NMOS 0.43 0.4 0.63 115 x 10-6 0.06

PMOS -0.4 -0.4 -1 -30 x 10-6 -0.1

115 x 10-6 0.63 (1.25 – 0.43 – 0.63/2)

-30 x 10-6 -1.0 (1.25 – 0.4 – 1.0/2)x x = = 33..55

((WW//LL ))pp = 3.5 x 1.5 = 5.25 for a 5.25 for a VVMM of 1.25 Vof 1.25 V

=(W/L)p

(W/L)n

Example: Simulated ResultsExample: Simulated Results

1.3

1.4

1.5

1.6

1.7

1.8

(V)

11..25 25 VV


100

101

0.8

0.9

1

1.1

1.2

1.3MV

(V)

Wp/W

n

11..25 25 VV

rr = = 33..44

Minimum WidthMinimum Width--toto--Length = 1.5Length = 1.5

Observations IObservations I VM is relatively insensitiveto variations in

device ratio Small Variations of the ratio do not significantly

disturb VTC.

Common Industry Practice to set Wp smallersmallerthan the


Common Industry Practice to set Wp smallersmallerthan the requirement.

Increasing the width of the PMOS moves VMtowards VDD

Increasing the width of the NMOS moves VMtoward GND

2

3

VVOHOH = V= VDDDD

Noise Margins: Determining VNoise Margins: Determining VIHIH and Vand VILIL

NMNMH H = V= VDD DD -- VVIHIHNMNML L = V= VIL IL -- GNDGND

By definition, VIH and VILare where gain

dVdVoutout //dVdV inin = = --11

GainGain g = g = SlopeSlope


0

1

VIL VIHVVinin

A pieceA piece--wise linear approximation of VTCwise linear approximation of VTC

VVOLOL = GND= GND

VVILIL VVIHIH

NMNML L = V= VIL IL -- GNDGND

So high gain in the So high gain in the transition region is transition region is very desirablevery desirable

Slope = gSlope = g

VVMM Approximating: VVIH IH = V= VM M -- VVM M /g/gVVIL IL = V= VM M + (V+ (VDD DD -- VVM M )/g)/g

CMOS Voltage Gain CMOS Voltage Gain

GainGain is a is a strongstrong function of the function of the slopes of the currents in the slopes of the currents in the saturation region, for saturation region, for VVinin = = VVMM

-8

-6

-4

-2

00 0.5 1 1.5 2

VVinin


-18

-16

-14

-12

-10

-8

Determined only by technology parameters, especially Determined only by technology parameters, especially channel length modulation (channel length modulation (λλλλλλλλ). Only designer influence ). Only designer influence through through supply voltagesupply voltageand and VVMM (transistor sizing).(transistor sizing).

Example: VTC and Noise Margin Example: VTC and Noise Margin For a 0.25µm, (W/L)p/(W/L)n = 3.4, (W/L)n = 1.5

(min size) VDD = 2.5V

VVMM ≈≈≈≈≈≈≈≈ 11..25 25 V, V, gg= = --2727..55VVILIL = = 11..2 2 V, V, VVIHIH = = 11..3 3 VV

NMNM = = NMNM = = 11..22

Real ValueReal ValueVVILIL = = 11..03 03 V, V, VVIHIH = = 11..45 45 VVNMNM = = 11..0303, , NMNM = = 11..0505


NMNM LL = = NMNMHH = = 11..22

Output resistance ⇒ Sensitivity of gate output Sensitivity of gate output with respect to noisewith respect to noise

lowlow--outputoutput= = 22..4 4 kkΩΩΩΩΩΩΩΩhighhigh--outputoutput= = 33..3 3 kkΩΩΩΩΩΩΩΩ Preferably as low as possible

NMNM LL = = 11..0303, , NMNMHH = = 11..0505

Observations IIObservations II First-Order Analysis overestimates the gain

Max. gain only 17 at VM →→→→→→→→ VVILIL = = 11..1717VV, , VVIHIH = = 11..3333VV

Piecewise Linear Approximation is too overly optimistic


Major contributor to deviation from the true gain

CMOS inverter is a poor analog amplifier! One of the major differences between analog and

digital designs is that digital circuits operate in the regions of extreme nonlinearityextreme nonlinearity. Well-defined and well-separated high and low signals

1.5

2

2.5

Vou

t(V)

Impact of Process Variation on VTCImpact of Process Variation on VTC

Good PMOSBad NMOS


0

0.5

1

0 0.5 1 1.5 2 2.5

Vin(V)

V

Bad PMOSGood NMOS

Process variations (mostly) cause a shift in the sw itching threshold

Scaling the Supply VoltageScaling the Supply Voltage

1

1.5

2

2.5

0.05

0.1

0.15

0.2


0

0.5

0 0.5 1 1.5 2 2.5

Vin(V)

Reducing Reducing VVDDDD improves Gain…improves Gain…

0

0.05

0 0.05 0.1 0.15 0.2

Vin(V)

But it deteriorates for very low But it deteriorates for very low VVDDDD

Gain=-1

Practical Lower Bound:Practical Lower Bound: VVDDminDDmin > > 2 2 to to 4 4 kt /qkt /q

Observations IIIObservations III

Reducing the supply voltage has a positive impact on the energy dissipationenergy dissipation…

But is also detrimental to the delay of the gatedelay of the gate

DC Characteristic becomes increasingly


DC Characteristic becomes increasingly sensitive to device variations once supply and intrinsic voltages become comparable

Scaling the supply voltage = reducing the swing

Reduce internal noise (e.g., crosstalk)Reduce internal noise (e.g., crosstalk)

More susceptible to external noise that do not scale More susceptible to external noise that do not scale

Inverter Switching Inverter Switching CharaterisitcsCharaterisitcsCharaterisitcsCharaterisitcs

Dynamic BehaviorDynamic Behavior

Delay Definitions (Propagation delay)Delay Definitions (Propagation delay)


Delay DefinitionsDelay Definitions-- Rise and Fall timeRise and Fall time


Delay DefinitionsDelay Definitions--with input slopewith input slope

t t

V in

t

50%

Vout

tf

tpHL tpLH

tr

t

90%

10%

50%


CMOS Inverter Dynamic Behavior CMOS Inverter Dynamic Behavior Transient behavior of the gate is determined by

the time it takes to charge and discharge the load capacitance, CCLL, through on-transistors Delay is a function of load capacitances and transistor

on-resistances


Getting CCLL as small as possible is crucial to the realization of high-performance CMOS circuits Transistor Capacitances Wire Capacitances Fanout

Wire ResistancesWire Resistancesalso become more important.

VDD VDD

VinVout

M2M4Cdb2

C

Cgd12

C

Cg4

C

Vout2

Computing the CapacitancesComputing the Capacitances

Extrinsic Extrinsic


M1 M3Cdb1 Cw Cg3

Interconnect

Fanout

VVoutout22VVinin

VVoutout

CCLL

Simplified ModelSimplified Model

Intrinsic Intrinsic

Finding CFinding Cgdgd: The Miller Effect: The Miller Effect

∆∆∆∆∆∆∆∆VV

M1 and M2 are either in cut-off or in saturation.

The floating gate-drain capacitor is replaced by a capacitance-to-ground (gate-bulk capacitor).

VVoutout

CCgdgd11 VVoutout ∆∆∆∆∆∆∆∆VV


∆∆∆∆∆∆∆∆VV

“A capacitor experiencing identical but opposite vo ltage swings “A capacitor experiencing identical but opposite vo ltage swings at both its terminals can be replaced by a capacit or to ground at both its terminals can be replaced by a capacit or to ground whose value is two times the original value”whose value is two times the original value”

VVinin

M1

∆∆∆∆∆∆∆∆VV22CCgdgd 11

VVinin

M1

Clock charge feed throughClock charge feed through


Diffusion Capacitances: CDiffusion Capacitances: Cdbdb11and Cand Cdbdb22

We can simplify the diffusion capacitance calculations by using a KKeqeqto linearize the nonlinear capacitor to the value of the junction capacitance under zero-bias

CC = = KK CC


0.25 0.25 µµµµµµµµm m ProcessProcess

highhigh--toto--lowlow lowlow--toto--highhigh

KKeqbpeqbp KKeqsweqsw KKeqbpeqbp KKeqsweqsw

NMOSNMOS 0.57 0.61 0.79 0.81

PMOSPMOS 0.79 0.86 0.59 0.7

CCeqeq= = KKeqeqCCj0j0

Extrinsic Capacitances: CExtrinsic Capacitances: Cgg33and Cand Cgg44

Simplification of the actual situation

Assumes all the components of CCgategateare between VVoutout

and GNDGND (or VVDDDD)

Assumes the channel capacitances of the loading gates are constant


gates are constant

The extrinsic, or fan-out, capacitance is the total gate capacitance of the loading gates M3 and M4.

CCfanfan--outout = = CCgategate(NMOS) + (NMOS) + CCgategate(PMOS)(PMOS)

= (= (CCGSOnGSOn+ + CCGDOnGDOn+ + WWnnLLnnCCoxox) + () + (CCGSOpGSOp+ + CCGDOpGDOp+ + WWppLLppCCoxox))

Example: Layout of Two InvertersExample: Layout of Two Inverters

InIn OutOut

MetalMetal11

PMOSPMOS11..125125//00..2525

PolysiliconPolysilicon

VVDDDDAD = Drain Area AD = Drain Area PD = Drain Perimeter PD = Drain Perimeter AS = Source AreaAS = Source AreaPS = Source PerimeterPS = Source Perimeter


00..25 25 µµµµµµµµmm W/LW/L AD AD ((µµµµµµµµmm22)) PD PD ((µµµµµµµµm)m) AS AS ((µµµµµµµµmm22)) PS PS ((µµµµµµµµm)m)

NMOSNMOS 0.375/0.25 0.3 1.875 0.3 1.875

PMOSPMOS 1.125/0.25 0.7 2.375 0.7 2.375

GNDGNDNMOSNMOS

0.375/0.250.375/0.25

PolysiliconPolysilicon λλλλλλλλ = = 00..125125

Minimum Drawn LengthMinimum Drawn Length

Example: Components of CExample: Components of CLL ((00..25 25 µµµµµµµµmm))

CC TermTerm ExpressionExpressionValue Value (fF)(fF)

HH→→→→→→→→LLValue Value (fF)(fF)

LL→→→→→→→→HH

CCgdgd 11 2 2 CCgd0gd0n n WWnn 0.23 0.23

CCgdgd 22 2 2 CCgd0gd0p p WWpp 0.61 0.61

CCdbdb 11 KKeqbpneqbpn ADADnnCCjj + + KKeqswneqswn PDPDnnCCjswjsw 0.66 0.90


CCdbdb 11 KKeqbpneqbpn ADADnnCCjj + + KKeqswneqswn PDPDnnCCjswjsw 0.66 0.90

CCdbdb 22 KKeqbppeqbpp ADADppCCj j + K+ Keqswpeqswp PDPDppCCjswjsw 1.5 1.15

CCgg33 (2 (2 CCgd0ngd0n ))WWnn + + CCoxox WWnnLLnn 0.76 0.76

CCgg44 (2 (2 CCgd0pgd0p ))WWp p + + CCoxox WWppLLpp 2.28 2.28

CCww from extractionfrom extraction 0.12 0.12

CL ∑∑∑∑∑∑∑∑ 6.16.1 6.06.0

Wiring CapacitanceWiring Capacitance

The wiring capacitance depends upon the length and width of the connecting wires and is a function of the fan-out from the driving gate and the number of fan-out gates.

Wiring capacitance is growing in importance


Wiring capacitance is growing in importance with the scaling of technology.

Delay calculationDelay calculationmethod method 11method method 11


Switch Model of CMOS Transistor ModelSwitch Model of CMOS Transistor Model--11

|V G S|

Approximate as a simple RC network

Where, R is given as an equivalent resistance of the NMOS and PMOS devices

C is given as the total lumped Cload capacitance

R o n

|V G S| < |VT ||V G S| > |V T |


CMOS Inverter: Transient ResponseSwitch model

VDD

tpHL = f(Ron .CL)

= 0.69 RonCL

Vout = VDD (1 – e –t / RON

CL ) Vout = VDD (e –t / R

ONC

L )

Vout

V in = VDD

Ron

CL

t

Vout

VDD

RonCL

1

0.5

ln(0.5)

0.36


Inverter Propagation DelayInverter Propagation Delay

Charge

VVDDDD

RRpp Discharge

VVDDDD

“Propagation delay is proportional to the time“Propagation delay is proportional to the time--constant of the constant of the network formed by the onnetwork formed by the on--resistance and the load capacitance” resistance and the load capacitance”

tt pp = = ff ((RRonon , , CCLL) )

ttpHLpHL = = 00..6969RReqneqnCCLL

ttpLHpLH = = 00..6969RReqpeqpCCLL


VVoutout

CCLL

VVin in = = 00

Low to HighLow to High

VVin in = V= V DDDD

CCLL

VVoutout

RRnn

High to LowHigh to Low

To equalize rise and fall times make the on-resistance of the NMOS and PMOS approximately equal.

ttpHLpHL = = 00..6969RReqneqnCCLL

t p =t pHL + t pLH

2

= 0.69CL

Reqn + Reqp

2

Determination of RDetermination of Reqeq


In velocity saturated deviceIn velocity saturated device


CMOS Inverter Driving a Lumped Capacitance Load

• CMOS Inverter can be viewed as a single transistor either charging the Cload or discharging the Cload

– Vin is assumed to switch abruptly

– If Vin switches high, the NMOS Tx discharges Cload while the PMOS Tx turns OFFturns OFF

– If Vin switches low, the PMOS Tx charges Cload while the NMOS Tx turns OFF

• Cload is comprised of

– Cgate due to the gate capacitance of receiving circuits

– Cwire of the interconnect metal

– Cparasitics of the inverter output junctions



Inverter Transient Response Inverter Transient Response ((00..25 25 µm)µm)

1

1.5

2

2.5

3 VVDDDD= = 22..55VVWW//LLnn = = 11..55WW//LLpp = = 44..55RReqneqn= = 13 13 kkΩΩΩΩΩΩΩΩ //11..55RR = = 31 31 kkΩΩΩΩΩΩΩΩ //44..55

ttpLHpLH

SimulationSimulation AnalysisAnalysis


-0.5

0

0.5

1

0 50 100 150 200 250

t(psec)

RReqpeqp= = 31 31 kkΩΩΩΩΩΩΩΩ //44..55

tt pHLpHL = = 3636 psecpsectt pLHpLH = = 29 29 psecpsec

tt pp = (= (3636++2929)/)/2 2 = = 3232..5 5 psecpsectt pHLpHL = = 3939..9 9 psecpsec andand tt pLHpLH = = 3131..7 7 psecpsec

ttpHLpHL

Analysis results is Analysis results is too optimistictoo optimistic ~ ~ 1010% better% better

Inverter Propagation Delay, RevisitedInverter Propagation Delay, Revisited

4.5

55.5

(nor

mal

ized

)

ttpHLpHL = = 00..69 69 RReqneqn CCLL

= = 00..6969((33CVCVDDDD)/()/(44IIDSATnDSATn))

To see how a designerdesignercan optimize the delay of a gate, we have to expand Req in the delay equation.


11.5

22.5

3

3.54

0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4

VDD(V)

t p(n

orm

aliz

ed)

= = 00..6969((33CVCVDDDD)/()/(44IIDSATnDSATn))

tpHL ≈ 0.52CL

W L( )n′ k nVDSATn

Delay as a function of VDelay as a function of VDDDD

4

4.5

5

5.5

(no

rma

lize

d)

0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.41

1.5

2

2.5

3

3.5

VDD

(V)

t p(n

orm

aliz

ed

)


tpHL ≈ 0.52CL

W L( )n′ k nVDSATn

Minimizing Propagation DelayMinimizing Propagation Delay Reduce CReduce CLL

Keep the drain diffusion as small as possible

Increase W/L ratio of the transistorIncrease W/L ratio of the transistor Most powerful and effective way

Watch out for selfself--loadingloading!


Watch out for selfself--loadingloading! When the intrinsic capacitance dominates

Increase Increase VVDDDD

Trade off energy efficiency for performance

Very minimal improvement above a certain level

Reliability concerns enforce a firm upper bound on VDD

PMOSPMOS--toto--NMOS RatioNMOS Ratio So far PMOS and NMOS have been sized such that

their Req’s match (ratio of 3 to 3.5) symmetrical VTC equal high-to-low and low-to-high propagation delays

If speed is the only concern, reducereducethe width of


If speed is the only concern, reducereducethe width of the PMOS device! widening the PMOS degradesdegradesthe tpHL due to larger

parasitic capacitance

ββββββββ = (= (WW//LL ))pp/(/(WW//LL ))nn

rr = = RReqpeqp//RReqneqnresistance ratio of identically-sized PMOS and NMOS

βopt = r 1+ CW

Cdn2 + CCgn2

Method Method 2 2 Method Method 2 2 AVERAGE CURRENT THROUGH LOADAVERAGE CURRENT THROUGH LOAD


VDD

tpHL = C L (V50% -VDD)

Iav

CMOS Inverter Propagation Delay

Vout

V in = V DD

CLIav tpLH = C L (V50%-VOL)

I av


I av, HL = ½ [ic(VIN=VOH, VOUT= VOH)]+ ic(VIN=VOH, VOUT= V50%)]

Average Current Calculations

I av, LH = ½ [ic(VIN=VOL, VOUT= V50%)]+ ic(VIN=VOL, VOUT= VOL)]


Method is Simple

Drawback------neglects variation of capacitance Drawback------neglects variation of capacitance load during the entire simulation


MethodMethod--33

Differential equation approachDifferential equation approachDifferential equation approachDifferential equation approachaccurateaccurate


Propagation delay times can be found more accurately

By solving the state equations associated with the output node

Differential equation associated with output node

Capacitance current is function of output voltage







ttpHLpHL



ttpLHpLH



Impact of Rise Time on DelayImpact of Rise Time on Delay

(nse

c)0.35

0.3

0.25

t pH

L(

0.2

0.15

trise (nsec)10.80.60.40.20


Consider Input slopeConsider Input slope


Design for PerformanceDesign for Performance--(speed)(speed)

Keep capacitances small

Increase transistor sizes

watch out for self-loading!

Increase V Increase VDD


Power ConsumptionPower ConsumptionPower ConsumptionPower Consumption

Where Does Power Go?Where Does Power Go?

Static Power Consumption

Ideally zero for static CMOS but in the real world..

Leakage Current LossLeakage Current Loss Diodes and Transistors constantly losing charge


Dynamic Power Consumption

Charging/Discharging CapacitancesCharging/Discharging Capacitances Major Source of Power Dissipation in CMOS Circuits

DirectDirect--Path Current Loss Path Current Loss Short circuit between Power Rail during Switching

VVinin VVoutout

CCLL

VVDDDD

Dynamic Power ConsumptionDynamic Power Consumption

iiVDDVDD(t)(t)


PPdyndyn = Energy/cycle * = Energy/cycle * ff clkclk

CCLL

Energy Supplied/Cycle =Energy Supplied/Cycle = iVDD(t)VDDdt0

∞

∫ == CCLL * * VVDDDD22

Energy Stored/Cycle = Energy Stored/Cycle = iVDD(t)vout(t)dt0

∞

∫ == CCLL * * VVDDDD2 2 / / 22

== CCLL * * VVDDDD22 * * ff clkclk

Switching ActivitySwitching Activity Power dissipation does not depend on the size of

the devices but depends on how often the circuit is switched. Switching ActivitySwitching Activity≡ frequency of energy-consuming

transition = ff 00→→→→→→→→11


transition = ff 00→→→→→→→→11

PPdyndyn = = CCLL * * VVDDDD22 * * ff 00→→→→→→→→11

= C= CLL * * VVDDDD22 * * PP00→→→→→→→→11 * * ff clkclk

= C= Ceffeff * * VVDDDD22 * * ff clkclk

ClockClock

Gate outputGate output

Effective CapacitanceEffective Capacitance CC effeff = Average Capacitance Switched per clock cycle

PP00→→→→→→→→11= = 00..2525,,ff00→→→→→→→→11= = ff clk clk / / 44

Example: Power Dissipation of an ICExample: Power Dissipation of an IC Consider a 0.25 micron chip, 500 MHz clock, average

load cap of 15fF/gate (for fanout of 4), 2.5V supply.

Dynamic Power consumption per gate is

PPdyndyn = C= Ceffeff * * VVDDDD22 * * ff clkclk

= 15 fF * (2.5 V)2 * 500 MHz


~ ~ 47 47 µµµµµµµµWW

With 1 million gates and a switching activity of 25%

Dynamic Power of the entire chip is

PPchipchip = = PPdyndyn * * NNgg * * PPaa (Ng = no. of gates)

= 47 µW/gate * 106 gates * 0.25

= = 1111..75 75 W ~ W ~ 12 12 WW

Lowering Dynamic PowerLowering Dynamic Power

PPdyndyn= = CCLL VVDDDD22 PP00→→→→→→→→1 1 ff

Quadratic EffectQuadratic EffectLowering Physical CapacitanceLowering Physical Capacitance

Supply Voltage:Supply Voltage:Has been dropping with successive generations

Capacitance:Capacitance:Function of fan-out, wire length, transistor sizes


PPdyndyn= = CCLL VVDDDD22 PP00→→→→→→→→1 1 ff

Clock frequency:Clock frequency:Increasing…Increasing…

Activity factor:Activity factor:How often, on average, do gates switch?

Reduction can be obtained only at Logic Reduction can be obtained only at Logic and Architectural Abstraction Levelsand Architectural Abstraction Levels

Short Circuit Power ConsumptionShort Circuit Power Consumption

CCLL

VVinin VVoutout

VVDDDD

IIscsc

tt scsc


Finite slope of the input signal causes a Finite slope of the input signal causes a direct current direct current pathpath between between VVDDDD and and GNDGND for a short period of time for a short period of time

during switching when both the NMOS and PMOS during switching when both the NMOS and PMOS transistors are conducting (active).transistors are conducting (active).

CCLL

EEscsc = = tt scsc VVDDDD IIpeakpeak PP00→→→→→→→→11

PPscsc = = tt scsc VVDDDD IIpeakpeak ff00→→→→→→→→11

Short Circuit Currents DeterminatesShort Circuit Currents Determinates

tt = Duration of the slope of the input signal


ttscsc= Duration of the slope of the input signal

II peakpeakdetermined by the saturation current of the PMOS and NMOS transistors

which depend on their sizes, process technology, temperature, etc.

strong function of the ratio between input and output slopes a function of CCLL

IIscsc ≈≈≈≈≈≈≈≈ 00 IIsc sc ≈≈≈≈≈≈≈≈ IImaxmax

Impact of CImpact of CLL on Pon Pscsc

VVinin VVoutout

CCLL

VVDDDD

VVinin VVoutout

CCLL

VVDDDD


LargeLarge capacitive loadcapacitive load SmallSmall capacitive loadcapacitive load

CCLL CCLL

Output fall time significantly larger than input rise time.

Output fall time substantially smaller than input rise time.

II peakpeakas a Function of Cas a Function of CLL

1.5

2

2.5

x 10-4

CL = 20 fF

C = 100 fF

Short circuit dissipation is minimized by

When load capacitance is small, Ipeak is large.


-0.5

0

0.5

1

0 2 4 6

time (sec)time (sec)x 10-10

CL = 100 fF

CL = 500 fF

500 500 psec input slopepsec input slope

is minimized by matching the rise/fall times of the input and output signals - slope slope engineeringengineering .

PPscscas a Function of Rise/Fall Timesas a Function of Rise/Fall Times

When load capacitance is small (tsin/tsout > 2 for VDD > 2V) the power is dominated by PPscsc

4

5

6

7

8 VDD= 3.3 V

VDD = 2.5 V


normalized wrt zero input normalized wrt zero input riserise--time dissipationtime dissipation

If VVDDDD < < VVTnTn + |+ |VVTpTp|| then Psc is eliminated since both devices are never never on at the same timeon at the same time.

0

1

2

3

0 1 2 3 4 5tt sinsin /t/t soutsout

VDD = 1.5V

W/LW/Lpp = = 11..125 125 µµµµµµµµm/m/00..25 25 µµµµµµµµmmW/LW/Lnn = = 00..375 375 µµµµµµµµm/m/00..25 25 µµµµµµµµmmCCLL = = 30 30 fFfF

Static (Leakage) Power ConsumptionStatic (Leakage) Power Consumption

PPstatstat= V= VDDDD IIstatstat

Drain junction Drain junction leakageleakage

VVoutout = = VVDDDD

VVDDDDVVDDDD

dominant dominant factor.factor.


leakageleakage

SubSub--threshold currentthreshold currentGate leakageGate leakage

All leakages increase exponentially with temperature Junction leakage doubles every 9C

Sub-threshold current becomes more concern in vDSM The closer the threshold voltage to zero, the larger the

leakage current at VGS = 0V (when NMOS off)

Leakage as a Function of VLeakage as a Function of VTT

1.E-04

1.E-02

Continued scaling of supply voltage and the subsequent scaling of threshold voltage will make sub-threshold conduction a dominant component of power dissipation.

An An 9090mV/decade VmV/decade VTTrollroll--off off -- so each so each


1.E-12

1.E-10

1.E-08

1.E-06

1.E-04

0 0.2 0.4 0.6 0.8 1

VGS (V)

ID (A

)

VT=0.4VVT=0.1V

rollroll--off off -- so each so each 255255mV increase in mV increase in VVTT gives gives 3 3 orders of orders of magnitude reduction magnitude reduction in leakage (but in leakage (but adversely affects adversely affects performance)performance)

24 24 ÅÅ

11..2 2 VV

CLCL013 013 HSHS

29 29 ÅÅ

11..5 5 VV

CLCL015 015 HSHS

42 42 ÅÅ42 42 ÅÅ42 42 ÅÅ42 42 ÅÅTToxox (effective)(effective)

2 2 VV11..8 8 VV11..8 8 VV11..8 8 VVVVdddd

CLCL018 018 HSHS

CLCL018 018 ULPULP

CLCL018 018 LPLP

CLCL018 018 GG

TSMC Processes Leakage and VTTSMC Processes Leakage and VTFrom MPR, June From MPR, June 20002000, pp. , pp. 19 19 –– Performance of various TSMC processes Performance of various TSMC processes ((G genericG generic , , LP low powerLP low power , , ULP ultra low powerULP ultra low power , , HS high speedHS high speed ))


8080

00..25 25 VV

1313,,000000

920920//400400

00..08 08 µµm m

5252

00..29 29 VV

11,,800800

860860//370370

00..11 11 µµm m

4343141422223030FET Perf. FET Perf. (GHz)(GHz)

00..40 40 VV00..73 73 VV00..63 63 VV00..42 42 VVVVTnTn

30030000..151511..60602020IIoffoff (leakage) (leakage) ((ρρρρρρρρA/A/µµµµµµµµm)m)

780780//360360320320//130130500500//180180600600//260260IIDSatDSat (n/p) (n/p) ((µµµµµµµµA/A/µµµµµµµµm)m)

00..13 13 µµm m 00..18 18 µµm m 00..16 16 µµm m 00..16 16 µµm m LL gategate

Exponential Increase in LeakagesExponential Increase in Leakages

100

1000

10000

00..10 10 µµµµµµµµmm




Leakage currents double every Leakage currents double every 10 10 degree increase in temperaturedegree increase in temperature


1

10

30 40 50 60 70 80 90 100 110

Temperature (C)

The Leakage Power is six orders of magnitude smalle r than The Leakage Power is six orders of magnitude smalle r than the dynamic power (at room temperature)the dynamic power (at room temperature)

Energy and Power EquationsEnergy and Power Equations

ff 00→→→→→→→→11 = = PP00→→→→→→→→11 * * ff clockclock

EE = = CCLL VVDDDD22 PP00→→→→→→→→11 + + tt scsc VVDDDD IIpeakpeak PP00→→→→→→→→11 + + VVDDDD IIleakageleakageTTclockclock


Dynamic powerDynamic power(~(~9090% today and % today and

decreasing decreasing relatively)relatively)

ShortShort--circuit powercircuit power(~(~88% today and % today and

decreasing absolutely)decreasing absolutely)

Leakage powerLeakage power(~(~22% today and % today and

increasing)increasing)

PP = = CCLL VVDDDD22 ff00→→→→→→→→11 + + tt scsc VVDDDD IIpeakpeak ff00→→→→→→→→11 + + VVDDDD IIleakageleakage

PowerPower--Delay and EnergyDelay and Energy--Delay ProductDelay Product

PowerPower--delay product (PDP) = delay product (PDP) = PPavav* * ttpp = (= (CCLLVVDDDD22)/)/22

PDP is the average energy consumedper switching event (Watts * sec = Joule)

Lower power design could simply be a slower design

EnergyEnergy--delay product (EDP) = PDP * delay product (EDP) = PDP * tt = = PP * * tt 22


EnergyEnergy--delay product (EDP) = PDP * delay product (EDP) = PDP * ttpp = = PPavav* * ttpp22

EDP is the average energy consumed multiplied by the computation time required

Takes into account that one can trade increased delay for lower energy/operation (e.g., via supply voltage scaling that increases delay, but decreases energy consumption)

EnergyEnergy--Delay PlotDelay Plot

EDP = αCL2VDD

3

2 VDD −VTE( )

Where VTE = VT+VDSAT/2

5

10

15

EnergyEnergy--DelayDelay

0.25 micron


VDDopt = 3

2VTE

VVTnTn = = 00..43 43 V, V, VVDSATnDSATn = = 00..63 63 V, V, VVTEnTEn = = 00..74 74 VVVVTpTp = = --00..4 4 V, V, VVDSATpDSATp = = --1 1 V, V, VVTEpTEp = = --00..9 9 VV

VVTETE ≈ (≈ (VVTn Tn +| +| VVTpTp |)/|)/2 2 = = 00..8 8 V V

VVDDoptDDopt = (= (33//22)*)*00..8 8 = = 11..2 2 VV

0

5

0.5 1 1.5 2 2.5

Vdd (V)

DelayDelayEnergyEnergy

11..1 1 VV

Observation VIObservation VI Voltage Dependence of the EDP

Higher Supply Voltages reduce delay, but harm the energy.

Vice Versa for low voltages

VDDopt simultaneously optimizes performance (delay) and energy


and energy

For submicron technologies with VT in the range of 0.5 V, VDDopt ~ 1V.

VDDopt does not necessarily represent the optimum voltage for a given design problem

Goal of the design (speed or power)determinates the supply voltage

ENDENDENDEND

Some Interesting QuestionsSome Interesting Questions

What will cause this model to break?What will cause this model to break?

When will it break?When will it break?

Will the model gradually slow down?Will the model gradually slow down?

Power and power density


Power and power density

Leakage

Process Variation

Documents

VM Switching Power