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7/29/2019 vlsi m.e
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GOJAN SCHOOL OF BUSINESS & TECHNOLOGYEDPALAYAM, REDHILLS, CHENNAI-52.
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
MODEL EXAMINATION
VL 9212 VLSI DESIGN TECHNIQUES
M.E. - Applied Electronics
Time : Three hours Maximum : 100 Marks
Answer ALL questions
PART A (10 2 = 20 Marks)
1. Give two reasons as to why polysilicon is used as Gate material in VLSI.
2. What is pinch - off? What is its effect?
3. Give Noise margin 0 and Noise margin 1 of a CMOS gate.
4. Mention the drawbacks of pass transistor logic.
5. What is body effect? Show the same for PMOSFET.
6. Placement and routing have to be optimal in VLSI design, why?
7. What is DFT? What is its philosophy?
8. Indicate any two ways to reduce power in a CMOS IC.
9. Differentiate concurrent statements from sequential statements.
10.
List the operators used in Verilog.
PART B (5 16 = 80 Marks)
11. (a) (i) With the help of structure and transfer characteristic differentiate
the working of an enhancement type N-MOSFET from depletion
type N-MOSFET. (8)
(ii) Write the expression for the threshold voltage of a NMOSFET.
Briefly explain all the terms. (8)
Or
(b) (i) Explain any two secondary effects of a MOSFET. (6)
(ii) Illustrate the fabrication steps involved in a twin-tub CMOS IC.
(10)
12. (a) (i) Compare the design of a 4 : 1 MUX built using transmission gates
with the one built using static CMOS gates. (8)
(ii) Implement the following Boolean gates using static CMOS
structures.2-I/P AND gate, 2-I/P OR gate, 2-I/P Ex-OR gate
and 2-I/P Ex-NOR gate. (8)
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Or
(b) (i) Explain the working of a domino logic. (6)
(ii) What is meant by transmission gate? Design a 2 1 mux using
transmission gate. (10)
13. (a) (i) Derive an expression for dynamic power dissipation of a CMOS IC.
Comment on the same. (10)
(ii) What do you mean by transistor sizing? Clearly answer as to why is
it done? (6)
Or
(b) (i) Discuss the different scaling models that are prevalent in VLSI.
Illustrate them with examples. (10)
(ii) What are the limitations of scaling? Explain. (6)14. (a) (i) Starting from basics, design and explain a 4 bit high speed adder.(8)
(ii) Explain the working of a 4 4 multiplier with examples. (8)
Or
(b) (i) What is Physical design in VLSI? Elaborate the same. (8)
(ii) For the circuit shown in Fig. 14 (b), generate, test vectors to detect
the s-a-1 and s-a-0 faults shown. Also indicate the other faults
covered by the test vectors generated. (8)
s-a-1
A
B
Y
C
D s-a-0
E
Fig. 14 (b)
15. (a) (i) Explain functions with suitable examples, with respect to Verilog.(8)
(ii) Write a Verilog Code for 3 to 8 decoder using gate level primitives.(8)
Or
(b) (i) Write a Verilog Code for +ve edge triggered D-Flip-Flop using data
flow modeling. Show the waveforms also. (8)
(ii) Explain the complete flow diagram of digital system design using
Verilog (HDL).(8)