Upload
arthicse
View
221
Download
0
Embed Size (px)
Citation preview
8/6/2019 Vlsi Intro 2010
http://slidepdf.com/reader/full/vlsi-intro-2010 1/33
Intr d ti n t VL I D i nIntr d ti n t VL I D i n
• Typical Design Flow• High Level Design• Low Level Desi n
S. Choomchua Ph.D.
Intro. to VLSI Design S. Choomchuay //KMITL 1
8/6/2019 Vlsi Intro 2010
http://slidepdf.com/reader/full/vlsi-intro-2010 2/33
o e o pso e o ps
ea
Circuit Desi n Applications
Fabrication
Intro. to VLSI Design S. Choomchuay //KMITL 2
8/6/2019 Vlsi Intro 2010
http://slidepdf.com/reader/full/vlsi-intro-2010 3/33
VL I D i n hall n VL I D i n hall n
• Increasing productivity yield
• Shorter design cycle with more product feature-• Design reuse enable• Increase flexibilit to desi n chan es
• Faster exploitation of alternative architecture• Faster exploitation of alternative libraries
• etter as er es gn au t ng ver cat on
Intro. to VLSI Design S. Choomchuay //KMITL 3
8/6/2019 Vlsi Intro 2010
http://slidepdf.com/reader/full/vlsi-intro-2010 4/33
SemiconductorVacuum tube
Discrete Small IC LSI VLSI
Metal Base PCB Chip
10-50 / 6"x9" 10-50 /2x2 mm 10000-100000/1x1 cm
Intro. to VLSI Design S. Choomchuay //KMITL 4
ear
8/6/2019 Vlsi Intro 2010
http://slidepdf.com/reader/full/vlsi-intro-2010 5/33
Design Tools
&
simulation
Layout (pattern)
Design & synthesis
.
Fabrication
Sim. Tools Mask Set
Process Assembly
Material & IC Chi sPackaging
Intro. to VLSI Design S. Choomchuay //KMITL 5
8/6/2019 Vlsi Intro 2010
http://slidepdf.com/reader/full/vlsi-intro-2010 6/33
Switch 1
upp y o age
Switch 2Control
u r r e n t
C
Switch 3 Switch 4
Switch
Intro. to VLSI Design S. Choomchuay //KMITL 6
8/6/2019 Vlsi Intro 2010
http://slidepdf.com/reader/full/vlsi-intro-2010 7/33
Bipolar
Speed = ?
Dissipation = ?Dissipation = ?
MOS MOS xe xe
(BiCMOS)(BiCMOS)
Intro. to VLSI Design S. Choomchuay //KMITL 7
8/6/2019 Vlsi Intro 2010
http://slidepdf.com/reader/full/vlsi-intro-2010 8/33
Mask Set
Protective Selective Implant
Front End
icing on ing o ing
Intro. to VLSI Design S. Choomchuay //KMITL 8
ac n
8/6/2019 Vlsi Intro 2010
http://slidepdf.com/reader/full/vlsi-intro-2010 9/33
3"- 8"
Silicon Wafer
PROCESSClean Room
CVDrea men Implanter
Stepper
E-Beamnv ronment Machines
&Furnace
Intro. to VLSI Design S. Choomchuay //KMITL 9
8/6/2019 Vlsi Intro 2010
http://slidepdf.com/reader/full/vlsi-intro-2010 10/33
Process Ke word 1Process Ke word 1
x a onx a on siosio22
- Thermal
-CVD
ImplantationImplantation
Intro. to VLSI Design S. Choomchuay //KMITL 10
Annealing
8/6/2019 Vlsi Intro 2010
http://slidepdf.com/reader/full/vlsi-intro-2010 11/33
Process Ke word 2Process Ke word 2
o o ograp yo o ograp yUV light, Electron Beam
PhotoresisPhotoresis
SiOSiO22
MASK
SiPatterning
Developed
Etching &Strip off
Intro. to VLSI Design S. Choomchuay //KMITL 11
8/6/2019 Vlsi Intro 2010
http://slidepdf.com/reader/full/vlsi-intro-2010 12/33
B havi ral L v l f A tra ti nB havi ral L v l f A tra ti n
System
Algorithm
RTL
Transistor
Intro. to VLSI Design S. Choomchuay //KMITL 12
8/6/2019 Vlsi Intro 2010
http://slidepdf.com/reader/full/vlsi-intro-2010 13/33
es gn oma nes gn oma n
Abstract Structure Physical
Design DomainLevel of
Abstraction
ArchitectureDesign Algorithm
System StructuralSynthesis
RTL Level
StructuralDesignLo ic
RTL
yn es s
Logic LevelSynthesis Verification
DesignLayout
Design (Syn)
Logic
Gate
Verification
er ca on
Intro. to VLSI Design S. Choomchuay //KMITL 13
8/6/2019 Vlsi Intro 2010
http://slidepdf.com/reader/full/vlsi-intro-2010 14/33
8/6/2019 Vlsi Intro 2010
http://slidepdf.com/reader/full/vlsi-intro-2010 15/33
VL I L w L v l D i n VL I L w L v l D i n
Cell Library DesignLogic
Design
DRC
Simulation
LayoutDesign
Extraction
SimulationLogic Level
Model
SimulationCircuit
Design
MasksDeviceDevice Level
Model
Intro. to VLSI Design S. Choomchuay //KMITL 15
8/6/2019 Vlsi Intro 2010
http://slidepdf.com/reader/full/vlsi-intro-2010 16/33
Top Down DesignTop Down Design
System Level
Board Level
Chi LevelRTL
yn es s
Layout
Synthesis
Intro. to VLSI Design S. Choomchuay //KMITL 16
8/6/2019 Vlsi Intro 2010
http://slidepdf.com/reader/full/vlsi-intro-2010 17/33
HDL Synthesis ToolsHDL Synthesis Tools
VHDL
• 1980 , o ro ect• 1983 IBM and TI joint project
• 1987 DoD and IEEE1076 Standards• 1993 Revise of IEEE1076• 1996 Extend to 1076.3 and 1076.4
Verilog• 1981 CAE software launched by Dateway Design Auto.
(founded by Phil Mooreby)• 1983 Release of Verilog HDL
• 1987 Extended to Verilog XL• 1989 Verylog XL is widely used• 1990 Cadence bought Gateway• 1995 Verilo --> IEEE1364
Intro. to VLSI Design S. Choomchuay //KMITL 17
8/6/2019 Vlsi Intro 2010
http://slidepdf.com/reader/full/vlsi-intro-2010 18/33
Synthesis OptimisationSynthesis Optimisation
Criteria
Synthesis
(Translation)Area
&Timing
Optimisation
moduleConstraints
Netlist
Intro. to VLSI Design S. Choomchuay //KMITL 18
8/6/2019 Vlsi Intro 2010
http://slidepdf.com/reader/full/vlsi-intro-2010 19/33
nth i n trainnth i n train
• Library process factor• O eratin volta e
• Area
- max area • Operating temperature • Timing
- fan-in, fan-out- I/ & o/ loadin ca .
- Max.clock frequency• Power- .
• Testability- Full or partial scan-
Intro. to VLSI Design S. Choomchuay //KMITL 19
8/6/2019 Vlsi Intro 2010
http://slidepdf.com/reader/full/vlsi-intro-2010 20/33
8/6/2019 Vlsi Intro 2010
http://slidepdf.com/reader/full/vlsi-intro-2010 21/33
La t D i nLa t D i n
Conventional static gate(Complementary)
A B
Y
• PMOS chain is a complementaryarran ement of N-Chain
A
C• Output is taken at the center
C B AY +⋅= )(
Intro. to VLSI Design S. Choomchuay //KMITL 21
8/6/2019 Vlsi Intro 2010
http://slidepdf.com/reader/full/vlsi-intro-2010 22/33
La t D i nLa t D i n
Actual MOS Devices
Gate (Control)
(N)(N)
Silicon(P)
= ? micronGate
Intro. to VLSI Design S. Choomchuay //KMITL 22
8/6/2019 Vlsi Intro 2010
http://slidepdf.com/reader/full/vlsi-intro-2010 23/33
La t D i nLa t D i n
MOS Parameters
Tox
Silicon(P)
(N)(N)
L
W/L defines MOS currentK = Process Transconductance
T GSD −=
)]([21
LW
OX C K μ=
Intro. to VLSI Design S. Choomchuay //KMITL 23
8/6/2019 Vlsi Intro 2010
http://slidepdf.com/reader/full/vlsi-intro-2010 24/33
Layout DesignLayout DesignW Channel Width
MOS Device Modelanne eng
AD, AS Drain,Source AreaPD,PS Drain,Source Periphery
(N)(N)
W
Substrate (P) AS ADG
Cgs C dC
L
vS v
D
iD
Intro. to VLSI Design S. Choomchuay //KMITL 24v
Sub
8/6/2019 Vlsi Intro 2010
http://slidepdf.com/reader/full/vlsi-intro-2010 25/33
A t al M D vi A t al M D vi
Inverter, X-section
I/P
GND VddO/P
p pn np n
P WellN-Type Substrate
Intro. to VLSI Design S. Choomchuay //KMITL 25
8/6/2019 Vlsi Intro 2010
http://slidepdf.com/reader/full/vlsi-intro-2010 26/33
8/6/2019 Vlsi Intro 2010
http://slidepdf.com/reader/full/vlsi-intro-2010 27/33
LL--Edit Tri k itEdit Tri k it
NOR 2-input (N well)
• Only one active, We haveto say N-active or P-active
• Poly Contact or ActiveContact (both to metal)
• Port names need for
extraction simulation• DRC needs
Intro. to VLSI Design S. Choomchuay //KMITL 27
8/6/2019 Vlsi Intro 2010
http://slidepdf.com/reader/full/vlsi-intro-2010 28/33
L w L v l D i n DRL w L v l D i n DR
What does it say?
• Minimum features size(Layers & wire)2λx2λ
• Minimum spacing between2 objects
base
2λ
Intro. to VLSI Design S. Choomchuay //KMITL 28
8/6/2019 Vlsi Intro 2010
http://slidepdf.com/reader/full/vlsi-intro-2010 29/33
L w L v l D i nL w L v l D i n
Stick Diagram
• Color stick objects represent layer and routing
Intro. to VLSI Design S. Choomchuay //KMITL 29
8/6/2019 Vlsi Intro 2010
http://slidepdf.com/reader/full/vlsi-intro-2010 30/33
Low Level DesignLow Level Design
Layer design guide
LayerLayer RR CC CommentsComments
Global Signal
Lon wirin
Polysilicon Low Moderate High IR drop
Diffusion Moderate High High Capacitance
Intro. to VLSI Design S. Choomchuay //KMITL 30
8/6/2019 Vlsi Intro 2010
http://slidepdf.com/reader/full/vlsi-intro-2010 31/33
Low Level DesignLow Level Design
MOS as RC
W A t
L LLL
W Wt A
n
s AB
1
;
1
=ρ=ρ
ρ===
r
SubG
WL
C
)(0εε
=−
NMOSW
nq
pqnq
n
pn
)(1
μ=
μμ
OX T
WLCg
)(ε=
Intro. to VLSI Design S. Choomchuay //KMITL 31
8/6/2019 Vlsi Intro 2010
http://slidepdf.com/reader/full/vlsi-intro-2010 32/33
Low Level DesignLow Level Design
Complement Logic Switch
chainRP
NMOS
chainR
n
nCg
Intro. to VLSI Design S. Choomchuay //KMITL 32
8/6/2019 Vlsi Intro 2010
http://slidepdf.com/reader/full/vlsi-intro-2010 33/33
L w L v l D i nL w L v l D i n
STD Cell Style
• All Cells are same height• Width can be varied• Power rails (left-right)• ,
• Routing channels outside
Intro. to VLSI Design S. Choomchuay //KMITL 33