Darshan Institute of Engineering & Technology-Rajkot Department of Electronics & Communication

GTU Examination Question Bank

Sem.: 6th Sem Subject: VLSI Technology and Design (161004)

Sr. No

Exam Year

Question Marks

Chapter 1 Introduction: 1

May 2011 Discuss VLSI design flow in detail 04 Dec. 2011 Explain VLSI Design flow using Y-chart. 07 Summer 2013

Discuss VLSI Design flow in detail. 07

2 Summer 2012

Answer the following: (I) Compare Semi-custom and Full custom VLSI design style (II) Discuss general architecture of FPGA

07

3 Summer 2012

Define and briefly discuss following: 1. Yield

01

4 Winter 2012

Discuss following approaches (with examples) used to reduce complexity of IC design: 1. Hierarchy, 2. Regularity, 3. Modularity, and 4. Locality

07

5 Summer 2013

Modularity in VLSI design 01

6 Summer 2013

List VLSI design styles and discuss FPGA 3.5

7 Winter 2013

Discuss following criteria which are considered to measure the quality of chip design. 1. Testability 2. Yield and manufacturability 3. Reliability 4.Technology updateability

7

Chapter 2 Fabrication of MOSFET 8 May 2011 Discuss fabrication process of NMOS transistor. 07 9 Dec-2011 Explain the fabrication steps of nMOS transistor with necessary

figures. 07

10 Summer 2012

Discuss process flow for the fabrication of an n-type MOSFET on p-type silicon

07

11 Summer 2012

Define or briefly discuss following: Negative photoresist Positive photoresist

02

12 Winter 2012

Why do we need isolation between MOS transistors fabricated on a single chip? Explain etched field-oxide isolation and LOCOS isolation techniques with diagrams

07

Winter 2013

Why do we require device isolation between MOS transistors that comprise an IC? Explain LOCOS isolation technique with necessary diagrams.

04

Summer 2013

Basic steps of the Local Oxidation of silicon (LOCOS) process to create oxide isolation around active areas.

3.5

13 Winter 2012

Draw layout of CMOS Inverter and indicate minimum eight layout rules of your choice in terms of .

07

14 Winter What is the difference between positive photoresist and negative 03

2013 photoresist? Which is commonly used in the manufacturing of high density integrated circuits?

Chapter 4. MOS Inverters: Static characteristics: 15 May 2011 Design of a depletion-load NMOS inverter:

ncox= 30 A/V2 , VT0 = 0.8 V (enhancement-type), VT0 = - 2.8 V,(depletion-type), = 0.38 V1/2, |2 F| = 0.6 V, VDD = 5 V. 1) Determine the (W/L) ratios of both transistors such that:

i) the static (DC) power dissipation for Vin = VOH is 250 W, and ii) VOL = 0.3 V.

2) Calculate VIL and VIH values, and determine the noise margins

07

16 May 2011 Draw circuit of resistive load inverter. Derive VIH , VIL ,VOL and VOH for resistive load inverter.

07

Summer 2013

Draw the Resistive Load Inverter circuit. Derive critical voltage points VOH,VOL,VIL and VIH for Resistive Load Inverter circuit.

07

Winter 2013

Draw circuit of resistive load inverter. Derive VIL,VIH and VOL for resistive load inverter.

07

17 May 2011 Consider a CMOS inverter circuit with the following parameters: VDD = 3.3 V, For NMOS VTO,n = 0.6 V, n Cox=60 A/V2 , (W/L)n=8 For PMOS VTO,p = - 0.7 V, p Cox=25 A/V2 , (W/L)p=12. Calculate noise margin and Vth of the circuit.

07

18 Dec-2011 Design a resistive load inverter with R = 1k, such that VOL = 0.6V. The enhancement-type nMOS driver transistor has the following parameters: VDD = 5.0V VTO = 1.0 V = 0.2 V1/2 = 0 nCox = 22.0 A/V2 a. Determine the required aspect ratio, W/L. b. Determine VIL and VIH.

07

19 Dec-2011 Draw the inverter circuit with depletion type nMOS load. Mention the operating regions of driver and load transistors for different input voltages. Derive critical voltage points VOH, VOL and VIL for depletion- load nMOS inverter.

07

20 Summer 2012

Draw the CMOS Inverter circuit and Voltage Transfer Characteristic (VTC) for different operating regions of the nMOS and pMOS transistors. Derive critical voltage points VIL,VIH.

07

Winter 2013

For a CMOS inverter circuit, derive its critical voltage points VIL and VIH.

07

21 Summer 2012

Consider a CMOS Inverter circuit with the following parameters: VDD=3.3V, VTO,n=0.6V, VTO,p= -0.7V, kn=200 A/V2, kp=80 A/V2 Calculate the noise margin of the circuit.

07

22 Summer 2012

Define and briefly discuss following: 4. Noise margin

01

Summer 2013

Briefly discuss following: 5. Noise Margin High

01

23 Winter 2012

Derive expressions for VIH

and VIL

for CMOS Inverter. 07

Winter 2013

For a CMOS inverter circuit, derive its critical voltage points VIL and VIH.

07

24 Summer 2013

Consider a resistive-load inverter circuit with VDD =5 V, Kn=10A/V2 , VTO=0.8V, RL=200k,and W/L=4. Calculate the critical Voltages (VOH, VOL, VIL & VIH) on the VTC and find the noise margins of the circuit.

07

25 Winter 2013

Consider the CMOS inverter, with the following device parameters: nMOS VTO,n = 0.6 V nCox = 60 A/V2 pMOS VTO,p = -0.8 V pCox = 20 A/V2 Also: VDD = 3V, = 0. a. Determine the (W/L) ratios of the nMOS and the pMOS transistor such that the switching threshold is Vth = 1.5V. b. Calculate noise margin.

07

Chapter 5 : MOS Inverters Switching characteristics and Interconnect Effects 26 Winter

2013 Explain Elmore delay calculation method for complex RC network. Derive the formula for Elmore delay DN.

07

27 Summer 2013

Derive expression for propagation delay times tPHL and tPLH. 07

Winter 2012

Define propagation delay and derive expression for PHL

for CMOS Inverter. Assume ideal step as an input to CMOS Inverter

07

28 Winter 2012

Obtain expression for switching power dissipation in CMOS Inverter circuit. Assume ideal step as an input to CMOS Inverter. Under what constraints, derived expression can be applied to any CMOS logic circuit?

07

29 Summer 2012

Draw input and output waveform during high to low transition of output for a CMOS inverter and derive expression for PHL

07

Dec 2011 Draw input and output waveforms during high to low transition of output for a CMOS inverter. Derive expression for PHL.

07

30 May 2011 How will you calculate propagation delay times PLH and PHL for CMOS Inverter?

07

Chapter 5 Combinational MOS Logic Circuits 31 Winter

2013 Explain two input depletion load NOR gate and derive the necessary equations for the same.

07

32 Winter 2013

Draw CMOS implementation of D latch with two inverters and two CMOS TG gates. Explain its working.

07

33 Winter 2013

For XOR function, draw following implementations. 3. CMOS transmission gate(TG)

02

34 Summer Draw circuit for CMOS two input NOR gate. Derive VTH of the 07

2013 same. 35 Summer

2013 Discuss CMOS transmission gate for all operating regions and plot equivalent resistance of CMOS transmission gate as a function of output voltage.

07

36 Winter 2012

Draw two-input CMOS NOR gate and obtain expression for switching threshold voltage (v

th). Assume that both NMOS

transistors are identical. Similarly, PMOS transistors are also identical.

07

37 Winter 2012

Justify importance of transmission gate. Draw six-transistor CMOS transmission gate implementation of the XOR function. Verify its functionality.

07

38 Summer 2012

Implement following Boolean functions using transmission gates

03.5

39 Dec 2011 Realize the following Boolean function using CMOS TG. F = AB + AC + ABC.

02

40 Dec 2011 Implement the following Boolean function using CMOS. F =[(C+D+E) . (B+A)]. Find a equivalent CMOS inverter circuit for simultaneous switching of all inputs, assume that (W/L)p = 15 for all pMOS transistors and (W/L)n = 10 for all nMOS transistors.

07

41 May 2011 Explain CMOS transmission gate. 07