Microsoft Word - VLSI Design Lab2_v1.docVLSI Design Lab 2 Due to 4/6 pm 12:00
Setup 1. %cd T181p6m_ads %cp .cdsinit ../ (run calibre) %icfb&
1.1 Tool=> Library manager 1.2 File=>New=>Library 1.3 library nameOK
3. File=>New=>Cell View
ciw
1.5 T181p6m_ads
Create Schematic 2.4 libraryFile=>New=>Cell View 2.5 Tool=>Composer SchematicCell Name
3 Add component library (analogLibbasic)schematic viewChoose: Add->Instancewindow,BrowseanalogLib
,. Note Tsmc or Umcpcell. ,Add->Pin,but must define input terminal and output terminal pin.(vdd and gnd inoutput)Add->Wire

)Lchannel length Wchannel width
5 Syntax check CHECKLVS(Layout V.S Schematic )
,Choose: Design->Check and Save CIW
messageschematic
Example 2no error --->
Layout Editor 1. libraryFile=>New=>Cell View Cell View => Virtuoso
2. Setup Option => Display
3. Create ()
k -Ruler Shift+k - r -Rectangle () o -contactvia() m -Move c -Copy s -Stretch Shift+z -Zoom out Ctrl+z -Zoom in f -Fit Edit shift+f & ctrl+f -switching instance view
Key+F3 – 3.1 Create =>Instance
layout Cell : Creative->Instance,BrowseCellpcell 3.2 Creative->Label (schematicpinCalibreLVSlayout
label)Notepoly 4. Layout XL Auto-drawing pcell layout but not include wire connection Tool=>Layout XL
: METAL1
METAL1
Invoke a schematic window First choose a MOS form the Schematic window then Create=>Pick from Schematic then drag to layout window.
Verification Using Calibre
Design Rule Checking(DRC) 1. Using Calibre DRC Tool Calibre=>Run DRC
1.DRC rule 2.DRC 3.run DRC(optional)
1.1 Cancel Load Runset File 1.2 DRC rule /home/raid1_2/userd/d93020/T181p6m_ads /DRC/Calibre_DRC-1_3A2_5C_modify /T18_Calibre_DRC_13A25C_modify Load () 2. Inputs gds Export form layout view
(gdslayout)
3. Outputs
3. Run DRC Run DebugDRC REV Erase error highlight error drc summary file*.drc.summary
error description
error position
error number
NOTE DRC ERRORDENSITYERROR

Layout v.s. Schematic 1. Calibre Interactive Using Calibre LVS Tool Calibre=>Run LVS
1.LVSrule 2.LVS 3.run DRC(optional)
schematic
layout
LVS report () Incorrectness Correctness
Netlist from schematic
Netlist from layout
Layout Parameter Extraction 1.2136 /home/raid1_2/userd/d93020/T181p6m_ads/LPE/Calibre_LPE-1_3A/T18_Calibre_L PE_13A.13a include /home/raid1_2/userd/d93020/T181p6m_ads/LPE/Calibre_LPE-1_3A/rules (UltraEdit) 1.1 Calibre Interactive Using Calibre LPE Tool Calibre=>Run PEX
LPE rule /home/raid1_2/userd/d93020/T181p6m_ads/LPE/Calibre_LPE-1_3A/T18_Calibre_L PE_13A.13a Load () 2. Inputs gdsexport from layout viewerschematic
4.Run PEX
Layout 1.layer Cap Lock 2.undo3 Options=>User Preference
Building Basic Logic Cell 1. It can make the layout fast, regular ,and clear. Easy to debug 2. It like cell base design. Only need connection Example (MCLA) Schematic view
Layout viewThe red blocks are instances.
Create symbol from Schematic 1. scmematiccell
symbolschematic
3. Pin Specification pin
Cross View Check
3-input nand gatefullcustom design flow
hspice simulation .subckt nand3 a b c out wp=2u wn=1u ld=0.18u mp1 out a vdd vdd pch w=wp l=ld mp2 out b vdd vdd pch w=wp l=ld mp3 out c vdd vdd pch w=wp l=ld mn1 out a 1 gnd nch w=wn l=ld mn2 1 b 2 gnd nch w=wn l=ld mn3 2 c gnd gnd nch w=wn l=ld .ends nand3
Submission Requirement layout view & schematic view*.drc.summary, *.lvs.report, *.sp, *.pex, *.pxi wordZIP
VLSI_LAB2_BXXXXXXXX_.zip genius@access.ee.ntu.edu.tw