VLSI Design and Test Automation Research

F. Beyette, H. Carter, W. B. Jone, C. Purdy, K. Tomko, R. Vemuri, P.

Welsey

Focus

• Design, analysis, and test of integrated circuits and systems.

• Digital, analog, mixed signal and mixed technology microchips and systems.

• Applications to computing, communication, and embedded processing.

• VLSI systems education.

n+n+S

GD

+

DEVICE

CIRCUIT

GATE

MODULE

SYSTEM

Existing Research Strengths

• Design– Digital and analog microchip design– FPGA-based reconfigurable systems– Mixed signal, mixed technology systems

(opto-electro-mechanical microsystems)– Test architectures, design-for-testability– Low power design

• Design Automation and CAD– Automated design synthesis– Discrete and continuous simulation– Test pattern generation– Analysis, benchmarking, experiment design– Hardware description languages, VHDL– Distributed/parallel computing and CAD methods

We are working very hard !We are working very hard !ResultResult

Visibility and Impact

• 150 journal, 410 conference papers since 90

• 3 books and 30 book chapters• 7 Best Paper awards• Editorships

– IEEE Transactions on VLSI– IEEE Potentials – Transactions on Modeling and Simulation– Journal of VLSI Design– IEEE Computer (guest)

• General/program/panel chairs of numerous conferences (30 since 95)

Industry Employers of Our Graduates

• Intel• Xilinx• Motorola• Hewlett-Packard• Honeywell• Sun Microsystems• LSI Logic• Digital-Compaq-Intel• Lucent• AT & T• Qualcom

• Cadence• Synopsys• Mentor Graphics• NeoLinear• FTL Systems• Simplex• Matrix• Symbios• Fore Systems• Oracle• Microsoft• EDAptive

• 45 PhDs and 120 Masters graduated since 1990.• 30 PhDs and 45 Masters in progress.

Past Sponsors of Our Research

• DARPA (MTO, ITO, DSO)• AFRL (SN, IF, and Mantech at WPAFB and GAFB)• Semiconductor Research Corporation• National Science Foundation• National Security Agency• DAGSI• NASA• Industries (GE, TI, Xilinx, TRW, Raytheon, Sun,

MTL, FTL, EDAptive….) • Several SBIRs (8 Phase II and many more Phase

I)

Total $15M since 1990.

Government Lab Collaborators

• Sandia National Lab• NASA Langley • NASA Lewis• AFRL, Sensors Directorate• AFRL, Information Directorate• Rome Research Institute, GAFB• JPL

Educational Grants/Contracts

• NSF (VLSI minor program and VLSI Design and Test Lab)• NSF (combined research and education)• DARPA (RASSP educator and facilitator contract)• DARPA (ADA education)• Several graduate fellowships (SRC, OBR etc.)• MOSIS (About 10K/year since 1991 for microchip

fabrication. About 250 microchips, each with 15,000-20,000 transistors, were fabricated and tested.)

• Xilinx (hardware donations, over $300K)• Altera (hardware and software donations)• Cadence, Synopsys, Xilinx etc. (CAD software donations

worth several $M)

Multichip Synthesis

• How to partition a large specification and synthesize a multichip design using the available package options?

Die and package options.

Multichip Synthesis System, MSS

• Viper multichip module design was automatically synthesized using the MSS CAD system.

• Viper is a RISC microprocessor.

• To accomplish this, the MSS system was successfully integrated with many commercial CAD systems.

VASE Mixed Signal Synthesis System

Functional Specification in VHDL-AMS

Performance Goals

Analog/DigitalPartitioning

AnalogSynthesis

Digital Synthesis (DSS)

Layout Integration

Analog ComponentLibrary

Digital ComponentLibrary

Analog Layout Digital Layout

Mixed Analog-Digital Layout

• VASE research nominated for Best Paper Award at DATE’99

Multi-Channel Voice Transmitter-ReceiverSynthesized Using VASE

Philip A. Wilsey

Experimental Computing Lab

A Plugin Architecture for Linking CAD Tool Backends to a VHDL

Frontend

SAVANT

WARPEDSimulation

Kernel

TyVIS VHDLSimulation

Kernel

TyVISCompliant C++

ScramVHDL

AnalyzerIIR

SAVANTTransmogrifi

er

IIR (Reduced Form)

SAVANTCloning Step

w/ TyVIS extension

SAVANT

SAVANT: VHDL analyzer/code generatorTyVIS: C++ Code Generator & VHDL simulation kernelWARPED: Discrete-event simulation kernel

VHDL '93VHDL-AMSVHDL-2001

MPI/TCP/BIP

Cloned IIR

w/ TyVIS C++Code Generator

Extension by Inheritance

IIRExtensionIIR

IIRBase

IIRScram

IIR

IIRScram

IIRBaseExtended fornew backend

analysis purposes

Extensibility through Cloning

PluginOutput

LibraryForm

AIREPlugin

ExtendedAIRE

SAVANTAnalyzer

VHDLSource

CloningStep

The Clone Step

IIR_ArchitectureDeclarationscram

IIR_TextLiteral

scramIIR_Statemen

tListscram

IIR_ProcessStatementscramIIR_ProcessState

mentscramIIR_ProcessState

mentscram

Module-LoadedFactory

IIR_ArchitectureDeclaration

publish_xml

IIR_TextLiteral

publish_xmlIIR_Statemen

tListpublish_xml

IIR_ProcessStatement

publish_xmlIIR_ProcessState

mentpublish_xmlIIR_ProcessState

mentpublish_xml

Prof. C. Purdy-- Digital Design Research

Circuits & Systems Design Laboratory

1. Sensor data processing and systems-on-a-chip

2. Evaluation of CAD algorithms

--Improved accuracy and speed

--Smaller circuits

Network on Chip (NoC)

• On chip communication with a network is very simple and reliable

• Routers are used to direct the flow of communication

• Predictable electrical parameters enable high performance circuits

• Enables the use of fault tolerant wiring and protocols

• Facilitating reuse with a universal interface and also extending the reuse to network

MEMS BIST and BISR Research Goals: 1. Develop robust and efficient BIST solution for capacitive MEMS2. Implement redundancy built-in self-repair feature into MEMS

device, thus greatly enhance the yield rate and in-field reliability

BISR comb accelerometer

Capacitance partition of dual-mode BIST solutionMites crawl on MEMS gears

Importance of Embedded Memory Testing / Diagnosis / Repair

Source – ITRS 2001 – Percentage of Logic Forecast in SoC Design

Year Node(nm)

% Area New Logic

% Area Reused Logic

% Area Memory

1999 180 64 16 202002 130 32 16 522005 100 16 13 712008 70 8 9 902014 35 2 4 94

Interconnect Noise Testing for High-Speed Deep sub-Micron VLSI circuits

• Deal with signal integrity problem due to cross-coupling capacitance and inductance in long interconnects

• Circuit speed in the level of GHZ• Hard to accurately model the behavior of

coupling capacitance and inductance for deep-submicron, high-speed (GHZ) circuits

• Try to use pseudo-exhaustive built-in self-test to solve the problem