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7/30/2019 VL500
1/10
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National Institute of Electronics andInformation Technology, Calicut
CDS/CA/7.5.1/F 40/R3
COURSEPROSPECTUS
NameoftheGroup:VLSIDesignGroup
Nameof
the
Course:
PG
Diploma
in
VLSI
&
Embedded
Hardware
Design
CourseCode:VL500
StartingDate:19th
August2013
Duration:24weeks
PREAMBLE: VLSI (Very Large Scale Integration) has emerged as a very significant
technology toprovide tremendousquantumofprocessingpowerand functionality to
modern electronic systems. Ubiquitous Computing, Communication and Embedded
Systems,basedonVLSIarerevolutionizingeverywalksofourdailylives,beitConsumer
Electronics,Communication,Computing,Automation,SpaceApplication,Defenseandto
just about everything. With the advancements in silicon processing technologies for
MEMS,NEMSandRFcomponents,manyoftheformerlyexternalcomponentscannow
be integrated into a single SystemonChip which has resulted in a dramatic
improvements in performance while achieving reduction in the size, cost and power
consumption .Complexity in such systems arises not only from the diversity of the
technologies,fromsensorsandactuatorsandRFfrontendstobasebandDSPsoftware,
etc., thatmustbe integratedonchipcomprisingof tensofmillionsof transistors,but
also from the fact that such systemsmustbe increasingly built from parts thathave
beendesignedseparatelyandusingdifferenttoolsandflows.
OBJECTIVEOFTHECOURSE:ThePGDiploma inVLSI&EmbeddedHardwareDesign is
intendedto
impart
training
in
designing
complex
embedded
systems
using
reusable
Intellectual Property (IP) Cores as building blocks and employing hierarchical design
methods.Emphasisoftheteachingcurriculum isondesignmethodologyandpractical
applications. The course contents have been designed keeping in view the emerging
trendsinneedsforskilledmanpower.
Thecurriculumhasbeendesignedinconsultation withindustry andacademicexperts
andour strategicpartners, tomap the skill setsanddesignmethodologies,which is
high in demand in VLSI & Embedded Systems industries. Our students have been
successfullyplaced in reputedproductcompanies andwe enjoy the trustofmany
reputed
companies,
who
have
entered
into
strategic
alliances
with
us.
OUTCOMEOFTHECOURSE:Thiscourse is frequentlyupdated insynchronizationwith
the industry to provide the trainees indepth knowledge and skills required by
Embedded&VLSImarketsaroundtheglobe.Itprovidescomprehensiveunderstanding
aboutthefundamentalprinciples,methodologiesandindustrypractices.
Thisuniquelyhybridcoursemakes the successfulparticipants readilyemployable in
multiplerolesavailableinbroadspectrumofrelevant industries.Forpeopleinterested
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National Institute of Electronics andInformation Technology, Calicut
CDS/CA/7.5.1/F 40/R3
inentrepreneurshipsthiswouldbeanexcellentlaunchpad.Inadditionthecoursealso
servesasaconcreteplatformfor peopleinvolvedinapplicationresearch,consultancy
andhighendproduct development inbothindustryandacademia.
COURSESTRUCTURE:TheVL500containsninemodules.Thestudentsare required to
doaprojectworkinanyoneofthemodularareas,foraperiodof8weekstobeeligible
forissueofPGDiplomainVLSIDesign.
VL500 ModuleName Duration
VL501 AdvancedDigitalDesign 3weeks
VL502 VHDL LanguageandCodingforSynthesis 3weeks
VL
503
Verilog
Language
and
Coding
for
Synthesis
3
weeks
VL504 CMOS LogicDesign 1week
VL505 EmbeddedControllerBasedProduct Design 2weeks
VL506 ProgrammableSoC 1week
VL507 FPGADesignMethodologyandPrototyping 2weeks
VL508 RTL Verification 1week
VL509
Project
8weeks
OTHERCONTENTS
a. Course Fees: For SC/ST Category Applicants : Total Fee payable is Rs.3,500.00/*(Allinclusive, singlepayment.*ConditionsApply).
GeneralCategoryApplicants:TotalFeepayableisRs.76,410.00(allinclusive)
andcanbepaidinlumpsumORinmaximumofthreeinstallmentsasgivenbelow
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National Institute of Electronics andInformation Technology, Calicut
CDS/CA/7.5.1/F 40/R3
PAYMENTSCHEDULEOFFEESIN03INSTALLMENTSBYGENERALCATEGORYSTUDENTS
Installment
No
Amount(Rs) DueDateandremarks
First
35,000.00
7thAugust
2013
Duedateforthe students inthefirstselection listhave
to pay the first installment fee for taking provisional
admission
Second 25,000.00 19th
August2013(TheDayofcounseling)
Thestudents intheadditionalselection listhavetopay
boththefirst&secondinstallmentsoffeetogetheronor
beforethisdate
Third 16410.00 28th
September2013
TotalFees 76,410.00 (Allinclusive)
b. ELIGIBILITY: M.E/M.Tech/BE/B.Tech in Electronics/ Electronics &Communication/ Electrical/ Instrumentation/Computer Science/IT or M.Sc
(Electronics/CS). Diploma students may also be considered. Graduates with
appropriateexperienceandfinalyearstudents#alsomayapply
#Finalyearstudentshavetoincludethecopiesofcoursecompletioncertificate
of their qualifying degree/ diploma or copies of the mark lists up to the last
semester/year.Onthedateofcounseling/admission,he/shemustproducethe
originalsofcoursecompletioncertificate/marklistsuptothelastsemester/year
examination.
c. NUMBEROFSEATS:40SC/ST
candidates
and
Persons
with
disabilities
are
eligible
for
seat
reservation
andrelaxationintheminimummarksforeligibility.
d. HOWTOAPPLY:Procedure forOnline application: Students can apply online by filling up the
online application form. The students are first required to obtain the DD for
Rs.1000.00 towards advance deposit. The students are required to fill the
detailswithregardstotheDD/JournalNumber,Dateandamount.Thestudents
arerequestedtonotedowntheirregistrationnumberallottedafterpressingthe
"Submit" button and forward the demand draft mentioning their name, their
onlineregistration
number
and
course
code
(i.e.;
VL500),
on
the
back
side
of
the
DD.Online registrationsnotcontaining theadvancedepositdetailswillnotbe
consideredforprocessing.
Procedure forapplyingoffline using theprintcopyof Application form:The
studentscandownloadandprinttheapplicationformfromourwebsiteandfill
the particulars and forward the same to the Training Officer along with the
requisitefee,asmentionedabove.
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National Institute of Electronics andInformation Technology, Calicut
CDS/CA/7.5.1/F 40/R3
FilledinapplicationformsandDemandDraft(mentionthenameofthestudent,name
ofthecourseappliedfor[ie;VL500:PGDiplomainVLSI&EmbeddedHardwareDesign]
andcontactnumberonthebacksideoftheDD), shouldbesentto:
TheTrainingOfficer
NationalInstituteofElectronicsandInformationTechnologyCalicut
P.B.No.5,NITCampus(Post)
CALICUT,Kerala.PIN673601
Thenameofthecourseapplied for (i.e. ;VL500:PGDiploma inVLSI&EmbeddedHardware
Design) should be super scribed on the top of the cover in which the application form is
forwarded
MODEOFPAYMENT:(Any1of3optionsgivenbelowmaybeusedtopaythefees)
1Demand
Draft
to
be
drawn
in
favor
of
Director,
NIELIT,
Payable
at
State
Bank
of
India,
CalicutNITBranch(2207).TheDDshouldreachherebeforethelastdatetoapply.
2
Through any branch of SBI (where this format is accepted) using the pay in slip
available in our web site (http://www.calicut.nielit.in/course/payinslip.pdf). The
originalcounterfoilshouldreachherebeforethelastdatetoapply.
3 The fees can be paid directly into our account from any bank where core banking
facilityisavailable.Thedetailsrequiredfordirectpaymentareasgivenbelow.
SavingsAccountNo: 31329537747
AccountName Director,NIELIT,Calicut
BankName:
SBI,
NIT
Chathamangalam
BankCode: 2207
IFSCNo: SBIN0002207
MICR: 673002012
The depositor should obtain the UTR Number/Journal No from the branch while
depositingcashdirectlyintoouraccount.Depositorshouldalsoobtainthecounterfoil
dulyfilledupandsignedbythestaffwithsealofthebankthroughwhichtheamount
wasdeposited.The followingdetailsshouldreachherebeforethe lastdatetoapply,
[email protected]@calicut.nielit.in
1. NameoftheDepositor2. NameoftheStudent3. DateofPayment4. AmountDeposited5. NameofBank/branchthroughwhichamountdeposited6. PurposeCourseID(VL500)AdvanceDeposit/InstallmentFeeetc.7. ProofofDeposit(counterfoil/acknowledgementinoriginal)
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National Institute of Electronics andInformation Technology, Calicut
CDS/CA/7.5.1/F 40/R3
8. UTR/JournalNumberThecounterfoilinoriginalcarryingtheUTR/JournalNumberissuedbythebankmust
beproduced
by
the
applicant
on
the
day
of
counseling
to
our
accounts
department
for
reconciliationandthereceiptissuedbytheaccountsdepartmentmustbekeptsafe.
The Institutewillnotbe responsible foranymistakesdonebyeither thebank
concernedorbythedepositorwhileremittingtheamountintoouraccount.
e. SELECTIONOFCANDIDATES:Candidateswillbeselectedbasedontheirmarksintheir qualifying examination subject to eligibility and availability of seats.
Selectionofcandidateswhohavecompletedthecoursebutexpectingtheresults
shall be based on the availability of seats. All selected candidates shall be
intimatedoftheirselectionbyemailalone.The listofselectedcandidatesshall
bepublishedinourwebsite
Theadmissiontothecourseshallbebasedonthefollowingcriteria:1. Shouldhavepassedtheeligibilitycriteriaasmentionedabove.Selectionlistofstudentswillbepreparedandpublishedinourwebsiteasfollows.
First selection listwillbepreparedbasedon theapplications receivedonorbefore
25th
July2013.
Additional selection listwill be preparedbasedon the applications receivedonor
before07th
August2013andexcludingtheapplicants, included inthe firstselection
list.
f. TEST/INTERVIEW(IFAPPLICABLE):NotApplicableg. COUNSELING/ADMISSION:19thAugust2013h. ADMISSIONPROCEDURE:
Students who have been selected for counseling/admission are required to
reporttoNIELITontheprescribeddayby9:30hrsalongwiththefollowing
1.AttestedCopiesofProofofAge,Qualifications,etc
2.OriginalCertificatesoftheabove
3. Two copies of passport size photographs and one stamp size photograph for
identity
card.
4.SC/STCertificateinEnglish/Hindionly(ifapplicable)
5.IncomeCertificateinEnglish/Hindionly (ifapplicable)
6. Proof of Payment(s) made (counterfoils in original containing the UTR/Journal
Number,dulystampedbythebankstaff)
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National Institute of Electronics andInformation Technology, Calicut
CDS/CA/7.5.1/F 40/R3
The students on reaching the NIELIT are required to meet the Front Office
Councilor (FOC). The FOC then directs the student to theCourseCoordinator.
The student gets the enrollment form verifiedby theCourse Coordinator and
thenmeets
the
FOC
who
shall
direct
the
student
to
the
Accounts
section
for
paymentoffees.Astudentisthusadmitted.
i. DISCONTINUING THE COURSE: No fees under any circumstances shall berefunded in the event of a student discontinuing the course. A student can
however,beeligible formodule certificates (applicableonly for courseswhich
provide formodular admission)whichhehas successfullycompletedprovided
hehaspaidtheentirecoursefees.
j. COURSETIMINGS:Theclassesandlabsarefrom9.30amto12.30pmand1.45pmto5.00pmMondaytoFriday.
k. LOCATIONANDHOWTOREACH:NIELITCalicutislocatedveryneartoNIT(REC)campusandisabout22Kmsfrom
the Calicut (Kozhikode) city. A number of buses [Buses to NIT via
Kunnamangalam]areavailable from "PalayamBusStandorKSRTCBusStand".
Ourstop iscalled"CEDT/Pandrandu" & isonestopbeforeNIT.Thebus fare is
Rs.15/ fromCalicutCitytoNIELITanditisontherightsideoftheroad.
Calicut(Kozhikode) iswellconnectedbyRail,RoadandAirformdifferentparts
ofthecountry.TheclimaticconditionsinCalicutareperhapsoneofthebestin
India throughout the year. The maximum and minimum temperatures range
between35
and
20oC.
The
cool
breeze
further
adds
to
the
comfort.
l. COURSEENQUIRIES:Students can enquire about the various courses either on telephone or by
personalcontactbetween9.15A.M.to5.15P.M. (Lunchtime1.00pm to1.30
pm).
ContactDetails
VL500CourseCoordinator 9995427802/04952287266.Extn:244
CourseCoordinatorsemail [email protected]
TrainingOfficer 04952287266/2287268
TrainingOfficersEmail: [email protected]
OfficeFax 0495 2287168
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National Institute of Electronics andInformation Technology, Calicut
CDS/CA/7.5.1/F 40/R3
m. IMPORTANTDATESLast date for receiving completed
applicationforms
First selection list will be prepared
basedontheapplicationsreceivedon
orbefore25th
July2013.
The additional selection list will be
prepared based on the applications
receivedonorbefore7th
August2013,
andexcludingtheapplicants,included
inthefirstselectionlist.
Publication of first selection list in the
Websitehttp://www.calicut.nielit.in/
26th
July2013.
Last datefor takingprovisional admission
bypaying thefirst installment offees,for
applicantsinthefirstselectionlist
7th
August 2013
Publication of additional selection list in
ourwebsite(iftherearevacantseats)
08th
August 2013
Counselingdate 19th
August2013
ClassCommencementdate 20th
August2013
Payment of first installment of fees for
applicantsinfirstselectionlist
7th
August 2013
Paymentof
second
installment
fees
for
applicantsinfirstselectionlist
Onor
before
19th
August
2013
Paymentofthird installmentfees Onorbefore28th
September2013.
n. PLACEMENT:Wehaveaplacementcell,whichprovidesplacementassistancetostudentswhoqualifyourcourses.Partiallistofourpaststudents,placedisgiven
inthewebsite
o. HOSTELFACILITIES:Hostel accommodation is available for boys and girls on daily or monthly
chargeablebasis.
The
hostel
fee
varies
from
Rs.
700.00
to
Rs.
1300.00
(for
boys)
permonthandRs.1000.00toRs.1400.00(forGirls)permonthdependingonthe
locationofaccommodation.However, students are required topay thehostel
feesforthedurationofthecourseforwhichtheyareseekingadmissionatthe
timeofjoiningthecourse.
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National Institute of Electronics andInformation Technology, Calicut
CDS/CA/7.5.1/F 40/R3
p. CANTEENFACILITIES:The Institute has a canteen functioning at the main campus and food at
reasonable ratesisavailableforbreakfast,lunch,anddinner.
q. LABFACILITIESAltera&XilinxDevelopmentBoards&TrainerKits
XilinxISE,AlteraQuartusII,NIOSIITrainerKits
ASICDesign&VerificationtoolsfromSynopsys
CompleterangeofSimulation,SynthesisToolsfromMentorGraphics
FPGADesignandVerificationTools
ASICDesignVerificationTools&HardwareSoftwareCoverificationTools
ICNanometerDesignTools(Backendtools)&SystemModelingTools
DigitalStorage&MixedSignalOscilloscopes,
LogicAnalyzer&SMDReworkstation
r. COURSECONTENTS:1.AdvancedDigitalDesign
a. CombinationalCircuitDesignb. SequentialCircuitDesignc. DesignofcontrollerandDatapathunitsd. StateMachinese. ControllerDesignusingFSMs&ASMsf. DesignExamples&CaseStudies
2.VHDL LanguageandCodingforSynthesis
a. LanguageConstructs,Datatypesb. DesignStylesc. BehavioralModeling,DataflowModelingd. StructuralModelinge. GenericsandConfigurationsf. Subprogramsandoverloadingg. PackagesandLibrariesh.
Advanced
features
of
VHDL
i. TestBenchDesignandCodingj. Synthesisissuesk. MiniProjectandCaseStudies
3.Verilog LanguageandCodingforSynthesis
a. IntroductiontoVerilogHDL&HierarchicalModelingConceptsb. LexicalConventions&DataTypes
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National Institute of Electronics andInformation Technology, Calicut
CDS/CA/7.5.1/F 40/R3
c. SystemTasks&CompilerDirectivesd. Modules,PortsandModuleInstantiationMethodse. GateLevelModelingf. DataflowModelingg. BehavioralModelingh. RTLDesignandLogicSynthesisandSynthesisissuesi. DesignVerificationusingTestbenchesj. MiniprojectandCaseStudies
4.CMOSLogicDesign
a. MOSFundamentalsb. MOSSwitches&Designsc. TransmissionGatesd. Inverter DC,ACCharacteristicse. CombinationalandSequentialLogicf. IntroductiontoLayoutTools
5.EmbeddedControllerBasedProductDesign
a. Introduction:QualityConcepts,b. ProductDevelopmentProcess&IndustrialDesignc. BasicElectronics,Test&MeasurementEquipmentsd. PCBDesignandEMCGuidelinese. 8051Architecturef. CProgrammingBasics&EmbeddedCg. DevelopingprogramsforEmbeddedProductsh. DebuggingToolsi. PeripheralInterfacing:ADC,LCD,SerialPort,LEDs/Relays,Buzzerj. CaseStudyk. DesignSyndicate
6.ProgrammableSoC
a. IntroductiontoProgrammableSoCb. PSoC DesignersIDEc. DesignexamplesusingPSoCs
7. FPGADesignMethodologyandPrototyping
a. IntroductiontoProgrammableLogicandFPGAsb. PopularCPLD &FPGAFamiliesc. ArchitectureofpopularXilinxandAlteraFPGAsd. FPGADesignFlowAlteraQuartusIIe. FPGA DesignFlowXilinxISEf. ImplementationDetails.
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National Institute of Electronics andInformation Technology, Calicut
CDS/CA/7.5.1/F 40/R3
g. AdvancedFPGADesigntipsh. LogicSynthesisforFPGAi. Placement&Routingj. StaticTimingAnalysisk. DesignproblemsusingXilinxPlatformsl. DesignproblemsusingAlteraPlatformsm. CaseStudiesonFPGABasedimplementationsn. IPReuseMethodologyo. SoftIPvsHardIPp. IPDesign Process&SystemIntegrationwithreusableIP
8.RTLVerification
a. FunctionalVerificationConceptsb. Simulators,CoverageandMetricsc. IntroductiontoVerificationMethodologiesd. Testingstrategy DirectedandrandomTestinge. TestCasesVsTestBenchesf. VerificationComponents(Drivers,Checkers,Monitors,
Scoreboardsetc)
g. Casestudyof aVerificationIP9.Project
Thefollowingtextsdonotformpartoftheprospectus:
ThisapprovalisvalidforuploadingtoNIELIT,Calicutwebsiteaswell.
SignatureoftheCourseCoordinator:
SignatureofTrainingOfficer:
Approved/NotApproved
Director
Guidelines:
1.AllTextinItalicsaretobeenteredbythecoursecoordinator
2.TheCourseProspectustobeputtoDirectorforapprovalthroughTrainingOfficerbefore
issue.