Vivado Design Suite · 1 day ago · HDMI GT Controller v1.0 LogiCORE IP Product Guide Vivado Design Suite PG334 (v1.0) March 5, 2021

HDMI GT Controller v1.0

LogiCORE IP Product GuideVivado Design Suite

PG334 (v1.0) March 5, 2021

https://www.xilinx.com

Table of ContentsChapter 1: Introduction.............................................................................................. 4

Features........................................................................................................................................4IP Facts..........................................................................................................................................5

Chapter 2: Overview......................................................................................................6Navigating Content by Design Process.................................................................................... 6Core Overview..............................................................................................................................6Applications..................................................................................................................................8Unsupported Features................................................................................................................8Licensing and Ordering.............................................................................................................. 9

Chapter 3: Product Specification......................................................................... 10Performance.............................................................................................................................. 11Resource Use............................................................................................................................. 12Port Descriptions.......................................................................................................................12Register Space........................................................................................................................... 16

Chapter 4: Designing with the Core................................................................... 36Clocking...................................................................................................................................... 36Resets..........................................................................................................................................40Interrupts................................................................................................................................... 41Program and Interrupt Flow....................................................................................................41Versal ACAP GTY HDMI GT Controller Implementation....................................................... 45

Chapter 5: Design Flow Steps.................................................................................49Customizing and Generating the Core...................................................................................49Constraining the Core...............................................................................................................53Synthesis and Implementation................................................................................................60

Chapter 6: Example Design..................................................................................... 61

Appendix A: Verification, Compliance, and Interoperability...............62

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Appendix B: Upgrading............................................................................................. 63

Appendix C: Debugging.............................................................................................64Finding Help on Xilinx.com...................................................................................................... 64Debug Tools............................................................................................................................... 65Interface Debug........................................................................................................................ 66

Appendix D: Application Software Development....................................... 70

Appendix E: Additional Resources and Legal Notices..............................71Xilinx Resources.........................................................................................................................71Documentation Navigator and Design Hubs.........................................................................71References..................................................................................................................................71Revision History......................................................................................................................... 72Please Read: Important Legal Notices................................................................................... 72




Chapter 1

IntroductionThe Xilinx® HDMI GT Controller LogiCORE™ IP core is designed for enabling plug-and-playconnectivity with Xilinx HDMI™ technology MAC Transmit or Receive subsystems. The interfacebetween the video MAC and PHY layers are standardized to enable ease of use in accessingshared transceiver resources. The AXI4-Lite register interface is provided to enable dynamicaccesses of transceiver controls/status.

Appropriate HDMI cable driver (TX) and EQ/retimer (RX) devices are required to meet HDMIelectrical compliance.

Features• AXI4-Lite support for register accesses

• Protocol Support for HDMI

• Full transceiver dynamic reconfiguration port (DRP) accesses to MMCME5

• Independent TX and RX path line rates

• Single quad support

• Protocol specific functions for HDMI

○ HDMI clock detector

○ Use of 4th GT channel as TX TMDS clock source

○ Non-integer data recovery unit (NI-DRU) support for lower line rates.

Chapter 1: Introduction




IP FactsLogiCORE™ IP Facts Table

Core Specifics

Supported Device Family Versal™ ACAP GTYE5 Transceivers

Supported User Interfaces AXI4-Stream, AXI4-Lite

Resources Performance and Resource Use web page

Provided with Core

Design Files Verilog

Example Design Provided with the HDMI IP subsystems

Test Bench Not Provided

Constraints File Xilinx Design Constraints (XDC)

Simulation Model Not Provided

Supported S/W Driver Standalone

Tested Design Flows3

Design Entry Vivado® Design Suite

Simulation For supported simulators, see the Xilinx Design Tools: Release Notes Guide.

Synthesis Vivado Synthesis

Support

Release Notes and Known Issues Master Answer Record: 72991

All Vivado IP Change Logs Master Vivado IP Change Logs: 72775

Xilinx Support web page

Notes:1. For a complete list of supported devices, see the Vivado® IP catalog.2. Standalone driver details can be found in <Install Directory>/Vitis/<Release>/data/embeddedsw/doc/

Xilinx_drivers.htm.3. For the supported versions of third-party tools, see the Xilinx Design Tools: Release Notes Guide.

Chapter 1: Introduction


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Chapter 2

Overview

Navigating Content by Design ProcessXilinx® documentation is organized around a set of standard design processes to help you findrelevant content for your current development task. All Versal™ ACAP design process DesignHubs can be found on the Xilinx.com website. This document covers the following designprocesses:

• Hardware, IP, and Platform Development: Creating the PL IP blocks for the hardwareplatform, creating PL kernels, subsystem functional simulation, and evaluating the Vivado®

timing, resource use, and power closure. Also involves developing the hardware platform forsystem integration. Topics in this document that apply to this design process include:

• Port Descriptions

• Register Space

• Clocking

• Resets

• Customizing and Generating the Core

• Chapter 6: Example Design

Core OverviewThe HDMI GT Controller core is a feature-rich soft IP core incorporating all the necessary logic toproperly interface with media access control (MAC) layers and control the physical-side interface(PHY) functionality. Xilinx® IP cores have been successfully tested on hardware and verified. Foradditional details on the interoperability results, contact your local Xilinx sales representative.

Chapter 2: Overview


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The core is intended to simplify the use of serial transceivers and adds domain-specificconfigurability. The HDMI GT Controller IP is not intended to be used as a stand-alone IP andmust be used with Xilinx Video MACs such as the HDMI™ 1.4/2.0 Transmitter/ReceiverSubsystems. The core enables simpler connectivity between MAC layers for TX and RX paths,and PHY layers. However, it is still important to understand the behavior, use, and any limitationsof the transceivers. See the device specific transceiver user guide for details.

The following figure shows the standard OSI Model and mapping it with video IP solutions.

Figure 1: OSI Mapping of Video Systems

Physical

Data Link

Network

Transport

Session

Presentation

Application

Physical(SERDES, IO)

Link Layer(HDMI)

HostApplication

(Drivers, Stack, Applications)

X22465-051419

In accordance with the OSI model, the major PHY component for video IP cores is SerDes.Standardizing the SerDes delivery model provides benefits and flexibility for a video MAC layerat the system level.

Chapter 2: Overview




The following figure shows the boundary between these MAC and PHY layers and key highlightsare:

• AXI4-Lite interface to provide software access.

• AXI4-Stream-based interface for easier connectivity between different video link layers.

• GT TX Interface: Standard GT TX channel interface for simpler connectivity (input and outputports) between Parent IP and GT Wizard. On top of IO connectivity, interface also carries theTX side configuration information of the GT Wizard such as the Line Rate Table. (The GT isalso referred to as a serial transceiver.)

• GT RX Interface: Standard GT RX channel interface for simpler connectivity (input and outputports) between Parent IP and GT Wizard. On top of IO connectivity, interface also carries theRX side configuration information of the GT Wizard such as the Line Rate Table.

Figure 2: Video IP Layer

LINK LAYERRTL

(Encrypted for Licensed IP Cores)

HDMI GT Controller

AXI4-Lite AXI4-Lite

AXI4-StreamVersal GT Wizard

Standard GTInterface

X23336-100919

ApplicationsThe HDMI GT Controller core is the supported method of configuring and using the PHY layerwith video MAC controllers.

Unsupported FeaturesThe following features of the standard are not supported in the core:

Chapter 2: Overview




• Multi-MAC controllers support (complex use cases).

• Any other protocol than HDMI. The current HDMI GT Controller core supports the sameprotocol MAC on both the input and output.

• Multiple protocols per instance (for example, two HDMIs in one HDMI GT Controller).

• Standalone use. (The HDMI GT Controller is designed to be used with the Xilinx HDMI MACsubsystems.)

Licensing and OrderingThis Xilinx® LogiCORE™ IP module is provided under the terms of the Xilinx Core LicenseAgreement. The module is shipped as part of the Vivado® Design Suite. For full access to all corefunctionalities in simulation and in hardware, you must purchase a license for the core. Togenerate a full license, visit the product licensing web page. Evaluation licenses and hardwaretimeout licenses might be available for this core. Contact your local Xilinx sales representative forinformation about pricing and availability.

Note: To verify that you need a license, check the License column of the IP Catalog. Included means that alicense is included with the Vivado® Design Suite; Purchase means that you have to purchase a license touse the core.

Information about other Xilinx® LogiCORE™ IP modules is available at the Xilinx IntellectualProperty page. For information about pricing and availability of other Xilinx LogiCORE IP modulesand tools, contact your local Xilinx sales representative.

License CheckersIf the IP requires a license key, the key must be verified. The Vivado® design tools have severallicense checkpoints for gating licensed IP through the flow. If the license check succeeds, the IPcan continue generation. Otherwise, generation halts with an error. License checkpoints areenforced by the following tools:

• Vivado Synthesis

• Vivado Implementation

• write_bitstream (Tcl command)

IMPORTANT! IP license level is ignored at checkpoints. The test confirms a valid license exists. It does notcheck IP license level.

Chapter 2: Overview


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Chapter 3

Product SpecificationThe HDMI GT Controller core is the supported method of configuring and using transceiverswith MAC subsystems. The core simplifies serial transceiver (GT) use by providing a standardizedinterface and software programmability of serial transceiver functions. The standardized GTinterface carries the GT Wizard configuration information based on the HDMI GT Controllerconfiguration which are passed to the GT Wizard when Block Automation is executed in the IPintegrator canvas.

The functional block diagram of the core is shown in the following figure.

Figure 3: Core Block Diagram

status sideband txstatus sideband rx

rx link data

ClockDetector

NI-DRUControl &

Status Mapper

AXI4-Lite CTRL/STAT (Registers + Interrupt)

SidebandMapper

AXI4

-LIT

E

Inte

rrup

t

GT REFCLKs(TX, RX, DRU)

HDMI 1.4/2.0Video & TMDS clocks

GT WIZ RESET CTLR

Clock Generator

GT RX[3:0] Intf

GT TX[3:0] Intf

RX USERDATA

MAPPER

TX USERDATA

MAPPER tx link data

X23337-100819

• AXI4-Lite Control/Status Manager: This block manages AXI4-Lite bus protocol accesses andhandles memory map accesses and interrupt management.

• Clock Detector: This block contains frequency counters to determine the corresponding GToperation based on the incoming GT reference clock frequency.

Chapter 3: Product Specification




• GT Reset Controller: This block contains GT Reset IPs specially made to assist in the Versal GTinitialization.

• NI-DRU: This block is used in applications where lower line rates (those below the ratessupported by the respective GTs) are needed. In HDMI™, the NI-DRU is enabled when the RXTMDS clock is below the threshold of the specific GT type.

• GTYE5 Thresholds○ LCPLL = 125.000 MHz○ RPLL = 125.0 MHz

The NI-DRU requires an additional fixed reference clock to the GT RX (as well as the RXTMDS clock) to run the low line rate data recovery. For more information on the referenceclock frequency requirement per transceiver type, see Reference Clock Requirements (linkbelow).

• Control and Status Mapper: This block maps the AXI4-Lite control and status registers to thecorresponding GT ports within the GT TX/RX interfaces.

• TX and RX User Data Mapper: This block maps the GT input or output data according to theAXI4-Stream protocol defined in the GT specification.

Additionally, the TX User Data Mapper multiplexes between normal AXI4-Stream data fromHDMI TX MAC and the TX TMDS Pattern Generator when the Use 4th GT Channel as TXTMDS clock option is enabled. This connects to the 4th GT channel and provides the patternto transmit the TMDS clock through the GT channel.

• Clock Generator: This block also produces video clocks and differential and single-ended TXand RX Transition Minimized Differential Signaling (TMDS) CLK as per requirement of the

• HDMI 1.4/2.0 Transmitter Subsystem Product Guide (PG235)

• HDMI 1.4/2.0 Receiver Subsystem Product Guide (PG236)

Note: The video clock maximum frequency is 297 MHz.

Related Information

Reference Clock Requirements

PerformanceThe HDMI GT Controller is designed to operate in coordination with the performancecharacteristics of the transceiver primitives it instantiates.



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The following documents provide information about DC and AC switching characteristics. Thefrequency ranges specified by these documents must be adhered to for proper transceiver andcore operation.

• Versal Prime Series Data Sheet: DC and AC Switching Characteristics (DS956)

• Versal AI Core Series Data Sheet: DC and AC Switching Characteristics (DS957)

• Versal AI Edge Series Data Sheet: DC and AC Switching Characteristics (DS958)

Resource UseFor full details about performance and resource use, visit the Performance and Resource Use webpage.

Port DescriptionsClock, Reset, and Initialization PortsTable 1: Clocking, Reset, and Initialization Ports

Port Name I/O Clock Domain Descriptiongt_refclk0_odiv2 I Available when GT REFCLK0 is selected as one of the

input clock sources in the GUI.Connects to BUFG_GT driven by ODIV2 output port ofIBUFDS_GTE

gt_refclk1_odiv2 I Available when GT REFCLK1 is selected as one of theinput clock sources in the GUI.Connects to BUFG_GT driven by ODIV2 output port ofIBUFDS_GTE






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Table 1: Clocking, Reset, and Initialization Ports (cont'd)

Port Name I/O Clock Domain Descriptiongt_refclk5_odiv2 I Available when GT REFCLK5 is selected as one of the

input clock sources in the GUI.Connects to BUFG_GT driven by ODIV2 output port ofIBUFDS_GTE

gt_powergood I Async Connects to GTPOWERGOOD port of the GT Wizard

gt_ch0/1/2/3_ilo_resetdone I Async Connects to CH0/1/2/3_ILORESETDONE ports of the GTWizard

gt_lcpll0/1_lock I Async Connects to HSCLK0/1_LCPLLLOCK of the GT Wizard

gt_rpll0/1_lock I Async Connects to HSCLK0/1_RPLLLOCK of the GT Wizard

gt_lcpll0/1_reset O Async Connects to HSCLK0/1_LCPLLRESET of the GT Wizard

gt_rpll0/1_reset O Async Connects to HSCLK0/1_RPLLRESET of the GT Wizard

apb_clk I Connect to the free-running clock driving the apb3clkport of the GT Wizard

tx_axi4s_aclk I Transmit Interface Clock

tx_axi4s_aresetn I TXUSRCLK2 Transmit Interface ResetUnused port. It can be tied High or left unconnected.

rx_axi4s_aclk I Receive Interface Clock

rx_axi4s_aresetn I RXUSRCLK2 Receive Interface ResetUnused port. It can be tied High or left unconnected.

sb_aclk I Sideband Interface ClockConnect to AXI4-Lite clock.

sb_aresetn I sb_aclk(AXI4-Lite)

Sideband Interface ResetUnused port. It can be tied High, left unconnected orconnected to the ARESETN port of the PROC_SYS_RESETIP under sb_aclk clock domain.

gt_txusrclk I Connect to the USRCLK output port of the BUFG_GTdriving the chN_txusrclk ports of the GT Wizard

gt_rxusrclk I Connect to the USRCLK output port of the BUFG_GTdriving the chN_rxusrclk ports of the GT Wizard

axi4lite_aclk I AXI Bus clock

axi4lite_aresetn I AXI4-Lite AXI Reset. Active-Low.Must be connected to ARESETN that is synched toaxi4lite_aclk port (that is,.peripheral_aresetn port of theProcessor System Reset Module IP)

tx_refclk_rdy I Async Active-High (default):1 - Locked0 - Unlocked

TX Reference clock ready or lock indicator. SeeReference Clocks Requirements for details abouttx_refclk_rdy port implementation.Active level is controlled by Tx RefClk Rdy Active GUIparameter. If set to Low,

1 - Unlocked0 - Locked

tx_tmds_clk O Single-ended TX TMDS Clock





Table 1: Clocking, Reset, and Initialization Ports (cont'd)

Port Name I/O Clock Domain Descriptiontx_tmds_clk_p/n O Differential TX TMDS Clock output

Note: These ports are disabled when GUI option Use4Th GT Channel as TX TMDS Clock is checked.

tx_video_clk O TX Video Clock

rx_tmds_clk O Single-ended RX TMDS Clock

rx_tmds_clk_p/n O Differential RX TMDS Clock output

rx_video_clk O RX Video Clock

Related Information


GT Interface PortsTable 2: GT Interface Ports

Port Name I/O Clock Domain Descriptiongt_tx0/1/2/3 I/O GT_TXUSRCLK Connects to the TX0/1/2/3_GT_IP_Interface port of the

GT Wizard

gt_rx0/1/2/3 I/O GT_RXUSRCLK Connects to the RX0/1/2/3_GT_IP_Interface port of theGT Wizard

gt_debug I/O Async Connects to the GT_DEBUG interface port of the GTWizard

ch0/1/2/3_debug I/O Aysnc Connects to the CH0/1/2/3_DEBUG interface port of theGT Wizard

HDMI Interface PortsTable 3: HDMI Interface Ports

Port Name I/O Clock Domain Descriptiontx_axi4s_ch_ tready O GT_TXUSRCLK AXI4-Stream tready indicator

: Transceiver channel index

tx_axi4s_ch_ tvalid I GT_TXUSRCLK AXI4-Stream tvalid indicator.: Transceiver channel index

tx_axi4s_ch_ tdata1 I GT_TXUSRCLK AXI4-Stream tdata bus: Transceiver channel index GT Mapping: TXDATA_IN

tx_axi4s_ch_ tuser I GT_TXUSRCLK AXI4-Stream tuser bus: Transceiver channel indexUnused

rx_axi4s_ch_ tready I GT_RXUSRCLK AXI4-Stream tready indicator: Transceiver channel index





Table 3: HDMI Interface Ports (cont'd)

Port Name I/O Clock Domain Descriptionrx_axi4s_ch_ tvalid O GT_RXUSRCLK AXI4-Stream tvalid indicator.

: Transceiver channel index

rx_axi4s_ch_ tdata2 O GT_RXUSRCLK AXI4-Stream tdata bus: Transceiver channel index GT Mapping:RXDATAOUT

rx_axi4s_ch_ tuser O GT_RXUSRCLK AXI4-Stream tuser bus: Transceiver channel indexUnused

Notes:1. Width = TX_DATA_WIDTH2. Width = RX_DATA_WIDTH

Sideband Signal Ports (Optional)Table 4: Sideband Signal Ports (Optional)

Port Name I/O Clock Domain Descriptionstatus_sb_tx_tready I sb_aclk AXI4-Stream based tready indicator

status_sb_tx_tdata[1:0] O sb_aclk AXI4-Stream based tdata bus

status_sb_tx_tvalid O sb_aclk AXI4-Stream based tvalid

status_sb_rx_tready I sb_aclk AXI4-Stream based tready indicator

status_sb_rx_tdata[1:0] O sb_aclk AXI4-Stream based tdata bus

status_sb_rx_tvalid O sb_aclk AXI4-Stream based tvalid

HDMI Transmit - Status Path

The following status is transferred to the Link layer. The status bits are driven using the AXI4-Liteclock.

Table 5: HDMI Transmit Status Sideband Definition

Bit Position Status Details0 TX Link Ready. This signal is asserted to indicate that the GT TX initialization is completed

(txresetdone).

1 TX Video Ready. This signal is asserted to indicate that the video clock from TX MMCM block isstable.

HDMI Receive - Status Path

The following status is transferred to the Link layer. The status bits are driven using the AXI4-Liteclock.





Table 6: HDMI Receive Status Sideband Definition

Bit Position Status Details0 RX Link Ready. This signal is asserted to indicate that the GT RX initialization is completed

(rxresetdone).

1 RX Video Ready. This signal is asserted to indicate that the video clock from the RX MMCM block isstable.

AXI4-Lite PortsTable 7: AXI4-Lite Ports

Port Name1 I/O Descriptionaxi4lite_awaddr[9:0] I Write address

axi4lite_awprot[2:0] I Protection type

axi4lite_awvalid I Write address valid

axi4lite_awready O Write address ready

axi4lite_awdata[31:0] I Write data bus

axi4lite_awstrb[3:0] I Write strobes

axi4lite_wvalid I Write valid

axi4lite_wready O Write ready

axi4lite_bresp[1:0] O Write response

axi4lite_bvalid O Write response valid

axi4lite_bready I Response ready

axi4lite_araddr[9:0] I Read address

axi4lite_arprot[2:0] I Protection type

axi4lite_arvalid I Read address valid

axi4lite_arready O Read address ready

axi4lite_rdata[31:0] O Read data

axi4lite_rresp[1:0] O Read response

axi4lite_rvalid O Read valid

axi4lite_rready I Read ready

irq O Interrupt output

Notes:1. Clock domain = AXI4-Lite.

Register SpaceThe HDMI GT Controller configuration data is implemented as a set of distributed registers thatcan be read or written from the AXI4-Lite interface. These registers are synchronous to the AXI4-Lite domain.





Any bits not specified in the following register tables are considered reserved and return 0 uponread. The power-on reset values of control registers are 0 unless specified in the definition. Onlyaddress offsets are listed in the following tables and the base address is configured by the AXIinterconnect at the system level.

For more information, see the Versal ACAP GTY and GTYP Transceivers Architecture Manual(AM002).

Table 8: Register Address Space

Address (hex) Register0x0000 Version Register (VR)

Shared Features and Resets

0x0014 Reset (PR)

0x0018 PLL Lock Status (PLS)

0x001C TX Initialization (TXI)

0x0020 TX Initialization Status (TXIS)

0x0024 RX Initialization (RXI)

0x0028 RX Initialization Status (RXIS)

0x0068 GT_DBG_CONTROL (GTDBGC)

0x006C GT_DBG_STATUS (GTDBGS)

Transmitter Functions

0x0078 TX Status (TXS)

0x007C TX Channel Control – Channel 1 and 2

0x0080 TX Channel Control – Channel 3 and 4

0x0084 TX Channel Control Channel 1 to 4

0x008C TX DRIVER Control Extension Channel 1 and 2

0x0090 TX DRIVER Control Extension Channel 3 and 4

Receiver Functions

0x0098 RX DRIVER Control Extension Channel 1 and 2

0x009C RX DRIVER Control Extension Channel 3 and 4

0x0104 RX Status (RXS)

0x0108 RX Equalization and CDR

Interrupts Registers

0x0110 Interrupt Enable Register (IER)

0x0114 Interrupt Disable Register (IDR)

0x0118 Interrupt Mask Register (IMR)

0x011C Interrupt Status Register (ISR)

TXUSRCLK Clocking

0x0120 MMCM TXUSRCLK Control/Status (MMCM_TXUSRCLK_CTRL)

0x0124 DRP CONTROL MMCM TXUSRCLK

0x0128 DRP STATUS MMCM TXUSRCLK

0x0140 MMCM RXUSRCLK Control/Status (MMCM_RXUSRCLK_CTRL)



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Table 8: Register Address Space (cont'd)

Address (hex) Register0x0144 DRP CONTROL MMCM RXUSRCLK

0x0148 DRP STATUS MMCM RXUSRCLK

Clock Detector

0x0200 Clock Detector Control Register

0x204 Clock Detector Status Register

0x0208 Clock Detector Frequency Counter Timeout

0x020C Clock Detector Transmitter Frequency

0x0210 Clock Detector Receiver Frequency

0x0214 Clock Detector Transmitter Timer

0x0218 Clock Detector Receiver Timer

0x021C Clock Detector DRU Frequency

Data Recovery Unit

0x0300 Data Recovery Unit Control Register

0x0304 Data Recovery Unit Status Register

0x0308 Data Recovery Unit Center Frequency Low Register – All Channels

0x030C Data Recovery Unit Center Frequency High Register – All Channels

0x0310 Data Recovery Unit Gain Register – All Channels

TX TMDS Pattern Generator

0x0340 Control Register

Version Register (0x0000)Table 9: Version Register (VR)

Bit DefaultValue

AccessType Description

31:24 1 RO Core major version.

23:16 0 RO Core minor version

15:12 0 RO Core version revision

11:8 0 RO Core patch details

7:0 0 RO Internal revision

Reset Register (PR) (0x0014)Table 10: Reset Register

Bit DefaultValue


0 1 RW TX GT Reset IP Reset





Table 10: Reset Register (cont'd)

Bit DefaultValue


1 1 RW RX GT Reset IP Reset

PLL Lock Status (PLS) Register (0x0018)Table 11: PLL Lock Status Register

Bit DefaultValue


6 0 RO RLL0LOCK

7 0 RO RLL1LOCK

8 0 RO LCLL0LOCK

9 0 RO LCLL1LOCK

TX Initialization (TXI) Register (0x001C)Table 12: TX Initialization Register

Bit DefaultValue


Channel 1

0 0 RW GTTXRESET

4 1 RW TX_LNKRDY_SB_MASK

5 0 RW GTTXMSTRESET

7 0 RW PLL_GT_RESET

Channel 2

8 0 RW GTTXRESET


13 0 RW GTTXMSTRESET

15 0 RW PLL_GT_RESET

Channel 3

16 0 RW GTTXRESET




Channel 4

24 0 RW GTTXRESET







Table 12: TX Initialization Register (cont'd)

Bit DefaultValue



TX Initialization Status (TXIS) Register (0x0020)Table 13: TX Initialization Status (TXIS)

Bit DefaultValue


Channel 1

0 0 RO TXRESETDONE

1 0 RO TXPMARESETDONE

2 0 RO GTPOWERGOOD

3 0 RO GTTXMSTRESETDONE

7:4 0 RO Reserved

Channel 2

8 0 RO TXRESETDONE


10 0 RO GTPOWERGOOD


15:12 0 RO Reserved

Channel 3

16 0 RO TXRESETDONE


18 0 RO GTPOWERGOOD


23:20 0 RO Reserved

Channel 4

24 0 RO TXRESETDONE


26 0 RO GTPOWERGOOD


31:28 0 RO Reserved





RX Initialization (RXI) Register (0x0024)Table 14: RX Initialization (RXI) Register

Bit DefaultValue


Channel 1

0 0 RW GTRXRESET

4 0 RW RX_LNKRDY_SB_MASK

5 0 RW GTRXMSTRESET

7 0 RW PLL_GT_RESET

Channel 2

8 0 RW GTRXRESET


13 0 RW GTRXMSTRESET


Channel 3

16 0 RW GTRXRESET




Channel 4

24 0 RW GTRXRESET




RX Initialization Status (RXIS) Register (0x0028)Table 15: RX Initialization Status (RXIS) Register

Bit DefaultValue


Channel 1

0 0 RO RXRESETDONE

1 0 RO RXPMARESETDONE

2 0 RO GTPOWERGOOD

3 0 RO GTRXMSTRESETDONE

7:4 0 RO Reserved

Channel 2

8 0 RO RXRESETDONE






Table 15: RX Initialization Status (RXIS) Register (cont'd)

Bit DefaultValue


10 0 RO GTPOWERGOOD


15:10 0 RO Reserved

Channel 3

16 0 RO RXRESETDONE


18 0 RO GTPOWERGOOD


23:20 0 RO Reserved

Channel 4

24 0 RO RXRESETDONE


26 0 RO GTPOWERGOOD


31:28 0 RO Reserved

GT_DBG_CONTROL (GTDBGC) (0x0068)Table 16: GT_DBG_CONTROL Register

Bit DefaultValue


15:0 0 RW GPI

GT_DBG_STATUS (GTDBGS) (0x006C)Table 17: GT_DBG_STATUS Register

Bit DefaultValue


15:0 0 RO GPO





TX Status (TXS) Register (0x0078)Table 18: TX Status (TXS) Register

Bit DefaultValue


Channel 1

4:3 0 RW TXBUFSTATUS[1:0]

Channel 2


Channel 3


Channel 4


TX Channel Control – Channel 1 and 2 Register(0x007C)Table 19: TX DRIVER Control – Channel 1 and 2 Register

Bit DefaultValue


Channel 1

3:0 0 RW TXDIFFCTRL[3:0]

4 0 RW TXELECIDLE

5 0 RW TXINHIBIT

10:6 0 RW TXPOSTCURSOR[4:0]

15:11 0 RW TXPRECURSOR[4:0]

Channel 2

19:16 0 RW TXDIFFCTRL [3:0]

20 0 RW TXELECIDLE

21 0 RW TXINHIBIT







TX Channel Control – Channel 3 and 4 Register(0x0080)Table 20: TX DRIVER Control – Channel 3 and 4 Register

Bit DefaultValue


Channel 3

3:0 0 RW TXDIFFCTRL[3:0]

4 0 RW TXELECIDLE

5 0 RW TXINHIBIT



Channel 4

19:16 0 RW TXDIFFCTRL [3:0]

20 0 RW TXELECIDLE

21 0 RW TXINHIBIT



TX Channel Control Channel 1 to 4 Register (0x0084)Table 21: TX Channel Control Channel 1 to 4 Register

Bit DefaultValue


0 0 RW MSB bit of Channel 1 TXDIFFCTRL




TX DRIVER Control Extension Channel 1 and 2Register (0x008C)Table 22: TX DRIVER Control Extension Channel 1 and 2 Register

Bit DefaultValue


Channel 1

7:0 0 RW TXRATE

Channel 2

23:16 0 RW TXRATE





TX DRIVER Control Extension Channel 3 and 4Register (0x0090)Table 23: Reset Register

Bit DefaultValue


Channel 3

7:0 0 RW TXRATE

Channel 4

23:16 0 RW TXRATE

RX DRIVER Control Extension Channel 1 and 2Register (0x0098)Table 24: RX DRIVER Control Extension Channel 1 and 2 Register

Bit DefaultValue


Channel 1

7:0 0 RW RXRATE

Channel 2

23:16 0 RW RXRATE

RX DRIVER Control Extension Channel 3 and 4Register (0x009C)Table 25: RX DRIVER Control Extension Channel 3 and 4 Register

Bit DefaultValue


Channel 3

7:0 0 RW RXRATE

Channel 4

23:16 0 RW RXRATE





RX Status (RXS) Register (0x0104)Table 26: RX Status Register

Bit DefaultValue


Channel 1

0 0 RO RXCDRLOCK

3:1 0 RO RXBUFSTATUS [2:0]

4 0 RO RXPRBSERR

7:5 0 RO Reserved

Channel 2

8 0 RO RXCDRLOCK


12 0 RO RXPRBSERR

15:13 0 RO Reserved

Channel 3

16 0 RO RXCDRLOCK


20 0 RO RXPRBSERR

23:21 0 RO Reserved

Channel 4

24 0 RO RXCDRLOCK


28 0 RO RXPRBSERR

31:29 0 RO Reserved

RX Equalization and CDR Register (0x0108)Table 27: RX Equalization and CDR Register

Bit DefaultValue


Channel 1

1 0 RW RXCDRHOLD

5:2 0 RW Reserved

Channel 2

9 0 RW RXCDRHOLD

15:10 0 RW Reserved

Channel 3

17 0 RW RXCDRHOLD

23:18 0 RW Reserved





Table 27: RX Equalization and CDR Register (cont'd)

Bit DefaultValue


Channel 4

25 0 RW RXCDRHOLD

31:26 0 RW Reserved

Interrupt Enable Register (IER) (0x0110)Table 28: Interrupt Enable Register

Bit DefaultValue


0 0 WO TX Reset Done Change Event

1 0 WO RX Reset Done Change Event

3 0 WO LCLL Lock Change Event

5 0 WO RPLL Lock Change Event

6 0 WO Clock Detector TX Frequency Change

7 0 WO Clock Detector RX Frequency Change

9 0 WO TX MMCM Lock Change Event

10 0 WO RX MMCM Lock Change Event

11 0 WO TX GPO Change Event

12 0 WO RX GPO Change Event

30 0 WO Clock Detector TX Debounce Timeout

31 0 WO Clock Detector RX Debounce Timeout

Interrupt Disable Register (IDR) (0x0114)Table 29: Interrupt Disable Register

Bit DefaultValue


0 0 WO TX Reset Done Change Event

1 0 WO RX Reset Done Change Event

3 0 WO LCPLL Lock Change Event

5 0 WO RPLL Lock Change Event

6 0 WO Clock Detector TX Frequency Change

7 0 WO Clock Detector RX Frequency Change

9 0 WO TX MMCM Lock Change Event

10 0 WO RX MMCM Lock Change Event

11 0 WO TX GPO Change Event





Table 29: Interrupt Disable Register (cont'd)

Bit DefaultValue


12 0 WO RX GPO Change Event

30 0 WO Clock Detector TX Debounce Timeout

31 0 WO Clock Detector RX Debounce Timeout

Interrupt Mask Register (IMR) (0x0118)Table 30: Interrupt Mask Register

Bit DefaultValue


0 0 RO TX Reset Done Change Event

1 0 RO RX Reset Done Change Event

3 0 RO LCPLL Lock Change Event

5 0 RO RPLL Lock Change Event

6 0 RO Clock Detector TX Frequency Change

7 0 RO Clock Detector RX Frequency Change

9 0 RO TX MMCM Lock Change Event

10 0 RO RX MMCM Lock Change Event

11 0 RO TX GPO Change Event

12 0 RO RX GPO Change Event

30 0 RO Clock Detector TX Debounce Timeout

31 0 RO Clock Detector RX Debounce Timeout

Interrupt Status Register (ISR) (0x011C)Valid interrupt event by AND of IMR and ISR.

Table 31: Interrupt Status Register

Bit DefaultValue


0 0 W1C TX Reset Done Change Event:Triggers an interrupt whenever the state of reset done changes. SW has to readthe TXIS register to know reset done state.

1 0 W1C RX Reset Done Change EventTriggers an interrupt whenever the state of reset done changes. The software hasto read the RXIS register to find out the reset done state.

3 0 W1C LCPLL Lock Change EventTriggers an interrupt whenever the state of LCPLL Lock changes. The software hasto read the PLS register to find out the lock state.





Table 31: Interrupt Status Register (cont'd)

Bit DefaultValue


5 0 W1C RPLL Lock Change EventTriggers an interrupt whenever the state of RPLL Lock changes. The software hasto read the PLS register to find out the lock state.

6 0 W1C Clock Detector TX Frequency Change

7 0 W1C Clock Detector RX Frequency Change

9 0 W1C TX MMCM Lock Change Event

10 0 W1C RX MMCM Lock Change Event

11 0 W1C TX GPO Change Event

12 0 W1C RX GPO Change Event

30 0 W1C Clock Detector TX Debounce Timeout

31 0 W1C Clock Detector RX Debounce Timeout

MMCM TXUSRCLK Control/Status(MMCM_TXUSRCLK_CTRL) Register (0x0120)Table 32: MMCM TXUSRCLK Control/Status Register

Bit DefaultValue1


0 0 RW Reserved

1 0 RW MMCM Reset

8 0 RW Reserved

9 0 RO MMCM Locked Status

10 0 RW MMCM Power Down

11 0 RW MMCM Lock Mask

12 1 RW MMCM CLKINSEL1 - TMDS Reference Clock0 - DRU Reference Clock

Notes:1. Default value for register is 32'h0000_1000.

DRP CONTROL MMCM TXUSRCLK Register (0x0124)Table 33: DRP CONTROL MMCM TXUSRCLK Register

Bit DefaultValue


11:0 0 RW DRPADDR[8:0]

12 0 RW DRPEN





Table 33: DRP CONTROL MMCM TXUSRCLK Register (cont'd)

Bit DefaultValue


13 0 RW DRPWE

31:16 0 RW DRPDI [15:0]

DRP STATUS MMCM TXUSRCLK Register (0x0128)Table 34: DRP STATUS MMCM TXUSRCLK Register

Bit DefaultValue


15:0 0 RO DRPDO[15:0] – Valid for Read Transfers

16 0 RO DRPRDY (Indicates valid transfer)

17 0 RO DRPBUSY (Indicated DRP port free)

31:18 0 RO Reserved

MMCM RXUSRCLK Control/Status(MMCM_RXUSRCLK_CTRL) Register (0x0140)Table 35: MMCM RXUSRCLK Control/Status Register

Bit DefaultValue1


0 0 RW Reserved

1 0 RW MMCM Reset

8 0 RW Reserved

9 0 RO MMCM Locked Status

10 0 RW MMCM Power Down

11 0 RW MMCM Locked Mask

12 1 RW MMCM CLKINSEL1 - TMDS Reference Clock0 - DRU Reference Clock

Notes:1. Default value for register is 32'h0000_1000.





DRP CONTROL MMCM RXUSRCLK Register (0x0144)Table 36: DRP CONTROL MMCM RXUSRCLK Register

Bit DefaultValue


11:0 0 RW DRPADDR[8:0]

12 0 RW DRPEN

13 0 RW DRPWE

31:16 0 RW DRPDI [15:0]

DRP STATUS MMCM RXUSRCLK Register (0x0148)Table 37: DRP STATUS MMCM RXUSRCLK Register

Bit DefaultValue


15:0 0 RO DRPDO[15:0] – Valid for Read Transfers

16 0 RO DRPRDY (Indicates valid transfer)

17 0 RO DRPBUSY (Indicated DRP port free)

31:18 0 RO Reserved

Clock Detector Control Register (0x0200)Table 38: Clock Detector Control Register

Bit DefaultValue


0 0 RW Run: Set this bit to enable clock detector.

1 0 RW TX Timer Clear – Self Clearing

2 0 RW RX Timer Clear – Self Clearing

3 0 RW TX Frequency Reset – Self Clearing when TX Frequency Zero bit asserts

4 0 RW RX Frequency Reset – Self Clearing when RX Frequency Zero bit asserts

12:5 0 RW Frequency Lock Counter Threshold

Clock Detector Status Register (0x0204)Table 39: Clock Detector Status Register

Bit DefaultValue


0 0 RO TX Frequency Zero

1 0 RO RX Frequency Zero





Table 39: Clock Detector Status Register (cont'd)

Bit DefaultValue


2 0 RO TX Reference Clock Locked

3 0 RO TX Reference Clock Locked Captured

Clock Detector Frequency Counter Timeout Register(0x0208)Table 40: Clock Detector Frequency Counter Timeout Register

Bit DefaultValue


31:0 0 RW Clock Frequency in Hertz (Typically system frequency value)

Clock Detector Transmitter Frequency Register(0x020C)Table 41: Clock Detector Transmitter Frequency Register

Bit DefaultValue


31:0 0 RO Transmitter Clock Frequency in Hertz

Clock Detector Receiver Frequency Register (0x0210)Table 42: Clock Detector Receiver Frequency Register

Bit DefaultValue


31:0 0 RO Receiver Clock Frequency in Hertz

Clock Detector Transmitter Timer Register (0x0214)Table 43: Clock Detector Transmitter Timer Register

Bit DefaultValue


31:0 0 RW Transmitter Timeout Value at System Clock per tick





Clock Detector Receiver Timer Register (0x0218)Table 44: Clock Detector Receiver Timer Register

Bit DefaultValue


31:0 0 RW Receiver Timeout Value at System Clock per tick

Clock Detector DRU Frequency Register (0x021C)Table 45: Clock Detector DRU Frequency Register

Bit DefaultValue


31:0 0 RO Data Recovery Unit Clock Frequency in Hertz

Data Recovery Unit Control Register (0x0300)Table 46: Data Recovery Unit Control Register - All Channels

Bit DefaultValue


0 0 RW Reset1 – Reset asserted0 – Reset released

1 0 RW Enable0 – DRU disabled1 – DRU enabled

31:2 0 RW Reserved

Data Recovery Unit Status Register (0x0304)Table 47: Data Recovery Unit Status Register

Bit DefaultValue


0 0 RO Channel 1 DRU Active




23:4 0 RO Reserved

31:24 0 RO DRU Version





Data Recovery Unit Center Frequency Low Register –All Channels Register (0x0308)Table 48: Center Frequency Low Register – All Channels Register

Bit DefaultValue


31:0 0 RW Center frequency bits 31:0

Data Recovery Unit Center Frequency High Register –All Channels Register (0x030C)Table 49: Center Frequency High Register – All Channels Register

Bit DefaultValue


4:0 0 RW Center frequency bits 36:32

31:5 0 RW Reserved

Data Recovery Unit Gain Register – All Channels(0x0310)Table 50: Gain Register – All Channels

Bit DefaultValue


4:0 0 RO Gain G1

7:5 0 RO Reserved

12:8 0 RO Gain G1 P

15:13 0 RO Reserved

20:16 0 RO Gain G2

31:21 0 RO Reserved





TX TMDS Pattern Generator Control Register(0x0340)Table 51: TX TMDS Pattern Generator Control Register

Bit DefaultValue


2:0 0 RW Clock Ratio0x0 - OFF0x1 - Ratio - 100x2 - Ratio - 200x3 - Ratio - 300x4 - Ratio - 400x5 - Ratio - 500x6 - OFF0x7 - OFF

31 0 RW Enable:1: Enable0: Disable





Chapter 4

Designing with the CoreThis section includes guidelines and additional information to facilitate designing with the core.

ClockingThe HDMI GT Controller clocking diagrams per transceiver type are shown as follows. Use thefollowing guidelines when connecting the HDMI GT Controller clock ports or refer to theexample design.

• Connect the external clock generator output clock to the TX reference clock input that wasselected in the HDMI GT Controller Vivado® IDE. The TX reference clock lock indicatorshould be connected to the tx_refclk_rdy port. See HDMI Reference Clock Requirements(link below) for its implementation.

• Connect the RX TMDS clock from the external HDMI retimer component clock output to thecorresponding RX reference clock input that was selected in the HDMI GT Controller IDE.

• Connect the DRU mode reference clock to the reference clock input that was selected in theHDMI GT Controller IDE. See HDMI Reference Clock Requirement for the NI-DRU modefrequency requirements.

• The gt_txusrclk/gt_rxusrclk signal is connected to the HDMI MAC controller and thechN_txusrclk/chN_rxusrclk ports of the GT Wizard.

• The tx_video_clk/rx_video_clk signals are connected to the HDMI MAC controller.

• The tx_tmds_clk_p/n signal should be connected to the HDMI TX connector.

• The tx_tmds_clk signal can be connected to any logic, for example, audio generatormodule.

• The rx_tmds_clk_p/n signal should be connected to the input of the external clockgenerator if the HDMI GT Controller is used in pass through mode. This is to have a phasealigned and jitter attenuated reference clock for the HDMI TX Subsystem.

• The rx_tmds_clk signal can be connected to any logic.

• The gt_refclk[0-5]_odiv2 signal is connected to the respective bufg_gt output. This isthe refclk that can be used in PL.

Chapter 4: Designing with the Core




• The rx_axi4s_aclk and tx_axi4s_aclk signals should be connected to the streamingclock similar to the gt_rxusrclk/gt_txusrclk signal.

• The sb_clk, axi4lite_aclk and apb_clk signals can all be same.

• The gt_lcpll0/1_lock and gt_rpll0/1_lock signals should be connected to therespective lock output signal of the GT quad.

Note: The HDMI RX and TX Subsystem clocks must be phase aligned in pass through mode to ensureseamless video streaming. Otherwise, the video output intermittently breaks due to mismatching clocks.This connection is not needed if the HDMI GT Controller is used in a TX-only application because theexternal clock generator should run in standalone mode, using its local oscillator as its reference.

The following clocking diagrams show the default clock buffers. These buffers can be changed byusers according to their own application, through the user configurable parameters. Theseparameters are in white dash-lined boxes with prefix CONFIG.<user_param_name>.

IMPORTANT! The HDMI GT Controller has been tested using the default settings. You are expected tounderstand the proper clock buffer usage and design implications when changing the user parameters. Seethe Versal ACAP Clocking Resources Architecture Manual (AM003).

The user parameters can be configured using Tcl commands or through the Block Propertieswindow in IP integrator. For example:

set_property -dict [list CONFIG.C_Use_Oddr_for_Tmds_Clkout {false}] [get_ips <ip name>]set_property -dict [list CONFIG.C_Tx_Outclk_Buffer {none}] [get_ips <ip name>]set_property -dict [list CONFIG.C_Rx_Video_Clk_Buffer {bufg}] [get_ips <ip name>]



https://www.xilinx.com/cgi-bin/docs/ndoc?t=architecture-manuals;d=am003-versal-clocking-resources.pdf



Figure 4: HDMI GT Controller Clocking Diagram

TX MMCME5

CLKIN1

CLKOUT1

External ClockGenerator

HDMI GT Controller Clocking

tx_video_clkIBUFDSG

TE5IBUFDSG

TE5IBUFDSG

TE5

tx_refclk_p

tx_refclk_n

rx_refclk_p

rx_refclk_n

dru_refclk_p

dru_refclk_n

ODIV2

ODIV2

ODIV2

CLKOUT2

CONFIG.C_Tx_Video_Clk_Buffer

RX MMCME5

CLKIN1

CLKOUT1

OBUFTDS

rx_tmds_clk_p

rx_tmds_clk_n

rx_tmds_clk

rx_video_clkCLKOUT2

CONFIG.C_Rx_Video_Clk_Buffer

CONFIG.C_Rx_Tmds_Clk_Buffer

CONFIG.C_Use_Oddr_for_Tmds_Clkout

HDMIRX

Retimer

*Needed for Passthrough application only

gt_rxusrclk

CONFIG.C_Use_GT_CH4_HDMI

tx refclkdru refclkrx refclk

CLOCK DETECTORgt_refclkX_odiv2

gt_refclkY_odiv2

gt_refclkZ_odiv2

DP159

HDMI TX

tx_tmds_clk_p

tx_tmds_clk_n

tx_tmds_clk

CONFIG.C_Use_Oddr_for_Tmds_Clkout

CTRL & STAT MAPPER

gt_txusrclk

to GT Wizard

to GT Wizard

to GT Wizard

CONFIG.C_Use_GT_CH4_HDMI

from GT Wizard

from GT Wizard

BUFG_GT

BUFG_GT

BUFG

BUFG

BUFG

BUFG

OBUFTDS

TX TMDSPattern

Generator

BUFG_GT

X23329-102119

Related Information


Connecting GT Reference Clocks to HDMI GTController and GT WizardThe HDMI GT Controller opens the gt_refclk[0-5]_odiv2 ports when selected as thereference clock source from the Vivado IDE. See the following figure on how to connect the GTreference clock from a differential input to the HDMI GT Controller and GT Wizard.

Two Utility Buffers and a Constant instance are needed to fully connect the GT reference clocks,configured as IBUFDSGTE, BUFG GT and constant value of 1 respectively. Follow the clockbuffer connections as shown in the following figure.





Figure 5: Connecting the GT Reference Clock

Note: BUFG_GT_CE port of the BUFG_GT buffer must be driven High.

Note: IBUF_DS_ODIV2 port of the IBUFDSGTE is by default configured to output divide by 1.

Note: It is not necessary that the transceiver GT_REFCLK always corresponds to the same refclk as theHDMI GT Controller (hdmi_gt_controller) core. For example, the RX refclk can be connected to the HDMIGT Controller core's gt_refclk0_odiv2 port while the same refclk can be connected to thetransceiver's REFCLK1. Refer to the clock connection guidance from the Versal™ GT Quad.

Using 4th GT Channel as TX TMDS Clock SourceHDMI 1.4 and 2.0 protocols use three GT channels in a Quad, leaving one unused. The 4th GTchannel can be enabled and used as the TX TMDS clock source instead of being generated byDCM (MMCM or PLL). This is done by checking the HDMI GT Controller core customizationscreen option, Use 4th GT Channel as TX TMDS Clock. The gt_tx3 interface port must beconnected to the GT Wizard’s TX3_GT_IP_Interface. Ensure that the Number of TX Lanes isfour in the GT Wizard customization screen.





Figure 6: 4th GT Channel as TX TMDS Clock

When this option is enabled, the TX TMDS Clock ports, tx_tmds_clk_p/n output ports aredisabled.

A pattern generator module is added in the HDMI GT Controller architecture to generate thespecific pattern needed to generate the required TMDS clock frequency from the 4th GTchannel. The pattern generator control register is located at offset 0x340 and is programmedbased on the line rate to TMDS clock ratio. The pattern generator supports ratio of 10, 20, 30,40, and 50. For example, in a typical HDMI 1.4 resolution such as 1080p60, the line rate perchannel is 1.485 Gb/s and the TMDS clock is 148.5 MHz, thus giving a ratio of 10. For low linerate resolutions such as 480P60 which needs an oversampling technique (for example, x3) to betransmitted, the ratio is computed as actual line rate per channel (270 Mbs x 3) over TMDS clock(27 MHz), which gives a ratio of 30. For HDMI 2.0 resolution such as 4KP60, the line rate is 5.94Gb/s and TMDS clock is 148.5 MHz, thus giving a ratio of 40.

ResetsThis core uses two GT RESET IP to handle the GT Wizard’s reset FSM, one for TX and the otherfor RX.





InterruptsThis core issues an active-High IRQ and must be used with an interrupt controller that is Level-High sensitive. Using sensitivity modes other than what was specified might result in incorrectsoftware behavior.

Program and Interrupt FlowThe HDMI GT Controller core driver manages the dynamic reconfiguration of the multi-gigabittransceiver and digital clock manager modules to allow seamless transmission and reception ofHDMI video to and from the FPGA physical interface.

The main program flow is shown in the following sections. At execution, the software applicationinitializes the HDMI GT Controller IP and registers the callback functions in the provided hooks.After the initialization, all API calls are interrupt triggered starting from either TX or RX referenceclock change.

Note: The HDMI GT Controller driver does not carry the video format, resolution, or color spaceinformation. Such information is handled by the HDMI TX and RX MAC. See the HDMI 1.4/2.0 TransmitterSubsystem Product Guide (PG235) and the HDMI 1.4/2.0 Receiver Subsystem Product Guide (PG236) for moreinformation.

HDMI TX FlowIn TMDS mode, a change in the TX reference clock signifies a video format change which triggersa series of interrupts until the GT TX attains the TX Reset Done status. The TX frequency changeis based on the toggling (deassertion then assertion) of the tx_refclk_rdy port or it can beforced by setting TX Frequency Reset bit (bit 3) of the Clock Detector Control register (0x200).This bit is self clearing. See HDMI Reference Clock Requirements (link below) for details abouttx_refclk_rdy port implementation.

There are several API callback hooks that the HDMI GT Controller core execute throughout theHDMI TX operation. If necessary, these callbacks are available for inserting or adding morefunction calls on top of what is in the software application.







Figure 7: HDMI TX Program Flow

START

IP Initialization & Callback Setup

TX Refclk Change Intr?

N

Y

TX Timer Timeout Intr?

Y

TX TMDS Patgen Disable

TX MMCM Lock Mask

TX GPO Intr?

N

Y

TX RSTDONE Intr?

Y

Set TX GPI = 0xF

Enable TX Debounce TimerSet TX GPI = 0x0

TX TMDS Patgen Enable

Call HDMI TX Init Callback Function

B

N

GT TX Channels Reconfig

TX MMCMReconfig

Call HDMI TX Ready Callback

Function

X23330-100719

Note: B in the previous figure continues on the next figure.

Related Information






HDMI GT Controller Core Driver TX CallbacksThe HDMI GT Controller core driver TX callbacks are:

• HDMI GT Controller HDMI TX Init Callback: This callback is namedXHDMIPHY1_HDMI_HANDLER_TXINIT in the HDMI GT Controller core driver. It is executedor called every time a change in the HDMI TX Transition Minimized Differential Signaling(TMDS) clock frequency occurs. This normally triggers a reset to the HDMI TX Subsystem IP.

• HDMI GT Controller HDMI TX Ready Callback: This callback is namedXHDMIPHY1_HDMI_HANDLER_TXREADY in the HDMI GT Controller core driver. It isexecuted or called every time the HDMI GT Controller core driver completes the initializationroutine necessary for the TX video format change.

HDMI RX FlowIn TMDS mode, a change in RX reference clock signifies a video format change which triggers aseries of interrupts until the GT RX attains the RX Reset Done status.

There are several API callback hooks that the HDMI GT Controller core execute throughout theHDMI RX operation. If necessary, these callbacks are available for inserting or adding morefunction calls on top of what is in the software application.





Figure 8: HDMI RX Program Flow

RX Refclk Change Intr?

N

Y

RX Timer Timeout Intr?

Y

RX MMCM Lock Mask

Disable NIDRU

RX GPO Intr?

N

N

Y

RX RSTDONE Intr?

N

Y

RX PLL Reconfig

Enable/Disable NIDRU

Enable RX Debounce Timer

Set RX GPI = 0xF

Set RX GPI = 0x0

Call HDMI RX Ready Callback

Function

Call HDMI RX Init Callback Function

A

B

GT RX ChannelsReset

X23331-100819

HDMI GT Controller Core Driver RX CallbacksThe HDMI GT Controller core driver RX callbacks are:

• HDMI GT Controller HDMI RX Init Callback: This callback is namedXHDMIPHY1_HDMI_HANDLER_RXINIT in the HDMI GT Controller core driver. It is executedor called every time a change in the HDMI RX TMDS clock frequency occurs.

• HDMI GT Controller HDMI RX Ready Callback: This callback is namedXHDMIPHY1_HDMI_HANDLER_RXREADY in the HDMI GT Controller core driver. It isexecuted or called every time the HDMI GT Controller core driver completes the initializationroutine necessary for the RX video format change. The hook normally updates the clock andline rate parameters of the HDMI RX Subsystem IP.





Versal ACAP GTY HDMI GT ControllerImplementation

The GTYE5 transceiver in the Versal™ ACAPs have two main types of PLLs, the LCPLL and theRPLL. One Quad has four channels which are clustered into two Duals, HSCLK0 and HSCLK1.Channels 0 and 1 are clustered in HSCLK0 while Channels 3 and 4 are clustered in HSCLK1. EachHSCLK dual has one LCPLL and RPLL which can only provide a clock to the channels they areclustered with. The HDMI GT Controller core uses all of the PLL types to support transmitter andreceiver operations simultaneously. The HDMI GT Controller core allows you to choose whetherto use the HSCLK0/1_LCPLL or the HSCLK0/1_RPLL on the transmitter. The receiver should usethe other PLL type that was not chosen for TX and vice versa. The GTYE5 transceiver has aminimum line rate support of 1.25 Gb/s per channel.

Block automation must be run on the HDMI GT Controller core after its graphical user interface(GUI) configuration to automatically instantiate and connect to the GT Wizard. This process alsoensures that the GT Wizard is preloaded with the necessary configurations such as the line rateconfiguration table (see the following table) which are needed for HDMI™ operation.

RPLL UseUsing the RPLL for the HDMI receiver includes certain restrictions. The TX does not have theserestrictions because the GT driver uses oversampling techniques to work around the limitationsof the RPLL. The HDMI RX limitations for the RPLL are described in this section.

The RPLL voltage controlled oscillator (VCO) must run in the range of 4.0 GHz to 8.0 GHz. TheVCO frequency is dependent on the TMDS clock frequency. The RPLL can apply a limited set ofmultipliers to the TMDS clock frequency. The GT driver measures the TMDS clock frequency andattempts to find a suitable line rate configuration to complete the reconfiguration process. If thedetected TMDS Clock frequency is outside normal operating mode, the HDMI GT Controllerswitches to NI-DRU Mode for RX or Oversampling mode for TX.

• NI-DRU mode: When the GT driver detects that the TMDS clock frequency is less than 125MHz, it enables the NI-DRU to receive bit rates that are less than 1.25 Gb/s. The NI-DRU runsat 2.5 Gb/s, which enables it to recover line rates that cannot be supported by the transceiver.

• Oversample Mode: When the GT driver detects that the TMDS clock frequency is less than125 MHz, it puts the TX in oversampling mode and applies a multiplier of 2, 3, or 5 to theTMDS clock to put the TX above the minimum line rate.





Table 52: Versal GTY RPLL Line Rate Configuration Table

TMDS ClockFrequency

(MHz)Line Rate (Gb/s) Line Rate CFG* HDMI Standard Notes

<120 TX: 1 or 2RX: 0

HDMI 1.4 TX: OversamplingRX: NI-DRU is used

125 to 200.0 1.25 to 2.0 1 HDMI 1.4 CDR is used

200.0 to 297 2.0 to 2.97 2 HDMI 1.4 CDR is used


100.0 to 148.5 4.0 to 5.94 4 HDMI 2.0 CDR is used

Note: The Line Rate CFG value is the configuration selection driven into the GT TXRATE or RXRATE portsdepending which side RPLL is used with.

The following table is for illustration only. For unlisted color formats, support might be possible ifthey are not restricted by the VCO frequency range.

Table 53: RPLL Support of RGB and YCbCr 4:4:4 Video Formats

Resolution (Hz)Bits Per Pixel

24 30 36 48480i60 DRU DRU DRU DRU

576i50 DRU DRU DRU DRU

1080i50 DRU DRU DRU √


480p60 DRU DRU DRU DRU


720p50 DRU DRU DRU √





1080p50 √ √ √ √

1080p60 √ √ √ √

2160p24 √ √ √ √

2160p25 √ √ √ √

2160p30 √ √ √ √

2160p60 √ 1 1 1

VGA 60 DRU DRU DRU DRU

SVGA 60 DRU DRU DRU DRU

XGA 60 DRU DRU DRU √

SXGA 60 DRU √ √ √

WXGA 60 DRU DRU DRU √





Table 53: RPLL Support of RGB and YCbCr 4:4:4 Video Formats (cont'd)


24 30 36 48WXGA + 60 DRU DRU √ √

UXGA 60 √ √ √ 2

WUXGA 60 √ √ √ √

WSXGA 60 √ √ √ √

Notes:1. Format is not supported because it exceeds the maximum line rate of HDMI 2.0.2. Format is above the design routing.

LCPLL UseUsing the LCPLL for the HDMI receiver includes certain restrictions. The TX does not have theserestrictions because the GT driver uses oversampling techniques to work around the limitationsof the LCPLL. The HDMI RX limitations for the LCPLL are described in this section.

The LCPLL voltage controlled oscillator (VCO) must run in the range of 8.0 GHz to 16.375 GHz.The VCO frequency is dependent on the TMDS clock frequency. The LCPLL can apply a limitedset of multipliers to the TMDS clock frequency. The GT driver measures the TMDS clockfrequency and attempts to find a suitable line rate configuration to complete the reconfigurationprocess. If the detected TMDS Clock frequency is outside normal operating mode, the HDMI GTController switches to NI-DRU Mode for RX or Oversampling mode for TX.

• NI-DRU mode: When the GT driver detects that the TMDS clock frequency is less than 125MHz, it enables the NI-DRU to receive bit rates that are less than 1.25 Gb/s. The NI-DRU runsat 2.5 Gb/s, which enables it to recover line rates that cannot be supported by the transceiver.

• Oversample Mode: When the GT driver detects that the TMDS clock frequency is less than125 MHz, it puts the TX in oversampling mode and applies a multiplier of 2, 3, or 5 to theTMDS clock to put the TX above the minimum line rate.

Table 54: Versal ACAP GTY LCPLL Line Rate Configuration Table

TMDS Clock Frequency (MHz) Line Rate(Gb/s)

Line RateCFG*

HDMIStandard Notes

<120 TX: 1 or 2RX: 0

HDMI 1.4 TX: OversamplingRX: NI-DRU is used


204.688 to 297 2.046 to 2.97 2 HDMI 1.4 CDR is used


102.344 to 148.5 4.094 to 5.94 4 HDMI 2.0 CDR is used





IMPORTANT! The Line Rate CFG value is the configuration selection driven into the GT TXRATE orRXRATE ports depending which side LCPLL is used with.

The following table is for illustration only. For unlisted color formats, support might be possible ifthey are not restricted by the VCO frequency range.

Table 55: LCPLL Support of RGB and YCbCr 4:4:4 Video Formats


24 30 36 48480i60 DRU DRU DRU DRU

576i50 DRU DRU DRU DRU










1080p50 √ √ √ √

1080p60 √ √ √ √

2160p24 √ √ √ √

2160p25 √ √ √ √

2160p30 √ √ √ √

2160p60 √ 1 1 1

VGA 60 DRU DRU DRU DRU

SVGA 60 DRU DRU DRU DRU

XGA 60 DRU DRU DRU √

SXGA 60 DRU √ √ √

WXGA 60 DRU DRU DRU √

WXGA + 60 DRU DRU √ √

UXGA 60 √ √ √ 2

WUXGA 60 √ √ √ √

WSXGA 60 √ √ √ √

Notes:1. Format is not supported because it exceeds the maximum line rate of HDMI 2.02. Format is above the design routing





Chapter 5

Design Flow StepsThis section describes customizing and generating the core, constraining the core, and thesimulation, synthesis, and implementation steps that are specific to this IP core. More detailedinformation about the standard Vivado® design flows and the IP integrator can be found in thefollowing Vivado Design Suite user guides:

• Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994)

• Vivado Design Suite User Guide: Designing with IP (UG896)

• Vivado Design Suite User Guide: Getting Started (UG910)

• Vivado Design Suite User Guide: Logic Simulation (UG900)

Customizing and Generating the CoreThis section includes information about using Xilinx® tools to customize and generate the core inthe Vivado® Design Suite.

If you are customizing and generating the core in the Vivado IP integrator, see the Vivado DesignSuite User Guide: Designing IP Subsystems using IP Integrator (UG994) for detailed information. IPintegrator might auto-compute certain configuration values when validating or generating thedesign. To check whether the values do change, see the description of the parameter in thischapter. To view the parameter value, run the validate_bd_design command in the Tclconsole.

You can customize the IP for use in your design by specifying values for the various parametersassociated with the IP core using the following steps:

1. Select the IP from the IP catalog.

2. Double-click the selected IP or select the Customize IP command from the toolbar or right-click menu.

For details, see the Vivado Design Suite User Guide: Designing with IP (UG896) and the VivadoDesign Suite User Guide: Getting Started (UG910).

Figures in this chapter are illustrations of the Vivado IDE. The layout depicted here might varyfrom the current version.

Chapter 5: Design Flow Steps


https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug994-vivado-ip-subsystems.pdf

https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug896-vivado-ip.pdf

https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug910-vivado-getting-started.pdf

https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug900-vivado-logic-simulation.pdf






Configuration TabFigure 9: Configuration Tab

The Vivado IDE displays a representation of the IP symbol on the left side, and the parameterassignments on the right side which are described as follows:

• Component Name: The component name is used as the base name of the output filesgenerated for the module. Names must begin with a letter and must be composed fromcharacters: a to z, 0 to 9 and "_". The name hdmi_gt_controller cannot be used as a componentname.

• Transceiver: Specifies the types of transceiver that is used in this core. This option is noteditable and depends on the device family.

• Transceiver Width: Specifies the width of the transceiver that is used in this core.

• Tx/Rx Protocol Selection: Specifies the protocol that is supported under this core. None orHDMI can be selected under this selection.

Note: When Tx/Rx Protocol Selection is set to None, some of the options such as PLL type and RefClock Selection are still open for changes and is vary per protocol of opposite direction. These optionscan be ignored when Tx/Rx Protocol Selection is set to None. Consider the following scenarios asexamples:

• Tx is HDMI and Rx is None.

○ The only configurable options on Rx are Rx PLL Type and Rx Ref Clock Selection





○ There is an automatic checking on PLL Type which disallow the setting of the same PLL type forTX and RX.

○ For Rx Ref Clock Selection, the setting has no impact on the refclk port.

• Tx/Rx Max GT Line Rate: Specifies the maximum line rate for the transceiver. For HDMIprotocol, this option is fixed to 5.94 Gb/s.

• Tx/Rx Channel: Specifies the number of transceiver channels to be used with this core. ForHDMI protocol, this option defaults to 3 channels, however it can be 4 for the TX when theUse 4th GT Channel as TX TMDS Clock option is enabled.

• Tx/Rx Ref Clock Selection: Specifies the reference clock that corresponds to the transceiver.

• TX REFCLK Ready Active: Specifies active-Low/High for Tx RefClk Ready. This option isdisplayed when HDMI protocol is selected.

• Use 4th GT Channel as TX TMDS Clock: To enable/disable the function specifies as per thedisplay option. This option is displayed when HDMI protocol is selected.

• Ni-DRU: When checked, the NI-DRU is included in the core. This option is displayed whenHDMI protocol is selected for receiver.

• Ni-DRU Ref Clock Selection: Specifies the reference clock that corresponds to the NI-DRU.This option is displayed when HDMI protocol is selected for receiver.

IMPORTANT! There is no automatic check between the DRU Ref Clock and the RX/TX Ref ClockSelection so you should avoid using the same clock for the DRU Ref Clock as either the TX or RX PLLRef Clock.

• Number of pixels per clock: Specifies the number of pixels for video clock generation.

User ParametersThe following table shows the relationship between the fields in the Vivado® IDE and the userparameters (which can be viewed in the Tcl Console).

Table 56: User Parameters

Vivado IDE Parameter/Value1 User Parameter/Value Default ValueTx/Rx Protocol Selection

NoneHDMI

C_Tx/Rx_Protocol HDMI

Tx/Rx Max GT Line Rate Rx_Max_GT_Line_Rate HDMI: 5.94

Tx/Rx Channels C_Tx/Rx_No_Of_Channels 3

Tx PLL Type2

LCPLL: 7RPLL: 8

C_TX_PLL_SELECTION LCPLL





Table 56: User Parameters (cont'd)

Vivado IDE Parameter/Value1 User Parameter/Value Default ValueRx PLL Type2

(similar to TX PLL Type)C_RX_PLL_SELECTION RPLL

Tx Ref Clock Selection2

GT REFCLK0: 0GT REFCLK1: 1GT REFCLK2: 2GT REFCLK3: 3GT REFCLK4: 4GT REFCLK5: 5

C_TX_REFCLK_SEL GT REFCLK1

Rx Ref Clock Selection2

(similar to Tx Ref Clock Selection)C_RX_REFCLK_SEL GT REFCLK0

TX REFCLK Ready Active C_Txrefclk_Rdy_Invert false

Use 4th GT Channel as TX TMDS Clock C_Use_GT_CH4_HDMI false

NI-DRU C_NIDRU true

NI-DRU Ref Clock Selection(similar to Tx Ref Clock Selection)

C_NIDRU_REFCLK_SEL GT REFCLK2

Number of pixels per clock Value Selection24

C_INPUT_PIXELS_PER_CLOCK 4

Transceiver Width Value Selection24

Transceiver_Width 4

Use ODDR/ODDRE1 for TX and RX differentialTMDS clock out

C_Use_Oddr_for_Tmds_Clkout2 true

TX TMDS Clock output buffernone, bufg3

C_Tx_Tmds_Clk_Buffer2 bufg

TX Video Clock output buffernone, bufg3

C_Tx_Video_Clk_Buffer2 bufg

RX TMDS Clock output buffernone, bufg3

C_Rx_Tmds_Clk_Buffer2 bufg

RX Video Clock output buffernone, bufg3

C_Rx_Video_Clk_Buffer2 bufg

DRU Reference Clock FrequencyValid values

400.00200.00

C_DRU_Refclk_Freq_MHz 400.00

Notes:1. Parameter values are listed in the table where the Vivado IDE parameter value differs from the user parameter value.

Such values are shown in this table as indented below the associated parameter.2. The user parameter applies to HDMI only and can be configured through a Tcl command or through the Block

Properties Window in IP integrator. Example:set_property -dict [list CONFIG.C_Rx_Video_Clk_Buffer {bufg}] [get_ips <ip name>]set_property -dict [list CONFIG.C_Use_Oddr_for_Tmds_Clkout {false}] [get_ips <ip name>]

3. See Clocking.





Related Information

Clocking

Output GenerationFor details, see the Vivado Design Suite User Guide: Designing with IP (UG896).

Constraining the CoreOut-of-Context ConstraintsWhen an out-of-context (OOC) design flow such as OOC synthesis or hierarchical design is used,the PHY also uses a special OOC XDC file customized for that instance. The OOC XDC fileprovides default period constraints on clock ports that would otherwise be constrained by theSystem XDC file.

Required ConstraintsGT clocking and location constraints must be added in the top level constraint file.

Device, Package, and Speed Grade SelectionsThe core constraints generated for a given instance reflect the selections made during IPcustomization for the target device. If you wish to use a different device, package, or speedgrade, use the Vivado IDE to select the desired part and re-customize the core rather thanmodifying an XDC file.

Clock Frequencies


The HDMI GT Controller application requires a system clock and a minimum of three GTreference clock inputs for full duplex operation:

• System Clock

• HDMI TX from an external clock generator

• HDMI RX in CDR mode (normal operation)

• HDMI 1.4/2.0 RX NI-DRU mode






The system clock should drive the sb_aclk and the axi4lite_aclk; the ports should beconnected to a 100 MHz clock. The system clock must be properly buffered (using BUFG) beforeit can be used and connected.

IMPORTANT! Because the system clock is used by the HDMI GT Controller as the reference clock for thefrequency counter in its Clock Detector module, use an oscillator that has a jitter of less than ±40 PPM.

Note the following constraints for the HDMI 1.4/2.0 reference clock:

• The HDMI TX and RX reference clock (Transition Minimized Differential Signaling (TMDS)clocks) input frequency varies according to the input video and both are maximized at 297MHz. The corresponding input ports need to be constrained at 297 MHz at the Vivado Projecttop level XDC file for proper timing analysis and closure; that is, create_clock -period3.367 [get_ports <HDMI TX/RX REFCLK portname>].

• The NI-DRU reference clock frequency can be chosen from 3 values: 125.00 MHz, 200.00MHz or 400.00 MHz. The NI-DRU reference clock frequency must be constrained at theVivado Project top level XDC file at specified frequency; for example, 125 MHz:create_clock -period 8.000 [get_ports <NI-DRU REFCCLK portname>]

Note: Although theoretically a vast range of REFCLK frequencies can be used with NI-DRU, only theindicated frequencies have been tested and characterized per transceiver type. NI-DRU settings, such asgain, were optimized and validated using the indicated frequencies. The REFCLK frequency was selectedto support the NI-DRU operation, thereby minimizing the number of REFCLKs needed for full HDMIoperation.

The following figure illustrates the full reference clock requirement connections.





Figure 10: HDMI GT Controller Reference Clock Connections

External Clock Generator

(for HDMI TX)

Versal ACAP

HDMI GTController

TX

RX

txrefclk clock p/n

nidru refclk clock p/n

rxrefclk clock p/n

txoutclk

tx_video_clk

tx_tmds_clk

tx_tmds_clk_p/n

HDMI TX Fabric

rx_tmds_clk_p/n

rx_video_clk

rx_tmds_clk

HDMI RX Fabric

GT Wizard

TX

RX

txrefclk odiv2

nidru odiv2

txoutclk

rxoutclk rxoutclk

rxrefclk odiv2TMDS RX Clock from HDMI RX

Interface

NI-DRU Clock Oscillator

X23332-103019

The HDMI TX reference clock comes from an external programmable clock generator capable ofgenerating a range of frequencies from the minimum PLL reference clock (see HDMI TXOversampled Reference Clock Requirements) to the maximum TMDS clock for supported videoformats. For example, the HDMI GT Controller TX uses LCPLL and supports up to 4Kp60 at twopixels per clock. This means the programmable clock generator must be able to generatefrequencies from 125 MHz to 297 MHz. For resolutions requiring lower TMDS clock than theminimum PLL reference clock, the HDMI GT Controller uses the oversampling technique (see thefollowing section for details).

IMPORTANT! The txrefclk port is accompanied by tx_refclk_rdy port which indicates a lockcondition. The tx_refclk_rdy port has three requirements:

• It is connected to the external clock generator lock pin by default or can be toggled throughGPIO. It must be toggled (deasserted then asserted) for every video format change. Alternatively,the TX Frequency Reset bit (bit 3) of the Clock Detector Control register (0x200) can be set if thetx_refclk_rdy port is active.

• It can only be asserted when the clock at txrefclk_p/n port is stable.

• At AXILITE CLK = 100 MHz, the tx_refclk_rdy minimum hold time is 5 μs.

Failing to meet these requirements causes instability to the system.





TX REFCLK frequency detection is sensitive only to the behavior of the tx_refclk_rdy port, achange on which triggers the clock detector to issue the TX frequency change event. Theexternal clock generator is set up for the desired TX clock frequency, which means that theHDMI GT Controller TX should get the requested frequency from the clock generator. Becausethe assumption is that the HDMI GT Controller gets the correct clock, it only requires the LOCKevent to trigger the TX reconfiguration which is represented by the assertion oftx_refclk_rdy.

Note: This mechanism applies only for the TX. The RX is sensitive to the frequency change because there isno user control on the incoming RX TMDS clock.

Related Information

HDMI TX Oversampled Reference Clock Requirements

HDMI TX Oversampled Reference Clock Requirements

In normal cases, the GT reference clock requirement is equal to the TMDS clock requirement of agiven HDMI resolution.

Note: The GT reference clock requirement value can be accessed through the HdmiTxRefClkHz variablein the HDMI GT Controller data structure declared in the application (for example, in reference design:Hdmiphy1.HdmiTxRefClkHz). The HdmiTxRefClkHz value is valid and can be accessed any time afterTX Timer Timeout Interrupt occurs (see the HDMI TX Flow). This value is ideally used in programming theexternal clock generator frequencies for GT TX operation.

The HDMI GT Controller TX application enters the oversampling mode when the reference clockand line rate required by video resolution to be transmitted is below the minimum supported bythe transceiver. The HDMI GT Controller driver increases the reference clock and line rate by afactor of x2, x3 or x5 until the minimum line rate for the transceiver is achieved. The followingtable shows the minimum line rate per transceiver and PLL types.

For example, the GTYE5 LCPLL needs to transmit 480p 60 Hz at eight bits per component. Thisvideo format requires a TMDS clock and line rate of 27 MHz and 270 Mb/s respectively which isbelow the GTYE5’s minimum supported line rate. The HDMI GT Controller driver searches forthe oversampling factor that satisfies this condition, which is x5. The new GT reference clock andline rate are 135 MHz and 1.35 Gb/s.

Table 57: HDMI Transceiver to PLL Type Minimum Reference Clock

Transceiver Type PLL Type Min Reference Clock/Line Rate (MHz)GTYE5 LCPLL 125 MHz / 1.25 Gb/s

RPLL 125 MHz / 1.25 Gb/s

Related Information

HDMI TX Flow





HDMI TX Clock Requirement Example

The frequency range of the external programmable clock generator must be selected based onthe transceiver type and the PLL type for TX. The following table shows the frequency rangeneeded from the clock generator if the HDMI GT Controller is used to support all the videoformats in the tables in the HDMI GT Controller HDMI Implementation section.

Table 58: External Clock Generator Typical Frequency Range

Configuration TX PLL Reference Clock Range (MHz)GTYE5 LCPLL 125 to 297

RPLL 125 to 297

The following table shows the external clock generator frequency range if the HDMI GTController TX is used to support video formats of SMPTE-SDI: SD-SDI, HD-SDI, and 3G-SDIwhich in HDMI have equivalent TMDS clocks 27, 74.25, or 74.25/1.001 MHz and 148.5 or148.5/1.001 MHz, respectively. SD-SDI and HD-SDI reference clock are below the minimumthreshold of all PLL types thus oversampling mode must be used to support it. HD-SDI referenceclock is below the minimum threshold of GTYE5 LCPLL and RPLL thus oversampling mode mustbe used to support it for corresponding transceiver and PLL types.

Table 59: External Clock Generator Frequency Range for SMPTE-SDI

TransceiverType TX PLL

ReferenceClock Range

(MHz)Remarks

GTYE5 LCPLL 125 to 148.5 SD-SDI uses x5 oversamplingHD-SDI uses x2 oversampling

RPLL 125 to 148.5 SD-SDI uses x5 oversamplingHD-SDI uses x2 oversampling

HDMI Generated Clocks

The HDMI GT Controller IP generates the TX TMDS, link and video clocks that are required byHDMI 1.4/2.0 Transmitter Subsystem. See the Clocking section of the HDMI 1.4/2.0 TransmitterSubsystem Product Guide (PG235) for more information.

The HDMI GT Controller IP generates the RX link and video clocks that are required by theHDMI 1.4/2.0 Receiver Subsystem. See the Clocking section of the HDMI 1.4/2.0 ReceiverSubsystem Product Guide (PG236) for more information.

Clock ManagementThis section is not applicable for this IP core.







Clock PlacementYou are expected to create package pin constraints for each instantiated transceiver differentialreference clock buffer primitive as well as each instantiated differential recovered clock outputbuffer primitive, if used. The constraints reflect the transceiver primitive site locations.

The MGT reference clock frequency must be constrained at the Vivado Project top level XDC fileat specified frequency; that is, for GTYE5: create_clock -period 3.367 [get_portsHDMI_RX_CLK_IN_clk_p]

BankingThe HDMI GT Controller core does not support multiple GT bank/quad in one IP instance.Multiple HDMI GT Controller instances are needed for applications requiring more than oneactive GT bank/quad.

Note: The majority of APIs in the HDMI GT Controller driver include the "QuadId" argument. This must bepermanently set to 0, because the HDMI GT Controller only supports one GT bank/quad per instance.

Transceiver PlacementYou must create an XDC file with location constraints for each enabled transceiver channelprimitive. The constraints reflect the transceiver primitive site locations.

I/O Standard and Placement

TMDS Clock

The TX TMDS clock output is implemented as differential output when theC_Use_GT_CH4_HDMI user parameters is set to false. If the parameter is set to true, the GTChannel 3 (4th channel) location must be properly constrained at the Vivado project top levelXDC.

The RX TMDS and NI_DRU clock inputs are implemented as a GT reference clock input andtherefore I/O standard constraints are not required.

IO Standard:

TX TMDS: set_property IOSTANDARD LVDS [get_ports HDMI_TX_CLK_P_OUT]RX TMDS & NI-DRU: N/A

Sample Pin Assignments:

TX TMDS: set_property PACKAGE_PIN H21 [get_ports HDMI_TX_CLK_P_OUT] RX TMDS: set_property PACKAGE_PIN C8 [get_ports HDMI_RX_CLK_P_IN] NI-DRU: set_property PACKAGE_PIN G8 [get_ports DRU_CLK_IN_clk_p]





Board design and connectivity should follow the HDMI standard recommendations with properlevel shifting or TMDS driver use.

High-Speed I/O

The three or four differential pairs of TX and RX high-speed lanes are implemented as GT TX andRX channels respectively thus IO standard constraints are not required. Board design andconnectivity should follow HDMI standard recommendations. Only the package pin assignmentsare needed for the GT channels.

Sample Pin Assignments:

set_property PACKAGE_PIN AB7 [get_ports TX_DATA_OUT_txp[0]]set_property PACKAGE_PIN AA9 [get_ports TX_DATA_OUT_txp[1]]set_property PACKAGE_PIN Y7 [get_ports TX_DATA_OUT_txp[2]]set_property PACKAGE_PIN W9 [get_ports TX_DATA_OUT_txp[3]]

set_property PACKAGE_PIN AB2 [get_ports RX_DATA_IN_rxp[0]]set_property PACKAGE_PIN AA4 [get_ports RX_DATA_IN_rxp[1]]set_property PACKAGE_PIN Y2 [get_ports RX_DATA_IN_rxp[2]]set_property PACKAGE_PIN W4 [get_ports RX_DATA_IN_rxp[3]]

Board Design Guidelines - HDMI

Transmitter

Figure 11: Transmitter Board

GTTX

TMDSRX

M/GTAVCC1.2V

TMDSLevel

Shifter

3V3

FPGA Receiver

X18963-012819

• The GT transmitter does not support TMDS Level Signaling and must be used with a cabledriver to be compliant with TMDS specification.





• TMDS Level Shifting can be done using external level shifter ASSPs such as:

○ Texas Instruments SN65DP159

• Board design simulation must be done to ensure proper operation.

Receiver

Figure 12: Receiver Board

GTRX

Retimer/EQ/

Repeater

M/GTAVCC

Transmitter FPGA

3V3

X18964-012819

• The GT Receiver does not support TMDS Level Signaling and must be used with a retimer orequalizer to be compliant with the TMDS specification.

• TMDS levels are emulated using external pull-up resistors (located close to the device GTs)

• Use external TMDS Retimer/EQ chip recommended for HDMI 2.0 data rates such as:

○ Texas Instruments TMDS181

• Board design simulation must be done to ensure proper operation.

Synthesis and ImplementationFor details about synthesis and implementation, see the Vivado Design Suite User Guide: Designingwith IP (UG896).






Chapter 6

Example DesignSee the Application Software Development section of HDMI 1.4/2.0 Transmitter SubsystemProduct Guide (PG235) and HDMI 1.4/2.0 Receiver Subsystem Product Guide (PG236) for details onrunning the HDMI example design flow.

Chapter 6: Example Design






Appendix A

Verification, Compliance, andInteroperability

For a list of tested boards, see the Example Design chapter.

Related Information

Example Design

Appendix A: Verification, Compliance, and Interoperability




Appendix B

UpgradingThis appendix is not applicable for the first release of the core.

Appendix B: Upgrading




Appendix C

DebuggingThis appendix includes details about resources available on the Xilinx® Support website anddebugging tools.

If the IP requires a license key, the key must be verified. The Vivado® design tools have severallicense checkpoints for gating licensed IP through the flow. If the license check succeeds, the IPcan continue generation. Otherwise, generation halts with an error. License checkpoints areenforced by the following tools:

• Vivado Synthesis

• Vivado Implementation

• write_bitstream (Tcl command)

IMPORTANT! IP license level is ignored at checkpoints. The test confirms a valid license exists. It does notcheck IP license level.

Finding Help on Xilinx.comTo help in the design and debug process when using the core, the Xilinx Support web pagecontains key resources such as product documentation, release notes, answer records,information about known issues, and links for obtaining further product support. The XilinxCommunity Forums are also available where members can learn, participate, share, and askquestions about Xilinx solutions.

DocumentationThis product guide is the main document associated with the core. This guide, along withdocumentation related to all products that aid in the design process, can be found on the XilinxSupport web page or by using the Xilinx® Documentation Navigator. Download the XilinxDocumentation Navigator from the Downloads page. For more information about this tool andthe features available, open the online help after installation.

Appendix C: Debugging


https://www.xilinx.com/support.html

https://forums.xilinx.com/




https://www.xilinx.com/support/download.html



Answer RecordsAnswer Records include information about commonly encountered problems, helpful informationon how to resolve these problems, and any known issues with a Xilinx product. Answer Recordsare created and maintained daily ensuring that users have access to the most accurateinformation available.

Answer Records for this core can be located by using the Search Support box on the main Xilinxsupport web page. To maximize your search results, use keywords such as:

• Product name

• Tool message(s)

• Summary of the issue encountered

A filter search is available after results are returned to further target the results.

Master Answer Record for the Core

AR 72991

Technical SupportXilinx provides technical support on the Xilinx Community Forums for this LogiCORE™ IP productwhen used as described in the product documentation. Xilinx cannot guarantee timing,functionality, or support if you do any of the following:

• Implement the solution in devices that are not defined in the documentation.

• Customize the solution beyond that allowed in the product documentation.

• Change any section of the design labeled DO NOT MODIFY.

To ask questions, navigate to the Xilinx Community Forums.

Debug ToolsThere are many tools available to address HDMI GT Controller design issues. It is important toknow which tools are useful for debugging various situations.





https://www.xilinx.com/support/answers/72991.htm





Vivado Design Suite Debug FeatureThe Vivado® Design Suite debug feature inserts logic analyzer and virtual I/O cores directly intoyour design. The debug feature also allows you to set trigger conditions to capture applicationand integrated block port signals in hardware. Captured signals can then be analyzed. Thisfeature in the Vivado IDE is used for logic debugging and validation of a design running in Xilinx®

devices.

The Vivado logic analyzer is used to interact with the logic debug LogiCORE IP cores, including:

• ILA 2.0 (and later versions)

• VIO 2.0 (and later versions)

See the Vivado Design Suite User Guide: Programming and Debugging (UG908).

Reference BoardsVarious Xilinx® development boards support the HDMI GT Controller core. These boards can beused to prototype designs and establish that the core can communicate with the system.

• Versal VCK190 Evaluation Kit

Note: Ensure that you have installed the VCK190 board support files. To do this, when you get to theDefault Part screen, select the Boards tab, and select Install/Update Boards. This takes you to the XhubStores, where you can right click on the VCK190 board and select Install.

Interface DebugAXI4-Lite InterfacesRead from a register that does not have all 0s as a default to verify that the interface isfunctional. Output s_axi_arready asserts when the read address is valid, and outputs_axi_rvalid asserts when the read data/response is valid. If the interface is unresponsive,ensure that the following conditions are met:

• The axi4lite_aclk input is connected and toggling.

• The interface is not being held in reset, and axi4lite_aresetn is an active-Low reset.

• The interface is enabled, and s_axi_aclken is active-High (if used).

• The main core clocks are toggling and that the enables are also asserted.



https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug908-vivado-programming-debugging.pdf



AXI4-Stream InterfacesIf data is not being transmitted or received, check the following conditions:

1. If transmit <interface_name>_tready is stuck Low following the<interface_name>_tvalid input being asserted, the core cannot send data.

2. If the receive <interface_name>_tvalid is stuck Low, the core is not receiving data.

3. Check that the aclk inputs are connected and toggling.

4. Check that the AXI4-Stream waveforms are being followed.

5. Check core configuration.

HDMI Debugging• What to check if I do not see TX or RX Frequency Events?

1. Make sure HDMI cable is properly inserted.

2. Ensure that the correct GTREFCLK input pins are connected according to Customizing andGenerating the Core.

3. Ensure that cable detect and HPD pins are properly connected with correct active levelsetting in the HDMI TX or RX subsystem GUI.

4. Try connecting with a different cable.

• Why does the HDMI GT Controller log shows error saying no DRU instance?

1. This indicates that HDMI design received a video carrying a TMDS Clock that is below thePLL thresholds and there is no NI-DRU in the IP instance to receive it.

2. The DRU must be enabled from the IP GUI to be able to receive resolutions below the PLLthreshold. The DRU must be supplemented with a corresponding GT clock based on therequirements listed in Reference Clocks Requirements.

3. Ensure the GTREFCLK is present and is driving the PLL.

4. Try toggling the PLL_GT_RESET bits of TXI or RXI registers.

5. Ensure that the HDMI GT Controller driver and IP versions are from the same Vivadobuild.

• Why do I see DRU reference clock frequency equal to 1 Hz?

This happens when the clock detector module identifies a mismatch between the actual andrequired DRU REFCLK frequency. This can be due to two reasons:

• The DRU clock frequency is outside ±10 kHz tolerance of the required frequency.

• When the DRU Ref Clock Selection is same as the RX or TX Ref Clock Selection, disablingthe RX or TX Ref Clock Selection can also disable the DRU Ref Clock, which reports theDRU clock frequency as equal to 1 Hz.





TX Only Sample HDMI GT Controller Log

The following log entries were taken from a HDMI GT Controller using LCPLL to clock the TX.

HDMIPHY log------TX frequency eventLCPLL lockLCPLL lost lockLCPLL lockLCPLL lost lockLCPLL lockTX frequency eventTX timer eventTX GPO Rising Edge DetectedTX MMCM reconfig doneGT TX reconfig doneTX MMCM lock

RX Only Sample HDMI GT Controller Log

The following log entry was taken from a HDMI GT Controller using the RPLL to clock the RX.

HDMIPHY log------RX frequency eventRX timer eventRX DRU disableRX GPO Rising Edge DetectedGT RX reconfig doneRPLL lost lockRX reset doneRPLL lockRX reset doneRX MMCM reconfig doneRX MMCM lock

Passthrough Sample HDMI GT Controller Log

The following log entry is from a HDMI GT Controller using LCPLL and RPLL to clock the TX andRX respectively.

HDMIPHY log------RX frequency eventRX frequency eventRX timer eventRX DRU disableRX GPO Rising Edge DetectedGT RX reconfig doneRPLL lost lockRX reset doneRPLL lockRX reset doneRX MMCM reconfig doneRX MMCM lockTX frequency event





LCPLL lost lockLCPLL lockLCPLL lost lockLCPLL lockLCPLL lost lockLCPLL lockTX frequency eventTX timer eventTX GPO Rising Edge DetectedTX MMCM reconfig doneGT TX reconfig doneLCPLL lost lockTX reset doneTX MMCM lockLCPLL lockRPLL lockTX reset done





Appendix D

Application Software DevelopmentFor HDMI application software development, refer to the Application Software Developmentsection of the HDMI 1.4/2.0 Transmitter Subsystem Product Guide (PG235) and the HDMI 1.4/2.0Receiver Subsystem Product Guide (PG236).

Appendix D: Application Software Development






Appendix E

Additional Resources and LegalNotices

Xilinx ResourcesFor support resources such as Answers, Documentation, Downloads, and Forums, see XilinxSupport.

Documentation Navigator and Design HubsXilinx® Documentation Navigator (DocNav) provides access to Xilinx documents, videos, andsupport resources, which you can filter and search to find information. To open DocNav:

• From the Vivado® IDE, select Help → Documentation and Tutorials.

• On Windows, select Start → All Programs → Xilinx Design Tools → DocNav.

• At the Linux command prompt, enter docnav.

Xilinx Design Hubs provide links to documentation organized by design tasks and other topics,which you can use to learn key concepts and address frequently asked questions. To access theDesign Hubs:

• In DocNav, click the Design Hubs View tab.

• On the Xilinx website, see the Design Hubs page.

Note: For more information on DocNav, see the Documentation Navigator page on the Xilinx website.

ReferencesThese documents provide supplemental material useful with this guide:

Appendix E: Additional Resources and Legal Notices




https://www.xilinx.com/cgi-bin/docs/ndoc?t=design+hubs

https://www.xilinx.com/cgi-bin/docs/rdoc?t=docnav



1. Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994)

2. Vivado Design Suite User Guide: Designing with IP (UG896)

3. Vivado Design Suite User Guide: Getting Started (UG910)

4. Vivado Design Suite User Guide: Logic Simulation (UG900)

5. Vivado Design Suite User Guide: Programming and Debugging (UG908)

6. Vivado Design Suite User Guide: Implementation (UG904)

7. HDMI 1.4/2.0 Transmitter Subsystem Product Guide (PG235)

8. HDMI 1.4/2.0 Receiver Subsystem Product Guide (PG236)

9. Versal ACAP GTY and GTYP Transceivers Architecture Manual (AM002)

10. Versal ACAP Clocking Resources Architecture Manual (AM003)

11. Versal Prime Series Data Sheet: DC and AC Switching Characteristics (DS956)

12. Versal AI Core Series Data Sheet: DC and AC Switching Characteristics (DS957)

13. Versal AI Edge Series Data Sheet: DC and AC Switching Characteristics (DS958)

Revision HistoryThe following table shows the revision history for this document.

Section Revision Summary03/05/2021 Version 1.0

Initial Xilinx release. N/A

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action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinxhad been advised of the possibility of the same. Xilinx assumes no obligation to correct anyerrors contained in the Materials or to notify you of updates to the Materials or to productspecifications. You may not reproduce, modify, distribute, or publicly display the Materialswithout prior written consent. Certain products are subject to the terms and conditions ofXilinx's limited warranty, please refer to Xilinx's Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms containedin a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe orfor use in any application requiring fail-safe performance; you assume sole risk and liability foruse of Xilinx products in such critical applications, please refer to Xilinx's Terms of Sale which canbe viewed at https://www.xilinx.com/legal.htm#tos.

AUTOMOTIVE APPLICATIONS DISCLAIMER

AUTOMOTIVE PRODUCTS (IDENTIFIED AS "XA" IN THE PART NUMBER) ARE NOTWARRANTED FOR USE IN THE DEPLOYMENT OF AIRBAGS OR FOR USE IN APPLICATIONSTHAT AFFECT CONTROL OF A VEHICLE ("SAFETY APPLICATION") UNLESS THERE IS ASAFETY CONCEPT OR REDUNDANCY FEATURE CONSISTENT WITH THE ISO 26262AUTOMOTIVE SAFETY STANDARD ("SAFETY DESIGN"). CUSTOMER SHALL, PRIOR TO USINGOR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE PRODUCTS, THOROUGHLY TESTSUCH SYSTEMS FOR SAFETY PURPOSES. USE OF PRODUCTS IN A SAFETY APPLICATIONWITHOUT A SAFETY DESIGN IS FULLY AT THE RISK OF CUSTOMER, SUBJECT ONLY TOAPPLICABLE LAWS AND REGULATIONS GOVERNING LIMITATIONS ON PRODUCTLIABILITY.

Copyright

© Copyright 2021 Xilinx, Inc. Xilinx, the Xilinx logo, Alveo, Artix, Kintex, Spartan, Versal, Virtex,Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the UnitedStates and other countries. AMBA, AMBA Designer, Arm, ARM1176JZ-S, CoreSight, Cortex,PrimeCell, Mali, and MPCore are trademarks of Arm Limited in the EU and other countries.HDMI, HDMI logo, and High-Definition Multimedia Interface are trademarks of HDMI LicensingLLC. All other trademarks are the property of their respective owners.



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