UNIT- III

INTERFACING WITH 8051

Input Output interfacing:

The I/O (Input/Output) is the third component of a microprocessor-based system. I/O devices, such as keyboards and displays, are the ears and eyes of the MPUs; they are the communication channels to the "outside world." Data can enter or exit in groups of eight bits using the entire data bus; this is called the parallel I/O mode. The other mode is the serial I/O, whereby one bit is transferred using one data line; typical examples include peripherals such as CRT terminals or cassette tapes. In this chapter, we focus on interfacing I/O devices in the parallel mode; the serial mode will be discussed in the topic.

In the parallel I/O mode, devices can be interfaced using two techniques: peripheral mapped I/O and memory-mapped I/O. In peripheral-mapped I/O, a device is identified with an 8-bit address and enabled by I/O-related control signals. In memory-mapped I/O, a device is identified with a 16-bit address and enabled by memory-related control signals. The process of data transfer in both is identical. Each device is assigned a binary address through its interfacing circuit. When the Z80 is programmed to transfer data, it places the appropriate address on the address bus,

Sends the control signals, enables the interfacing device, and transfers data. The interfacing device is like a gate for data bits, which is opened by the MPU whenever it intends to transfer data.

The basic concepts of peripheral-mapped and memory mapped I/O from the machine cycles. The peripheral-mapped I/O concepts are illustrated with two examples: interfacing LEDs as an output device and switches as an input device. The memory-mapped I/O technique is illustrated with an example of appliance control. The chapter also includes additional interfacing examples that occur frequently in microprocessor based products.

Interfacing Output Devices:

In peripheral-mapped I/O, a device is identified with an 8-bit address, and I/O related control signals are used to enable the device. The process of data transfer is in many ways similar to that of reading from or writing into a memory register. The Z80 uses the instruction IN to read (input) data from an input device and uses the instruction OUT to write (send) data to an output device. To understand interfacing of I/O devices, we need to examine the execution and machine cycles. Of these input/output instructions. In the next section, we will examine the execution of the OUT instruction and discuss the interfacing of output devices, and in Section 5.3, we will examine the IN instruction and discuss the interfacing of input devices.

The OUT instruction has three machine cycles: Opcode Fetch, Memory Read, and I/O Write. The Z80 reads the opcode and the port address from memory in the first two machine cycles and writes into the port in the third cycle. Figure 5.1 shows the timing of the OUT instruction with the port address 07H•

The first two machine cycles-Opcode Fetch and Memory Read-are similar to the machine cycles shown in Figure 3.5; however, in Figure 5.1, the low order and high-order address buses are shown separately to illustrate the contents of the low-order bus in the third cycle. In the Opcode Fetch cycle, the Z80 places the address 2050H on the address bus and fetches the opcode D3H (1 1 0 I 00 1 1) via the data bus. When the Z80 decodes the opcode, it realizes that the instruction consists of two bytes, and that it must read the second byte. In the second machine cycle, the Z80 places the next address, 2051H, on the address bus and reads the port address 07H•

In the third machine ‘cycle, M3 (I/O Write), the following events occur:

1. The Z80 places the port address 07 H on the low-order address bus and the contents of the accumulator on the data bus.

 

2. During T2, it asserts the I ͞͞O ͞R ͞Q͞ and ͞͞͞͞W͞͞R ͞ control signals; the assertion of I ͞͞O͞R ͞Q ͞ indicates that it is an I/O operation.

3. The Z80 automatically inserts a single Wait state Tw after T2 to allow sufficient response time for an I/O device; this Wait state is added regardless of the WAIT signal status.

4. During T3, the control signals I ͞͞O͞R ͞Q ͞ and W͞͞R ͞ become inactive.

To interface an output device, the information on the buses during the M3 cycle is critical. From the beginning of T2 until the end of T3, we have the port address (07H) on the low-order address bus and the data byte to be displayed on the data bus. The availability of this information is indicated by the control signals. Now what we must do is to latch (catch) this information using the control signals before it disappears from the buses; we need to open the gate at that precise moment to let the data flow to the "outside world." This is the essence of interfacing.

Bus standards:

The PCI (peripheral component interconnect) bus is virtually the only bus found in the newest Pentium 4 systems and just about all the Pentium systems. In all of the newer systems, the ISA bus still exists by special order, but as an interface for older 8-bit and 16-bit interface cards.

Many new systems contain only two ISA bus slots or no ISA slots. In time, the ISA bus may dis- appear, but it is still an important interface for many industrial applications. The PCI bus has replaced the VESA local bus. One reason is that the PCI bus has plug-and-play characteristics and the ability to function with a 64-bit data bus. A PCI interface contains a series of registers, located in a small memory device on the PCI interface, that contain information about the board. This same memory can provide plug-and-play characteristics to the ISA bus or any other bus. The information in these registers allows the computer to automatically configure the PCI card. This feature, called plug-and-play (PnP), is probably the main reason that the PCI bus has become so popular in the most systems.

Figure 15–6 shows the system structure for the PCI bus in a personal computer system. Notice that the microprocessor bus is separate and independent of the PCI bus. The microprocessor

connects to the PCI bus through an integrated circuit called a PCI bridge. This means that virtually any microprocessor can be interfaced to the PCI bus, as long as a PCI controller or bridge is designed for the system. In the future, all computer systems may use the same bus. Even the Apple Macintosh system is switching to the PCI bus. The resident local bus is often called a front side bus.

The PCI Bus Pin-Out

As with the other buses described in this chapter, the PCI bus contains all of the system control signals. Unlike the other buses, the PCI bus functions with either a 32-bit or a 64-bit data bus and a full 32-bit address bus. Another difference is that the address and data buses are multiplexed to reduce the size of the edge connector. These multiplexed pins are labeled AD0–AD63 on the connector. The 32-bit card (which is found in most computers) has only connections 1 through 62, while the 64-bit card has all 94 connections. The 64-bit card can accommodate a 64-bit address if it is required at some point in the future. Figure 15–7 on the next page illustrates the PCI bus pin-out.

As with the other bus systems, the PCI bus is most often used for interfacing I/O components to the microprocessor. Memory could be interfaced, but it would operate only at a 33 MHz rate with the Pentium, which is half the speed of the 66 MHz resident local bus of the Pentium system. A more recent version of PCI (2.1-compliant) operates at 66 MHz and at 33 MHz for

older interface cards. Pentium 4 systems use a 200 MHz system bus speed (although it is often listed as 800 MHz), but there is no planned modification to the PCI bus speed yet.

The PCI Address/Data Connections

The PCI address appears on AD0–AD31 and it is multiplexed with data. In some systems, there is a 64-bit data bus that uses AD32–AD63 for data transfer only. In the future, these pins can be used for extending the address to 64 bits. Figure 15–8 illustrates the timing diagram for the PCI bus, which shows the way that the address is multiplexed with data and also the control signals used for multiplexing.

During the first clocking period, the address of the memory or I/O location appears on the AD connections, and the command to a PCI peripheral appears on the C>BE pins. Table 15–4 illustrates the bus commands found on the PCI bus.

INTA Sequence During the interrupt acknowledge sequence, an interrupt controller (the controller that caused the interrupt) is addressed and interrogated for the interrupt vector. The byte-sized interrupt vector is returned during a byte read operation.

Special Cycle The special cycle is used to transfer data to all PCI components.

During this cycle, the rightmost 16 bits of the data bus contain a 0000H, indicating a processor shutdown, 0001H for a processor halt, or 0002H for 80X86 specific code or data.

I/O Read Cycle Data are read from an I/O device using the I/O address that appears on AD0–AD15. Burst reads are not supported for I/O devices.

I/O Write Cycle As with I/O read, this cycle accesses an I/O device, but writes data.

FIGURE 15–8 The basic burst mode timing for the PCI bus system. Note that this transfers either four 32-bit numbers (32-bit PCI) or four 64-bit numbers (64-bit PCI).

Memory Read Cycle Data are read from a memory device located on the PCI bus.

Memory Write Cycle As with memory read, data are accessed in a device located on the PCI bus. The location is written.

Configuration Read Configuration information is read from the PCI device using the

configuration read cycle.

Configuration Write The configuration write allows data to be written to the configuration area in a PCI device. Note that the address is specified by the configuration read.

Memory Multiple This is similar to the memory read access, except that it is usually

Access used to access many data instead of one.

Dual Addressing Used for transferring address information to a 64-bit PCI device, Cycle which only contains a 32-bit data path.

Line Memory Used to read more than two 32-bit numbers from the PCI bus.

Addressing

Memory Write with This is the same as line memory access, but it is used with a write.

Invalidation This write bypasses the write-back function of the cache.

Configuration Space

The PCI interface contains a 256-byte configuration memory that allows the computer to interrogate the PCI interface. This feature allows the system to automatically configure itself for the PCI plug-board. Microsoft Corporation calls this plug-and-play (PnP). Figure 15–9 illustrates the configuration memory and its contents.

The first 64 bytes of the configuration memory contain the header that holds information about the PCI interface. The first 32-bit doubleword contains the unit ID code and the vendor ID code. The unit ID code is a 16-bit number (D31–D16) that is an FFFFH if the unit is not installed, and a number between 0000H and FFFEH that identifies the unit if it is installed. The class codes identify the class of the PCI interface. The class code is found in bits D31–D16 of configuration memory at location 08H. Note that bits D15–D0 are defined by the manufacturer. The current

class codes are listed in Table 15–5 and are assigned by the PCI SIG, which is the governing body for the PCI bus interface standard. The vendor ID (D15–D0) is also allocated by the PCI SIG.

The status word is loaded in bits D31–D16 of configuration memory location 04H and the command is at bits D15–D0 of location 04H. Figure 15–10 illustrates the format of both the status and command registers.

The base address space consists of a base address for the memory, a second for the I/O space, and a third for the expansion ROM. The first two doublewords of the base address space contain either the 32- or 64-bit base address for the memory present on the PCI interface. The next doubleword contains the base address of the I/O space. Note that even though the Intel microprocessors only use a 16-bit I/O address, there is room for expanding the I/O address to 32 bits. This allows systems that use the 680X0 family and PowerPC access to the PCI bus because they do have I/O space that is accessed via a 32-bit address. The 600X0 and PowerPC use memory-mapped I/O, discussed at the beginning of Chapter 11.

BIOS for PCI

Most modem personal computers contain the PCI bus and an extension to the normal system BIOS that supports the PCI bus. These newer systems contain access to the PCI bus at interrupt vector 1AH. Table 15–6 lists the functions currently available through the DOS INT 1AH instruction with AH = 0B1H for the PCI bus.

Example 15–5 shows how the BIOS is used to determine whether the PCI bus extension available. Once the presence of the BIOS is established, the contents of the configuration memory can be read using the BIOS functions. Note that the BIOS does not support data transfers between the computer and the PCI interface. Data transfers are handled by drivers that are pro- vided with the interface. These drivers control the flow of data between the microprocessor and the component found on the PCI interface.

PCl Interface

The PCI interface is complex, and normally an integrated PCI bus controller is used for interfacing to the PCI bus. It requires memory (EPROM) to store vendor information and other information, as explained earlier in this section of the chapter. The basic structure of the PCI interface is illustrated in Figure 15–11. The contents of this block diagram illustrate the required components for a functioning PCI interface; it does not illustrate the interface itself. The Registers, Parity Block, Initiator, Target, and Vendor ID EPROM are required components of any PCI interface. If a PCI interface is constructed, a PCI controller is often used because of the complexity of this interface. The PCI con- troller provides the structures shown in Figure 15–11.

Timing and Control:

As you already know, the microcontroller oscillator uses quartz crystal for its operation. As the frequency of this oscillator is precisely defined and very stable, pulses it generates are always of the same width, which makes them ideal for time measurement. Such crystals are also used in quartz watches. In order to measure time between two events it is sufficient to count up pulses coming from this oscillator. That is exactly what the timer does. If the timer is properly programmed, the value stored in its register will be incremented (or decremented) with each coming pulse, i.e. once per each machine cycle. A single machine-cycle instruction lasts for 12 quartz oscillator periods, which means that by embedding quartz with oscillator frequency of 12MHz, a number stored in the timer register will be changed million times per second, i.e. each microsecond.

The 8051 microcontroller has 2 timers/counters called T0 and T1. As their names suggest, their main purpose is to measure time and count external events. Besides, they can be used for generating clock pulses to be used in serial communication, so called Baud Rate.

Timer T0

As seen in figure below, the timer T0 consists of two registers – TH0 and TL0 representing a low and a high byte of one 16-digit binary number.

Accordingly, if the content of the timer T0 is equal to 0 (T0=0) then both registers it consists of will contain 0. If the timer contains for example number 1000 (decimal), then the TH0 register (high byte) will contain the number 3, while the TL0 register (low byte) will contain decimal number 232.

Formula used to calculate values in these two registers is very simple:TH0 × 256 + TL0 = TMatching the previous example it would be as follows:3 × 256 + 232 = 1000

Since the timer T0 is virtually 16-bit register, the largest value it can store is 65 535. In case of exceeding this value, the timer will be automatically cleared and counting starts from 0. This

condition is called an overflow. Two registers TMOD and TCON are closely connected to this timer and control its operation.

TMOD Register (Timer Mode)

The TMOD register selects the operational mode of the timers T0 and T1. As seen in figure below, the low 4 bits (bit0 - bit3) refer to the timer 0, while the high 4 bits (bit4 - bit7) refer to the timer 1. There are 4 operational modes and each of them is described herein.

Bits of this register have the following function:

GATE1 enables and disables Timer 1 by means of a signal brought to the INT1 pin (P3.3):

o 1 - Timer 1 operates only if the INT1 bit is set.o 0 - Timer 1 operates regardless of the logic state of the INT1 bit.

C/T1 selects pulses to be counted up by the timer/counter 1: o 1 - Timer counts pulses brought to the T1 pin (P3.5).o 0 - Timer counts pulses from internal oscillator.

T1M1,T1M0 These two bits select the operational mode of the Timer 1.

T1M1 T1M0 Mode Description

0 0 0 13-bit timer

0 1 1 16-bit timer

1 0 2 8-bit auto-reload

1 1 3 Split mode

GATE0 enables and disables Timer 1 using a signal brought to the INT0 pin (P3.2): o 1 - Timer 0 operates only if the INT0 bit is set.o 0 - Timer 0 operates regardless of the logic state of the INT0 bit.

C/T0 selects pulses to be counted up by the timer/counter 0: o 1 - Timer counts pulses brought to the T0 pin (P3.4).o 0 - Timer counts pulses from internal oscillator.

T0M1,T0M0 These two bits select the oprtaional mode of the Timer 0.

T0M1 T0M0 Mode Description

0 0 0 13-bit timer

0 1 1 16-bit timer

1 0 2 8-bit auto-reload

1 1 3 Split mode

Timer 0 in mode 0 (13-bit timer)

This is one of the rarities being kept only for the purpose of compatibility with the previuos versions of microcontrollers. This mode configures timer 0 as a 13-bit timer which consists of all 8 bits of TH0 and the lower 5 bits of TL0. As a result, the Timer 0 uses only 13 of 16 bits. How does it operate? Each coming pulse causes the lower register bits to change their states. After receiving 32 pulses, this register is loaded and automatically cleared, while the higher byte (TH0) is incremented by 1. This process is repeated until registers count up 8192 pulses. After that, both registers are cleared and counting starts from 0.

Timer 0 in mode 1 (16-bit timer)

Mode 1 configures timer 0 as a 16-bit timer comprising all the bits of both registers TH0 and TL0. That's why this is one of the most commonly used modes. Timer operates in the same way as in mode 0, with difference that the registers count up to 65 536 as allowable by the 16 bits.

Timer 0 in mode 2 (Auto-Reload Timer)

Mode 2 configures timer 0 as an 8-bit timer. Actually, timer 0 uses only one 8-bit register for counting and never counts from 0, but from an arbitrary value (0-255) stored in another (TH0) register.

The following example shows the advantages of this mode. Suppose it is necessary to constantly count up 55 pulses generated by the clock.

If mode 1 or mode 0 is used, It is necessary to write the number 200 to the timer registers and constantly check whether an overflow has occured, i.e. whether they reached the value 255. When it happens, it is necessary to rewrite the number 200 and repeat the whole procedure. The same procedure is automatically performed by the microcontroller if set in mode 2. In fact, only the TL0 register operates as a timer, while another (TH0) register stores the value from which the counting starts. When the TL0 register is loaded, instead of being cleared, the contents of TH0 will be reloaded to it. Referring to the previous example, in order to register each 55th pulse, the

best solution is to write the number 200 to the TH0 register and configure the timer to operate in mode 2.

Timer 0 in Mode 3 (Split Timer)

Mode 3 configures timer 0 so that registers TL0 and TH0 operate as separate 8-bit timers. In other words, the 16-bit timer consisting of two registers TH0 and TL0 is split into two independent 8-bit timers. This mode is provided for applications requiring an additional 8-bit timer or counter. The TL0 timer turns into timer 0, while the TH0 timer turns into timer 1. In addition, all the control bits of 16-bit Timer 1 (consisting of the TH1 and TL1 register), now control the 8-bit Timer 1. Even though the 16-bit Timer 1 can still be configured to operate in any of modes (mode 1, 2 or 3), it is no longer possible to disable it as there is no control bit to do it. Thus, its operation is restricted when timer 0 is in mode 3.

The only application of this mode is when two timers are used and the 16-bit Timer 1 the operation of which is out of control is used as a baud rate generator.

Timer Control (TCON) Register

TCON register is also one of the registers whose bits are directly in control of timer operation.Only 4 bits of this register are used for this purpose, while rest of them is used for interrupt control to be discussed later.

TF1 bit is automatically set on the Timer 1 overflow. TR1 bit enables the Timer 1.

o 1 - Timer 1 is enabled.

o 0 - Timer 1 is disabled. TF0 bit is automatically set on the Timer 0 overflow. TR0 bit enables the timer 0.

o 1 - Timer 0 is enabled.o 0 - Timer 0 is disabled.

How to use the Timer 0 ?

In order to use timer 0, it is first necessary to select it and configure the mode of its operation. Bits of the TMOD register are in control of it:

Referring to figure above, the timer 0 operates in mode 1 and counts pulses generated by internal clock the frequency of which is equal to 1/12 the quartz frequency.Turn on the timer:

The TR0 bit is set and the timer starts operation. If the quartz crystal with frequency of 12MHz is embedded then its contents will be incremented every microsecond. After 65.536 microseconds, the both registers the timer consists of will be loaded. The microcontroller automatically clears them and the timer keeps on repeating procedure from the beginning until the TR0 bit value is logic zero (0).

How to 'read' a timer?

Depending on application, it is necessary either to read a number stored in the timer registers or to register the moment they have been cleared.

- It is extremely simple to read a timer by using only one register configured in mode 2 or 3. It is sufficient to read its state at any moment. That's all!

- It is somehow complicated to read a timer configured to operate in mode 2. Suppose the lower byte is read first (TL0), then the higher byte (TH0). The result is:

TH0 = 15 TL0 = 255

Everything seems to be ok, but the current state of the register at the moment of reading was:

TH0 = 14 TL0 = 255

In case of negligence, such an error in counting (255 pulses) may occur for not so obvious but quite logical reason. The lower byte is correctly read (255), but at the moment the program counter was about to read the higher byte TH0, an overflow occurred and the contents of both registers have been changed (TH0: 14→15, TL0: 255→0). This problem has a simple solution. The higher byte should be read first, then the lower byte and once again the higher byte. If the

number stored in the higher byte is different then this sequence should be repeated. It's about a short loop consisting of only 3 instructions in the program.

There is another solution as well. It is sufficient to simply turn the timer off while reading is going on (the TR0 bit of the TCON register should be cleared), and turn it on again after reading is finished.

Timer 0 Overflow Detection

Usually, there is no need to constantly read timer registers. It is sufficient to register the moment they are cleared, i.e. when counting starts from 0. This condition is called an overflow. When it occurrs, the TF0 bit of the TCON register will be automatically set. The state of this bit can be constantly checked from within the program or by enabling an interrupt which will stop the main program execution when this bit is set. Suppose it is necessary to provide a program delay of 0.05 seconds (50 000 machine cycles), i.e. time when the program seems to be stopped:

First a number to be written to the timer registers should be calculated:

Then it should be written to the timer registers TH0 and TL0:

When enabled, the timer will resume counting from this number. The state of the TF0 bit, i.e. whether it is set, is checked from within the program. It happens at the moment of overflow, i.e. after exactly 50.000 machine cycles or 0.05 seconds.

How to measure pulse duration?

Suppose it is necessary to measure the duration of an operation, for example how long a device has been turned on? Look again at the figure illustrating the timer and pay attention to the function of the GATE0 bit of the TMOD register. If it is cleared then the state of the P3.2 pin doesn't affect timer operation. If GATE0 = 1 the timer will operate until the pin P3.2 is cleared. Accordingly, if this pin is supplied with 5V through some external switch at the moment the device is being turned on, the timer will measure duration of its operation, which actually was the objective.

How to count up pulses?

Similarly to the previous example, the answer to this question again lies in the TCON register. This time it's about the C/T0 bit. If the bit is cleared the timer counts pulses generated by the internal oscillator, i.e. measures the time passed. If the bit is set, the timer input is provided with pulses from the P3.4 pin (T0). Since these pulses are not always of the same width, the timer cannot be used for time measurement and is turned into a counter, therefore. The highest frequency that could be measured by such a counter is 1/24 frequency of used quartz-crystal.

Timer 1

Timer 1 is identical to timer 0, except for mode 3 which is a hold-count mode. It means that they have the same function, their operation is controlled by the same registers TMOD and TCON and both of them can operate in one out of 4 different modes.

2.7 UART (Universal Asynchronous Receiver and Transmitter)

One of the microcontroller features making it so powerful is an integrated UART, better known as a serial port. It is a full-duplex port, thus being able to transmit and receive data simultaneously and at different baud rates. Without it, serial data send and receive would be an enormously complicated part of the program in which the pin state is constantly changed and checked at regular intervals. When using UART, all the programmer has to do is to simply select serial port mode and baud rate. When it's done, serial data transmit is nothing but writing to the SBUF register, while data receive represents reading the same register. The microcontroller takes care of not making any error during data transmission.

Serial port must be configured prior to being used. In other words, it is necessary to determine how many bits is contained in one serial “word”, baud rate and synchronization clock source. The whole process is in control of the bits of the SCON register (Serial Control).

Serial Port Control (SCON) Register

SM0 - Serial port mode bit 0 is used for serial port mode selection. SM1 - Serial port mode bit 1. SM2 - Serial port mode 2 bit, also known as multiprocessor communication enable bit.

When set, it enables multiprocessor communication in mode 2 and 3, and eventually mode 1. It should be cleared in mode 0.

REN - Reception Enable bit enables serial reception when set. When cleared, serial reception is disabled.

TB8 - Transmitter bit 8. Since all registers are 8-bit wide, this bit solves the problem of transmiting the 9th bit in modes 2 and 3. It is set to transmit a logic 1 in the 9th bit.

RB8 - Receiver bit 8 or the 9th bit received in modes 2 and 3. Cleared by hardware if 9th bit received is a logic 0. Set by hardware if 9th bit received is a logic 1.

TI - Transmit Interrupt flag is automatically set at the moment the last bit of one byte is sent. It's a signal to the processor that the line is available for a new byte transmite. It must be cleared from within the software.

RI - Receive Interrupt flag is automatically set upon one byte receive. It signals that byte is received and should be read quickly prior to being replaced by a new data. This bit is also cleared from within the software.

  Input and Output Devices: Input/Output devices are the means through which the MPU communicates with "the outside world." The MPU accepts binary data as input from devices such as keyboards and analog-to-digital (A/D) converters and sends data to output devices such as LEDs or printers. There are two different methods b which an MPU can identify I/O devices :one uses an 8-bit address and the other a 16- bit address These methods are described briefly in the following sections.

I/Os with 8-Bit Addresses (Peripheral-Mapped I/O)In this type of I/O, the MPU uses eight address lines to identify an input or an output device; this is also known as peripheral-mapped I/O .The eight address lines can have 256 (28 combinations) a dresses ;thus the MPU can identify 256 input devices and 256 output devices with addresses ranging from 00H to FFH· The input and output devices are differentiated by the control signals I/O Read for input devices and I/O Write for output devices. The entire range of I/O ad-dresses from 00H to FFH is also known as an I/O map. and individual addresses are also referred to as I/O device addresses or I/O port numbers.

If we use LEDs as output or switches as input. we need to resolve two issues: how to assign addresses and how to connect these I/O devices to the data bus . In a bus architecture ,these devices cannot be connected directly to the data bus or the address bus; all connections must be made through tri-stale interfacing devices so they will be enabled and connected to the buses only when the MPU chooses to communicate with them .In the case of memory . we did not have to be concerned with these problems because of the internal address decoding, Read/Write buffers .and availability of CS’ and control signals of the memory chip .In the case of I/O devices, we need to use external interfacing devices.

The steps in communicating with an I/O device are similar to those in com-municating with memory and can be summarized as follows:

1. The MPU places an 8-bit address on the address bus, which is decoded by the external decode logic

2. The MPU sends a control signal (I/O Read or I/O Write) to enable the I/O

device.

3. Data are transferred on the data bus.

I/Os with I6-bit Addresses (Memory-Mapped I/O)

In this type of I/O. the MPU uses 16 address lines to identify an I/O device; an I/O is connected as if it is a memory register. In memory-mapped I/O, the MPU uses the same control signals (Memory Read or Memory Write)and instructions as those of memory and follows the same steps as when it is accessing a memory. register. In some microprocessors. such as the Motorola 6800, all I/Os have 16- bit addresses so that I/Os and memory share the same memory map (64K) .

The peripheral- and memory-mapped I/O techniques will be discussed in detail in the context of interfacing I/O devices  .

Serial and Parallel Communication:

 

All communication we have dealt with up to now has been parallel. Data being transferred between one location and another (R0 to the accumulator, for example) travel along the 8-bit data bus. Because of this data bus, data bytes can be moved about the microcontroller at high speed.

 However, parallel communication has the disadvantage of requiring at least eight separate lines (in an 8-bit system) and in most cases extra lines to synchronize the data transfer (in the case of the microcontroller, the control bus).

 

Serial communication has the advantage of requiring only one line for the data, a second line for ground and possibly a third line for the clock. Therefore, because serial communication requires less physical wires, it is more suitable for transmitting data over longer distances.

 

The obvious disadvantage of serial communication, compared with parallel, is the reduction in the data transfer rate. If we imagine a system where it takes 1us for data to settle on the data bus, we could say it takes 1us to transfer a data byte using parallel communication. If we imagine the same timeframe for data bits settling on the serial line, it would take 8us to transfer a data byte using serial communication (1us for each bit).

     Synchronous Serial Communication

 

Synchronous serial communication requires an extra line for the clock signal. For serial communication, the 8-bit parallel data byte must be shifted down the serial line (in transmission). Therefore, one bit is followed by another. Some kind of system must be used to determine how long each bit is on the line. For example, the serial system designer may decide each bit will be on the line for 1us and, as explained above, transmission of the full eight bits would take 8us.

  With synchronous communication, the clock signal is transmitted on a separate line, as shown in the diagram below.

   

 

   

  In this way, the receiver is synchronized with the transmitter. As we shall see, the 8051 serial port in mode 0 is an example of synchronous serial communication.

        Asynchronous Serial Communication

 

A good example of asynchronous serial communication is the interface between a keyboard and a computer. In this case, the keyboard is the transmitter and the computer is the receiver. With asynchronous communication, a clock signal is not sent with the data. There are a number of reasons why this form of communication might be desirable over synchronous communication. One advantage is the fact that the physical line for the clock is not needed. Also, asynchronous communication is better over long distances. If we try to synchronize a remote receiver by sending the clock signal, due to propagation delays and interference, the validity of the clock is lost.

 

Another reason for not transmitting the clock arises when the data rate is erratic. For example, data rate from a keyboard to a computer is dependent upon the typist. The user may type at a rate of sixty words per minute, but at other times he/she may type a lot less. And for long periods there may be no data sent at all. Because of this erratic data rate an asynchronous communication system is suitable.

     Serial Communication Protocol

 

In any communication system, the receiver must know what kind of data to expect and at what rate the data will arrive. In both synchronous and asynchronous serial communication, the receiver needs to know with which bit the transmitter begins. In most systems the LSB is the first bit transmitted.

 For an asynchronous system, the number of bits transmitted per second must be known by the receiver. Since the clock signal is not transmitted, the receiver needs to know what clock frequency the transmitter is using so that it can use the same.

 The receiver also needs to know how many bits per word the transmitter is using (in most cases we deal with 8-bit words, but we will see cases where nine bits are transmitted per word).

  And the receiver needs to know where the data begins and where the data stops.

 

All these parameters make up the protocol. If the receiver uses the same protocol as the transmitter is should receive the data correctly (although errors can occur and we will look at how we catch these errors at a later date). If the receiver uses a protocol other than the one used by the transmitter, then the two devices are effectively speaking two different languages and the data received will be garbage.

     Start Bits and Stop Bits

 In asynchronous communication, at least two extra bits are transmitted with the data word; a start bit and a stop bit. Therefore, if the transmitter is using an 8-bit system, the actual number of bits transmitted per word is ten.

  In most protocols the start bit is a logic 0 while the stop bit is logic 1.  Therefore, when no data is being sent the data line is continuously HIGH.

 The receiver waits for a 1 to 0 transition. In other words, it awaits a transition from the stop bit (no data) to the start bit (logic 0). Once this transition occurs the receiver knows a data byte will follow.

 

Since it knows the data rate (because it is defined in the protocol) it uses the same clock as frequency as that used by the transmitter and reads the correct number of bits and stores them in a register. For example, if the protocol determines the word size as eight bits, once the receiver sees a start bit it reads the next eight bits and places them in a buffer.

 Once the data word has been read the receiver checks to see if the next bit is a stop bit, signifying the end of the data. If the next bit is not a logic 1 then something went wrong with the transmission and the receiver dumps the data.

  If the stop bit was received the receiver waits for the next data word, ie; it waits for a 1 to 0 transition.

        The 8051 Serial Port

 

The 8051 includes an on-chip serial port that can be programmed to operate in one of four different modes and at a range of frequencies. In serial communication the data is rate is known as the baud rate, which simply means the number of bits transmitted per second. In the serial port modes that allow variable baud rates, this baud rate is set by timer 1.

   

 

(The 8051 Microcontroller, 3rd Edition - I. Scott MacKenzie)      

 

The 8051 serial port is full duplex. In other words, it can transmit and receive data at the same time. The block diagram above shows how this is achieved. If you look at the memory map you will notice at location 99H the serial buffer special function register (SBUF). Unlike any other register in the 8051, SBUF is in fact two distinct registers - the write-only register and the read-only register. Transmitted data is sent out from the write-only register while received data is stored in the read-only register. There are two separate data lines, one for transmission (TXD) and one for reception (RXD). Therefore, the serial port can be transmitting data down the TXD line while it is at the same time receiving data on the RXD line.

 

The TXD line is pin 11 of the microcontroller (P3.1) while the RXD line is on pin 10 (P3.0). Therefore, external access to the serial port is achieved by connecting to these pins. For example, if you wanted to connect a keyboard to the serial port you would connect the transmit line of the keyboard to pin 10 of the 8051. If you wanted to connect a display to the serial port you would connect the receive line of the display to pin 11 of the 8051. This is detailed in the diagram below.

   

 

     Transmitting and Receiving Data

 Essentially, the job of the serial port is to change parallel data into serial data for transmission and to change received serial data into parallel data for use within the microcontroller.

 

Serial transmission is changing parallel data to serial data. Serial reception is changing serial data into parallel data. Both are achieved through the use of shift registers.

 

As discussed earlier, synchronous communication requires the clock signal to be sent along with the data while asynchronous communication requires the use of stop bits and start bits. However, the programmer wishing to use the 8051 need not worry about such things. To transmit data along the serial line you simply write to the serial buffer and to access data received on the serial port you simply read data from the serial buffer.

  For example:

 

MOV SBUF, #45H - this sends the byte 45H down the serial line MOV A, SBUF - this takes whatever data was received by the serial port and

puts it in the accumulator.

 

As mentioned earlier, it takes a certain length of time for a data byte to be transmitted down the serial line (determined by the baud rate). If we send data to SBUF and then immediately send more data to SBUF, as shown below, the initial character will be overwritten before it was completely shifted down the line.

  MOV SBUF, #23H MOV SBUF, #56H

  Therefore, we must wait for the entire byte to be sent before we send another. The serial port control register (SCON) contains a bit which alerts us to the fact that a byte has been transmitted; ie; the transmit interrupt flag (TI) is set by hardware once an entire

byte has been transmitted down the line. Since SCON is bit-addressable we can test this bit and wait until it is set, as shown below:

   

 

MOV SBUF, #23H; send the first byte down the serial lineJNB TI, $; wait for the entire byte to be sentCLR TI; the transmit interrupt flag is set by hardware but must be cleared by softwareMOV SBUF, #56H; send the second byte down the serial line

        How do we know when data has been received?

 

Similarly, we need to know when an entire byte has been received by the serial port. Another bit in SCON, the receive interrupt flag (RI) is set by hardware when an entire byte is received by the serial port. The code below shows how you would program the controller to wait for data to be received and to then move that data into the accumulator.

   

 JNB RI, $; wait for an entire byte to be receivedCLR RI; the receive interrupt flag is set by hardware but must be cleared by softwareMOV A, SBUF; move the data stored in the read-only buffer to the accumulator

        Why is there an extra register on the receive side?

 If you look at the block diagram of the serial port above you will notice the RXD line is applied to a shift register and the contents of this register are moved, in parallel, into the read-only buffer. The reason for this is to ensure received data is not lost.

  Once an entire byte is received (ie; shifted along RXD into the shift register) the RI bit is set and the data byte is moved into the read-only buffer.

  If another data byte is being received, it will be shifted into the shift register.

  However, if the controller moves the data from the read-only buffer (for example, MOV A, SBUF) before the next byte has been entirely received, then no data is lost.

Stepper Motor Control :

The circuit consists of AT89C51 microcontroller, ULN2003A, Motor. AT89c51 is low power, high-performance, CMOS 8bit, 8051 family microcontroller. It has 32 programmable I/O lines. It has 4K bytes of Flash programmable and erasable memory. An external crystal oscillator is connected at the 18 and 19 pins of the microcontroller. Motor is connected to the port2 of the microcontroller through a driver IC.

The  ULN2003A is a current driver IC. It is used to drive the current of the stepper motor as it requires more than 60mA of current. It is an array of Darlington pairs. It consists of seven pairs of Darlington arrays with common emitter. The IC consists of 16 pins in which 7 are input pins, 7 are output pins and remaining are VCC and Ground. The first four input pins are connected to the microcontroller. In the same way, four output pins are connected to the stepper motor.

Stepper motor has 6 pins. In these six pins, 2 pins are connected to the supply of 12V and the remaining are connected to the output of the stepper motor. Stepper rotates at a given step angle. Each step in rotation is a fraction of full cycle. This depends on the mechanical parts and the driving method.

Similar to all the motors, stepper motors will have stator and rotor. Rotor has permanent magnet and stator has coil. The basic stepper motor has 4 coils with 90 degrees rotation step. These four coils are activated in the cyclic order. The below figure shows you the direction of rotation of the shaft. There are different methods to drive a stepper motor. Some of these are explained below.

Full Step Drive: In this method two coils are energized at a time. Thus, here two opposite coils are excited at a time. 

Half Step Drive: In this method coils are energized alternatively. Thus it rotates with half step angle. In this method, two coils can be energized at a time or single coil can be energized. Thus it increases the number of rotations per cycle. It is shown in the below figure.

Programming Display Devices:

This article is about how to interface a seven segment LED display to an 8051 microcontroller. 7 segment LED display is  very popular and it can display digits from 0 to 9 and quite a few characters like A, b, C, ., H, E, e, F, n, o,t,u,y, etc. Knowledge about how to interface a seven segment display to a micro controller is very essential in designing embedded systems. A seven segment display consists of seven LEDs arranged in the form of a squarish ‘8’ slightly inclined to the right and a single LED as the dot character. Different characters can be displayed by selectively glowing the required LED segments. Seven segment displays are of two types, common cathode and common anode. In common cathode type , the cathode of all LEDs are tied together to a single terminal which is usually labeled as ‘com‘   and the anode of all LEDs are left alone as individual pins labeled as a, b, c, d, e, f, g &  h (or dot) . In common anode type, the anode of all LEDs are tied together as a single terminal and cathodes are left alone as individual pins. The pin out scheme and picture of a typical 7 segment LED display is shown in the image below.

The circuit diagram shown above is of an AT89S51 microcontroller based 0 to 9 counter which has a 7 segment LED display interfaced to it in order to display the count.  This simple circuit illustrates two things. How to setup simple 0 to 9 up counter using 8051 and more importantly how to interface a seven segment LED display to  8051 in order to display a particular result. The common cathode seven segment display D1 is connected to the Port 1 of the microcontroller (AT89S51) as shown in the circuit diagram. R3 to R10 are current limiting resistors. S3 is the reset switch and R2,C3 forms a debouncing circuitry. C1, C2 and X1 are related to the clock circuit. The software part of the project has to do the following tasks.

Form a 0 to 9 counter with a predetermined delay (around 1/2 second here). Convert the current count into digit drive pattern. Put the current digit drive pattern into a port for displaying.

All the above said tasks are accomplished by the program given below.

Program.

ORG 000H //initial starting addressSTART: MOV A,#00001001B // initial value of accumulatorMOV B,AMOV R0,#0AH //Register R0 initialized as counter which counts from 10 to 0LABEL: MOV A,BINC AMOV B,AMOVC A,@A+PC // adds the byte in A to the program counters addressMOV P1,AACALL DELAY // calls the delay of the timerDEC R0//Counter R0 decremented by 1MOV A,R0 // R0 moved to accumulator to check if it is zero in next instruction.JZ START //Checks accumulator for zero and jumps to START. Done to check if counting has been finished.SJMP LABELDB 3FH // digit drive pattern for 0DB 06H // digit drive pattern for 1DB 5BH // digit drive pattern for 2DB 4FH // digit drive pattern for 3DB 66H // digit drive pattern for 4DB 6DH // digit drive pattern for 5DB 7DH // digit drive pattern for 6DB 07H // digit drive pattern for 7DB 7FH // digit drive pattern for 8DB 6FH // digit drive pattern for 9DELAY: MOV R4,#05H // subroutine for delayWAIT1: MOV R3,#00HWAIT2: MOV R2,#00HWAIT3: DJNZ R2,WAIT3DJNZ R3,WAIT2DJNZ R4,WAIT1RETEND

ARM architecture

32-bit RISC-processor core (32-bit instructions), 37 pieces of 32-bit integer registers (16 available, Pipelined (ARM7: 3 stages), Cached (depending on the implementation), Von Neuman-type bus structure (ARM7), Harvard , (ARM9), 8 / 16 / 32 -bit data types, 7 modes of operation (usr, fiq, irq, svc, abt, sys, und), Simple structure -> reasonably good speed / power consumption ratio.

ARM7TDMI

ARM7TDMI is a core processor module embedded in many ARM7 microprocessors, such as ARM720T, ARM710T, ARM740T, and Samsung’s KS32C50100. It is the most complex processor core module in ARM7 series.T: capable of executing Thumb instruction setD: Featuring with IEEE Std. 1149.1 JTAG boundary-scan debugging interface.M: Featuring with a Multiplier-And-Accumulate (MAC) unit for DSP applications.I: Featuring with the support of embedded In-Circuit Emulator.Three Pipe Stages: Instruction fetch, decode, and Execution.

FEATURESA 32-bit RSIC processor core capable of executing 16- bit instructions (Von Neumann Architecture) High density code The Thumb’s set’s 16-bit instru ction length allows it to approach about 65% of standard ARM code size while retaining ARM 32-bit processor performance. Smaller die size About 72,000 transistors Occupying only about 4.8mm in a 0.6 umsemiconductor technology. Lower power consumption dissipate about 2mW MHZwith 0.6um technology.