Video and Image Processing Suite User Guide · 2021. 1. 29. · Video and Image Processing Suite Overview 1 2015.05.04 UG-VIPSUITE Subscribe Send Feedback The Altera® Video and Image

Video and Image Processing Suite UserGuide

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Contents

Video and Image Processing Suite Overview..................................................... 1-1Release Information.....................................................................................................................................1-3Device Family Support................................................................................................................................ 1-4Latency...........................................................................................................................................................1-5In-System Performance and Resource Guidance....................................................................................1-8Stall Behavior and Error Recovery.......................................................................................................... 1-12

Interfaces............................................................................................................. 2-1Video Formats.............................................................................................................................................. 2-2Avalon-ST Video Protocol..........................................................................................................................2-7

Video Data Packets........................................................................................................................ 2-11Static Parameters of Video Data Packets....................................................................................2-11Control Data Packets.....................................................................................................................2-15Ancillary Data Packets.................................................................................................................. 2-19User-Defined and Altera-Reserved Packets............................................................................... 2-19Packet Propagation........................................................................................................................ 2-19Transmission of Avalon-ST Video Over Avalon-ST Interfaces..............................................2-20Packet Transfer Examples.............................................................................................................2-21

Avalon-MM Slave Interfaces....................................................................................................................2-25Specification of the Type of Avalon-MM Slave Interfaces.......................................................2-27

Avalon-MM Master Interfaces.................................................................................................................2-28Specification of the Type of Avalon-MM Master Interfaces....................................................2-28

Buffering of Non-Image Data Packets in Memory............................................................................... 2-29

Getting Started.................................................................................................... 3-1IP Catalog and Parameter Editor...............................................................................................................3-1

Specifying IP Core Parameters and Options................................................................................3-2Installing and Licensing IP Cores.............................................................................................................. 3-2

OpenCore Plus IP Evaluation........................................................................................................ 3-3

Clocked Video Interface IP Cores.......................................................................4-1Control Port..................................................................................................................................................4-1Clocked Video Input Format Detection................................................................................................... 4-2

Interrupts.......................................................................................................................................... 4-5Clocked Video Output Video Modes........................................................................................................4-5

Interrupts.......................................................................................................................................... 4-9Generator Lock.............................................................................................................................................4-9Underflow and Overflow.......................................................................................................................... 4-11Timing Constraints....................................................................................................................................4-12Handling Ancillary Packets...................................................................................................................... 4-12

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Modules for Clocked Video Input II IP Core........................................................................................ 4-15Clocked Video Interface Parameter Settings......................................................................................... 4-18Clocked Video Interface Signals.............................................................................................................. 4-26Clocked Video Interface Control Registers............................................................................................4-36

2D FIR Filter IP Core.......................................................................................... 5-1Calculation Precision...................................................................................................................................5-1Coefficient Precision....................................................................................................................................5-2Result to Output Data Type Conversion.................................................................................................. 5-22D FIR IP Core Parameter Settings...........................................................................................................5-22D FIR Filter Signals....................................................................................................................................5-42D FIR Filter Control Registers................................................................................................................. 5-5

Video Mixing IP Cores........................................................................................ 6-1Alpha Blending.............................................................................................................................................6-2Video Mixing Parameter Settings..............................................................................................................6-3Video Mixing Signals...................................................................................................................................6-5Video Mixing Control Registers................................................................................................................ 6-8

Chroma Resampler IP Core................................................................................ 7-1Horizontal Resampling (4:2:2)................................................................................................................... 7-1

4:4:4 to 4:2:2...................................................................................................................................... 7-24:2:2 to 4:4:4...................................................................................................................................... 7-2

Vertical Resampling (4:2:0)........................................................................................................................ 7-3Chroma Resampler Parameter Settings.................................................................................................... 7-4Chroma Resampler Signals.........................................................................................................................7-5

Video Clipping IP Cores..................................................................................... 8-1Video Clipping Parameter Settings........................................................................................................... 8-1Video Clipping Signals................................................................................................................................8-4Video Clipping Control Registers..............................................................................................................8-6

Color Plane Sequencer IP Core...........................................................................9-1Combining Color Patterns..........................................................................................................................9-1Rearranging Color Patterns........................................................................................................................9-2Splitting and Duplicating............................................................................................................................9-3Subsampled Data..........................................................................................................................................9-4Color Plane Sequencer Parameter Settings.............................................................................................. 9-4Color Plane Sequencer Signals................................................................................................................... 9-5

Color Space Conversion IP Cores..................................................................... 10-1Input and Output Data Types.................................................................................................................. 10-2Color Space Conversion............................................................................................................................10-2Result of Output Data Type Conversion................................................................................................ 10-3

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Color Space Conversion Parameter Settings..........................................................................................10-4Color Space Conversion Signals.............................................................................................................. 10-8Color Space Conversion Control Registers..........................................................................................10-10

Control Synchronizer IP Core.......................................................................... 11-1Using the Control Synchronizer IP Core............................................................................................... 11-2Control Synchronizer Parameter Settings..............................................................................................11-4Control Synchronizer Signals...................................................................................................................11-5Control Synchronizer Control Registers................................................................................................ 11-6

Deinterlacing IP Cores...................................................................................... 12-1Deinterlacing Methods..............................................................................................................................12-2

Bob with Scanline Duplication.....................................................................................................12-3Bob with Scanline Interpolation.................................................................................................. 12-3Weave.............................................................................................................................................. 12-3Motion-Adaptive........................................................................................................................... 12-3Pass-Through Mode for Progressive Frames.............................................................................12-6

Frame Buffering......................................................................................................................................... 12-6Frame Rate Conversion.............................................................................................................................12-8Bandwidth Requirement Calculations for 10-bit YCbCr Video......................................................... 12-8Behavior When Unexpected Fields are Received.................................................................................. 12-9Handling of Avalon-ST Video Control Packets.................................................................................. 12-10Deinterlacing Parameter Settings.......................................................................................................... 12-10Deinterlacing Signals...............................................................................................................................12-17Deinterlacing Control Registers............................................................................................................ 12-23Design Guidelines for Broadcast Deinterlacer IP Core......................................................................12-30

Tuning Motion Shift....................................................................................................................12-32Active Video Threshold Adjustment........................................................................................ 12-32

Frame Reader IP Core....................................................................................... 13-1Single-Cycle Color Patterns......................................................................................................................13-1Frame Reader Output Pattern and Memory Organization..................................................................13-2Frame Reader Parameter Settings............................................................................................................13-3Frame Reader Signals................................................................................................................................ 13-3Frame Reader Control Registers..............................................................................................................13-5

Frame Buffer IP Cores.......................................................................................14-1Double Buffering........................................................................................................................................14-2Triple Buffering..........................................................................................................................................14-2Locked Frame Rate Conversion...............................................................................................................14-3Handling of Avalon-ST Video Control Packets.................................................................................... 14-3Color Format.............................................................................................................................................. 14-4Frame Buffer Parameter Settings.............................................................................................................14-5Frame Buffer Signals..................................................................................................................................14-9Frame Buffer Control Registers............................................................................................................. 14-13

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Gamma Corrector IP Core................................................................................ 15-1Gamma Corrector Parameter Settings....................................................................................................15-1Gamma Corrector Signals........................................................................................................................ 15-2Gamma Corrector Control Registers...................................................................................................... 15-3

Interlacer IP Core.............................................................................................. 16-1Interlacer Parameter Settings................................................................................................................... 16-2Interlacer Signals........................................................................................................................................16-2Interlacer Control Registers..................................................................................................................... 16-4

Scaler II IP Core.................................................................................................17-1Nearest Neighbor Algorithm................................................................................................................... 17-1Bilinear Algorithm.....................................................................................................................................17-2

Bilinear Algorithmic Description................................................................................................ 17-2Polyphase and Bicubic Algorithm........................................................................................................... 17-3

Double-Buffering........................................................................................................................... 17-5Polyphase Algorithmic Description............................................................................................ 17-6Choosing and Loading Coefficients............................................................................................ 17-6

Edge-Adaptive Scaling Algorithm...........................................................................................................17-8Scaler II Parameter Settings......................................................................................................................17-9Scaler II Signals........................................................................................................................................ 17-12Scaler II Control Registers...................................................................................................................... 17-14

Video Switching IP Cores..................................................................................18-1Mixer Layer Switching.............................................................................................................................. 18-2Video Switching Parameter Settings....................................................................................................... 18-3Video Switching Signals............................................................................................................................18-3Video Switching Control Registers......................................................................................................... 18-5

Test Pattern Generator IP Cores.......................................................................19-1Test Pattern.................................................................................................................................................19-1Generation of Avalon-ST Video Control Packets and Run-Time Control....................................... 19-3Test Pattern Generator Parameter Settings............................................................................................19-4Test Pattern Generator Signals................................................................................................................ 19-6Test Pattern Generator Control Registers.............................................................................................. 19-8

Trace System IP Core........................................................................................ 20-1Trace System Parameter Settings.............................................................................................................20-2Trace System Signals................................................................................................................................. 20-3Operating the Trace System from System Console...............................................................................20-4

Loading the Project and Connecting to the Hardware.............................................................20-5Trace Within System Console......................................................................................................20-6TCL Shell Commands................................................................................................................... 20-7

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Avalon-ST Video Monitor IP Core................................................................... 21-1Packet Visualization.................................................................................................................................. 21-2Monitor Settings........................................................................................................................................ 21-3Avalon-ST Video Monitor Parameter Settings......................................................................................21-3Avalon-ST Video Monitor Signals.......................................................................................................... 21-4Avalon-ST Video Monitor Control Registers........................................................................................21-6

Avalon-ST Video Verification IP Suite..............................................................A-1Avalon-ST Video Class Library.................................................................................................................A-2Running the Tests....................................................................................................................................... A-7

Video File Reader Test................................................................................................................. A-10Constrained Random Test...........................................................................................................A-15

Complete Class Reference........................................................................................................................A-19c_av_st_video_control ................................................................................................................ A-19c_av_st_video_data ......................................................................................................................A-21c_av_st_video_file_io .................................................................................................................. A-21c_av_st_video_item ..................................................................................................................... A-26c_av_st_video_source_sink_base .............................................................................................. A-27c_av_st_video_sink_bfm_’SINK ................................................................................................A-28c_av_st_video_source_bfm_’SOURCE .....................................................................................A-29c_av_st_video_user_packet ........................................................................................................ A-30c_pixel ............................................................................................................................................A-31

Raw Video Data Format...........................................................................................................................A-31

Choosing the Correct Deinterlacer.................................................................... B-1Cadence Detection and Reverse Pulldown in the Deinterlacer II IP Core..........................................B-3

Additional Information......................................................................................C-1Document Revision History...................................................................................................................... C-1How to Contact Altera............................................................................................................................... C-5

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Video and Image Processing Suite Overview 12015.05.04

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The Altera® Video and Image Processing Suite collection of IP cores ease the development of video andimage processing designs.

You can use these IP cores in a wide variety of image processing and display applications.

Attention: Altera has scheduled the following IP cores for product obsolescence and will discontinuesupport for it.

• Clipper• Test Pattern Generator

Altera recommends that you do not use these IP cores in new designs. For more informationabout Altera’s current IP offering, visit the Altera Intellectual Property web page.

Table 1-1: Video and Image Processing Suite IP Core Features

The table lists the IP cores in the Video and Image Processing Suite.

IP CoreFeature Support

Pixels in Parallel 4:2:2 Support Interlaced

2D FIR Filter No No No

Alpha BlendingMixer

No Yes Yes (1)

Chroma Resampler No Yes No

Clipper No Yes Yes (2)

Clipper II Yes Yes Yes (2)

Clocked VideoInput (CVI)

No Yes Yes

Clocked VideoInput II (CVI II)

Yes Yes Yes

(1) The IP core accepts interlaced input streams but they are treated as progressive inputs. Consequently, yourequire external logic to synchronize the input fields and prevent the mixing of F0 fields with F1 fields.

(2) The IP core accepts interlaced inputs but they are treated as progressive inputs.

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IP CoreFeature Support

Pixels in Parallel 4:2:2 Support Interlaced

Clocked VideoOutput (CVO)

No Yes Yes

Clocked VideoOutput II (CVO II)

Yes Yes Yes

Color PlaneSequencer

No Yes Yes

Color SpaceConverter (CSC)

No No Yes

Color SpaceConverter II (CSCII)

Yes No Yes

Control Synchron‐izer

No Yes Yes

Deinterlacer No Yes Yes

Deinterlacer II No Yes Yes

Broadcast Deinter‐lacer

No Yes Yes

Frame Buffer No Yes Yes

Frame Buffer II Yes Yes Yes

Frame Reader No Yes Yes

Gamma Corrector No Yes Yes

Interlacer No Yes Yes (3)

Mixer II Yes Yes Yes (1)

Scaler II No Yes Yes (2)

Switch No Yes Yes

Switch II Yes Yes Yes

Test PatternGenerator

No Yes Yes (4)

Test PatternGenerator II

Yes Yes Yes (4)

(3) The IP core either discards or propagates without change the interlaced data if you select Pass-throughmode in the parameter editor.

(4) For interlaced data NTSC, mismatched line counts of F0 and F1 are not supported.

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Release InformationThe following table lists information about this release of the Video and Image Processing Suite.

Table 1-2: Release Information

Item Description

Version 15.0

Release Date May 2015

OrderingCode

IPS-VIDEO (Video and Image Processing Suite)

Product ID 00B3 (2D FIR Filter)

00B5 (Alpha BlendingMixer)

0115 (Mixer II)

00D1 (Avalon-ST VideoMonitor)

00B1 (Chroma Resampler)

00C8 (Clipper)

0115 (Clipper II)

00C4 (Clocked VideoInput)

00F1 (Clocked VideoInput II)

00C5 (Clocked VideoOutput)

00EF (Clocked VideoOutput II)

00C9 (Color PlaneSequencer)

0003 (Color SpaceConverter)

00F2 (Color SpaceConverter II)

00D0 (Control Synchron‐izer)

00B6 (Deinterlacer)

00EE (Deinterlacer II)

0114 (Broadcast Deinter‐lacer)

0112 (Frame Reader)

00C3 (Frame Buffer)

0115 (Frame Buffer II)

00B2 (Gamma Corrector)

00DC (Interlacer)

00E9 (Scaler II)

00CF (Switch)

00F4 (Switch II)

00CA (Test Pattern Generator)

00F3 (Test Pattern Generator II)

00ED (Trace System)

Vendor ID 6AF7

Altera verifies that the current version of the Quartus II software compiles the previous version of each IPcore, if this IP core was included in the previous release. Any exceptions to this verification are reported inthe MegaCore IP Library Release Notes and Errata. Altera does not verify compilation with IP coreversions older than the previous release.

Related Information

• Altera IP Library Release Notes• Errata for VIP Suite in the Knowledge Base

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Device Family SupportThe table below lists the device support information for the Video and Image Processing Suite IP cores.

Table 1-3: Device Family Support

Device Family Support

Arria II GX / Arria II GZ Final

Arria V Final

Arria 10 Final—Supports only the following IP cores:

• Avalon-ST Video Monitor• Broadcast Deinterlacer• Clipper II• Clocked Video Input• Clocked Video Input II• Clocked Video Output• Clocked Video Output II• Color Space Converter II• Deinterlacer II• Frame Buffer II• Mixer II• Scaler II• Switch II• Test Pattern Generator II

Cyclone IV ES / Cyclone IV GX Final

Cyclone V Final

MAX 10 Final

Stratix IV Final

Stratix V Final

Other device families No support

Related InformationWhat's New for IP in Quartus II SoftwareProvides more information about the support levels and current status.

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LatencyYou can use the latency information to predict the approximate latency between the input and the outputof your video processing pipeline.

The latency is described using one or more of the following measures:

• the number of progressive frames• the number of interlaced fields• the number of lines when less than a field of latency• a small number of cycles O (cycles)

Note: O refers to a small number of clock cycles, and is not of zero value.

The latency is measured with the assumption that the IP core is not being stalled by other functions on thedata path; (the output ready signal is high).

Table 1-4: Video and Image Processing Suite Latency

The table below lists the approximate latency from the video data input to the video data output for typical usagemodes of the Video and Image Processing Suite IP cores.

IP Core Mode Latency

2D FIR Filter Latency Filter size: N × N (N–1) lines + O (cycles)

Alpha Blending Mixer/ Mixer II All modes O (cycles)

Chroma Resampler

Input format: 4:2:2; Outputformat: 4:4:4

O (cycles)

Input format: 4:2:0; Outputformat: 4:4:4 or 4:2:2

1 line + O (cycles)

Clipper/ Clipper II All modes O (cycles)

Clocked Video Input

Note: Add 1 cycle if you turnedon the Allow color planesin sequence inputparameter.

• Synchronization signals:Embedded in video

• Video in and out use thesame clock: On

8 cycles

• Synchronization signals: Onseparate wires


5 cycles

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Clocked Video Input II

• Synchronization signals:Embedded in video


10 cycles

• Synchronization signals: Onseparate wires


6 cycles

Clocked Video Output/

Clocked Video Output II

Note: Add 1 cycle if you turnedon the Allow color planesin sequence inputparameter.

All modes with video in and outuse the same clock: On

3 cycles

Note: Note: Minimum latencycase when video inputand output rates aresynchronized.

Color Plane Sequencer All modes O (cycles)

Color Space Converter (CSC)/

Color Space Converter II

All modes O (cycles)

Control Synchronizer All modes O (cycles)

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Deinterlacer

• Method: Bob• Frame buffering: None

O (cycles)

• Method: Motion-adaptive orWeave

• Frame buffering: Double ortriple buffering with rateconversion

• Output frame rate: As inputframe rate

1 frame + O (lines)

• Method: Motion-adaptive orWeave

• Frame buffering: Double ortriple buffering with rateconversion

• Output frame rate: As inputfield rate

1 field + O (lines)

• Method: All• Frame buffering: Double or

triple buffering with rateconversion

• Passthrough mode(propagate progressiveframes unchanged): On.

1 frame + O (lines)

Deinterlacer II • Method: Motion-adaptive• Frame buffering: None• Output frame rate: As input

field rate

2 lines

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Broadcast Deinterlacer

• Method: Motion-adaptive• Frame buffering: None• Output frame rate: As input

field rate

1 field + 2 lines

• Method: Motion-adaptive,video-over-film mode

• Frame buffering: 3 inputfields are buffered

• Output frame rate: As inputfield rate

40% to 60% (depending onphasing) of the time, the coreperforms a weave forward sothere is no initial field of latency.

1 field + 2 lines, or 2 lines

Frame Buffer/ Frame Buffer II All modes 1 frame + O (lines)

Frame Reader No latency issues.

Gamma Corrector All modes O (cycles)

Interlacer All modes O (cycles)

Scaler II • Scaling algorithm: Polyphase• Number of vertical taps: N

(N–1) lines + O (cycles)

Switch/ Switch II All modes 2 cycles

Test Pattern Generator/

Test Pattern Generator II

No latency issues.

In-System Performance and Resource GuidanceThe performance and resource data provided for your guidance.

Note: Run your own synthesis and fMAX trials to confirm the listed IP cores meet your system require‐ments.

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Table 1-5: Performance and Resource Data Using Arria V Devices

The following data are obtained through a 4K test design example using an Arria V device (5AGXFB3H4F35C4).

The general settings for the design is 8 bits per color plane; 2 pixels in parallel. The target fMAX is 148.5 MHz.

IP Core Configuration ALM RAM DSP

Mixer II • Number of color planes in parallel = 3• Inputs = 4• Output = 1• Internal Test Pattern Generator

1,591 0 0

Clocked VideoInput II

• Number of color planes in parallel = 3• Sync signals = On separate wires• Pixel FIFO size = 4096 pixels• Use control port = On

540 26 0

Clocked VideoOutput II

• Number of color planes in parallel = 3• Sync signals = On separate wires• Pixel FIFO size = 4096 pixels• Use control port = On• Run-time configurable video modes = 4

2,504 49 0

Color SpaceConverter II

• Run-time control = On• Color model conversion = RGb to YCbCr

1,515 0 18

Broadcast Deinter‐lacer

• Number of color planes in parallel = 2• Avalon-MM master local ports width =

256• FIFO depths = 512• Run-time control = Off

11,516 145 34

Frame Buffer II • Number of color planes in parallel = 2• Avalon-MM master ports width = 256• Read/write FIFO depth = 128• Frame dropping = On• Frame repeating = On

1,472 19 0


• Color space = RGB• Run-time control of image size = On

135 0 0

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Table 1-6: Performance and Resource Data Using Cyclone V Devices

The following data are obtained through a video design example using a Cyclone V device (5CGTFD9E5F35C7).

The general setting for the design is 8 bits per color plane. The target fMAX is 100 MHz.


2D FIR Filter • Number of color planes in sequence = 3• Filter size = 3×3• Runtime control = On• Integer bits = 4• Fractional bits = 3

581 10 3

Avalon-ST VideoMonitor

• Number of color planes in parallel = 3• Capture video pixel data = On

1,035 10 0

Avalon-ST VideoMonitor

• Number of color planes in parallel = 3• Capture video pixel data = Off

479 9 0

Alpha BlendingMixer

• Number of color planes in parallel = 3• Number of layers being mixed = 5• Alpha blending = On

1,324 1 24

ChromaResampler

• 4:2:2, number of color planes in parallel(din) = 2

• 4:4:4, number of color planes in parallel(dout) = 3

• Horizontal filtering algorithm = Filtered• Luma adaptive = On

591 0 0

Clipper II • Number of pixels (color planes) in parallel= 3

• Clipping method = Rectangle• Enable runtime control of clipping

parameters = On

402 0 0

Clocked VideoInput

• Number of color planes in parallel = 3• Sync signals = On separate wires• Pixel FIFO size = 2048 pixels• Use control port = On

257 13 0

Clocked VideoInput

• Number of color planes in sequence = 2• Sync signals = Embedded• Pixel FIFO size = 2048 pixels• Use control port = On

317 9 0

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Clocked VideoOutput

• Number of color planes in parallel = 3• Sync signals = On separate wires• Pixel FIFO size = 1024 pixels• Use control port = On• Run-time configurable video modes = 1

512 5 0


• din0: Color planes in parallel = 4• dout0: Color planes in parallel = 3• dout1: Color planes in parallel = 1

104 0 0

Color SpaceConverter

• Color plane configuration = Three colorplanes in parallel

• Run-time control = Off• Color model conversion = CbCrY': SDTV

to Computer B'G'R'• Coefficients integer bits = 2• Summands integer bits = 9• Coefficient and summand fractional bits =

8

284 0 9

Deinterlacer II • Number of color planes in parallel = 3• Deinterlace algorithm = Motion adaptive• Cadence detection algorithm = 3:2 detector• Avalon-MM master local ports width =

128• FIFO depths = 64

3,655 67 3

Frame Buffer • Number of color planes in parallel = 3• Avalon-MM master ports width = 128• Read/write FIFO depth = 64• Frame dropping = On• Frame repetition = On

1,084 19 0

Frame Reader • Number of color planes in parallel = 4• Avalon-MM master port width = 128• Read master FIFO depth = 64• Use separate clocks for the Avalon-MM

master interfaces = On

756 6 0

Gamma Corrector Number of color planes in parallel = 3 142 3 0

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Scaler II • Symbols in parallel = 3• Scaling algorithm = Polyphase• Enable run-time control of input/output

frame size = On• Vertical/horizontal filter taps = 4• Vertical/horizontal filter phases = 14

1,010 12 12

Test PatternGenerator

• Color space = RGB• Run-time control of image size = Off

65 0 0

Trace System • Buffer size = 8192• Bit width of capture interface(s) = 32• Number of inputs = 2

1,224 12 0

Stall Behavior and Error RecoveryThe Video and Image Processing Suite IP cores do not continuously process data. Instead, they use flow-controlled Avalon-ST interfaces, which allow them to stall the data while they perform internalcalculations.

During control packet processing, the IP cores might stall frequently and read or write less than once perclock cycle. During data processing, the IP cores generally process one input or output per clock cycle.There are, however, some stalling cycles. Typically, these are for internal calculations between rows ofimage data and between frames/fields.

When stalled, an IP core indicates that it is not ready to receive or produce data. The time spent in thestalled state varies between IP cores and their parameterizations. In general, it is a few cycles between rowsand a few more between frames.

If data is not available at the input when required, all of the IP cores stall and do not output data. With theexceptions of the Deinterlacer and Frame Buffer in double or triple-buffering mode, none of the IP coresoverlap the processing of consecutive frames. The first sample of frame F + 1 is not input until after the IPcores produce the last sample of frame F.

When the IP cores receive an endofpacket signal unexpectedly (early or late), the IP cores recover fromthe error and prepare for the next valid packet (control or data).

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IP Core Stall Behavior Error Recovery

2D FIR Filter • Has a delay of a little more than N–1lines between data input and output inthe case of a N×N 2D FIR Filter.

• Delay caused by line buffering internalto the IP core.

• Resolution is not configurable at runtime.

• Does not read the control packetspassed through it.

An error condition occurs if anendofpacket signal is received too earlyor too late for the compile timeconfigured frame size. In either case, the2D FIR Filter always creates outputvideo packets of the configured size.

• If an input video packet has a lateendofpacket signal, then the extradata is discarded.

• If an input video packet has an earlyendofpacket signal, then the videoframe is padded with an undefinedcombination of the last input pixels.

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Alpha BlendingMixer/

Mixer II

All modes stall for a few cycles after eachoutput frame and between output lines.

Between frames, the IP core processes non-image data packets from its input layers insequential order. The core may exertbackpressure during the process until theimage data header has been received for allits input.

During the mixing of a frame, the IP core:

• Reads from the background input foreach non-stalled cycle.

• Reads from the input ports associatedwith layers that currently cover thebackground image.

Because of pipelining, the foreground pixelof layer N is read approximately N activecycles after the corresponding backgroundpixel has been read.

• If the output is applying backpressure orif one input is stalling, the pipeline stallsand the backpressure propagates to allactive inputs.

• When alpha blending is enabled, onedata sample is read from each alpha portonce each time that a whole pixel of datais read from the corresponding inputport.

There is no internal buffering in the IP core,so the delay from input to output is just afew clock cycles and increases linearly withthe number of inputs.

The Alpha Blending Mixer IP coreprocesses video packets from thebackground layer until the end of packetis received.

• Receiving an endofpacket signal tooearly for the background layer—theIP core enters error mode andcontinues writing data until it hasreached the end of the current line.The endofpacket signal is then setwith the last pixel sent.

• Receiving an endofpacket signalearly for one of the foreground layersor for one of the alpha layers—the IPcore stops pulling data out of thecorresponding input and pads theincomplete frame with undefinedsamples.

• Receiving an endofpacket signal latefor the background layer, one ormore foreground layers, or one ormore alpha layers—the IP core enterserror mode.

This error recovery process maintainsthe synchronization between all theinputs and is started once the outputframe is completed. A large number ofsamples may have to be discardedduring the operation and backpressurecan be applied for a long time on mostinput layers. Consequently, this errorrecovery mechanism could trigger anoverflow at the input of the system.


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ChromaResampler

All modes stall for a few cycles betweenframes and between lines.

Latency from input to output variesdepending on the operation mode of the IPcore.

• The only modes with latency of morethan a few cycles are 4:2:0 to 4:2:2 and4:2:0 to 4:4:4—corresponding to one lineof 4:2:0 data

• The quantities of data input and outputare not equal because this is a rate-changing function.

• Always produces the same number oflines that it accepts—but the number ofsamples in each line varies according tothe subsampling pattern used.

When not stalled, always processes onesample from the more fully sampled side oneach clock cycle. For example, thesubsampled side pauses for one third of theclock cycles in the 4:2:2 case or half of theclock cycles in the 4:2:0 case.

• Receiving an early endofpacketsignal—the IP core stalls its input butcontinues writing data until it hassent an entire frame.

• Not receiving an endofpacket signalat the end of a frame—the IP corediscards data until it finds end-of-packet.

Clipper/

Clipper II• Stalls for a few cycles between lines and

between frames.• Internal latency is less than 10 cycles.• During the processing of a line, it reads

continuously but only writes wheninside the active picture area as definedby the clipping window.

• Receiving an early endofpacketsignal—the IP core stalls its input butcontinues writing data until it hassent an entire frame.

• Not receiving an endofpacket signalat the end of a frame—the IP corediscards data until it finds end ofpacket.

Clocked VideoInput/

Clocked VideoInput II

• Dictated by incoming video.• If its output FIFO is empty, during

horizontal and vertical blanking periodsthe IP core does not produce any videodata.

If an overflow is caused by adownstream core failing to receive dataat the rate of the incoming video, theClocked Video Input sends anendofpacket signal and restart sendingvideo data at the start of the next frameor field.



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Clocked VideoOutput/

Clocked VideoOutput II

• Dictated by outgoing video.• If its input FIFO is empty, during

horizontal and vertical blanking periodsthe IP core stalls and does not take inany more video data.

• Receiving an early endofpacketsignal— the IP core resynchronizesthe outgoing video data to theincoming video data on the next startof packet it receives.

• Receiving a late endofpacket— theIP core resynchronizes the outgoingvideo data to the incoming videoimmediately.

• If Genlock functionality is enabled—the IP core does not resynchronize tothe incoming video.


• Stalls for approximately 10 cycles afterprocessing each line of a video frame.

• Between frames the IP core stalls forapproximately 30 cycles

• Processes video packets per line untilthe IP core receives an endofpacketsignal on din0—the line width istaken from the control packets ondin0.

• Receiving an endofpacket signal oneither din0 or din1— the IP coreceases to produce output.

For the number of cycles left to finishthe line, the IP core continues to drainthe inputs that have not indicated end ofpacket.

• Drains din0 until it receives anendofpacket signal on this port(unless it has already indicated end ofpacket), and stalls for up to one lineafter this endofpacket signal.

• Signals end of packet on its outputsand continue to drain its inputs thathave not indicated end of packet.

Color SpaceConverter/

Color SpaceConverter II

• Only stalls between frames and notbetween rows.

• It has no internal buffering apart fromthe registers of its processing pipeline—only a few clock cycles of latency.

• Processes video packets until the IPcore receives an endofpacket signal—the control packets are not used.

• Any mismatch of the endofpacketsignal and the frame size ispropagated unchanged to the next IPcore.


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ControlSynchronizer

• Stalls for several cycles between packets.• Stalls when it enters a triggered state

while it writes to the Avalon-MM Slaveports of other IP cores.

• If the slaves do not provide a waitrequest signal, the stall lasts for no morethan 50 clock cycles. Otherwise the stallis of unknown length.

• Processes video packets until the IPcore receives an endofpacket signal—the image width, height andinterlaced fields of the control datapackets are not compared against thefollowing video data packet.

• Any mismatch of the endofpacketsignal and the frame size of videodata packet is propagated unchangedto the next IP core.

Deinterlacer • Bob algorithm

• While the bob algorithm (with nobuffering) is producing an outputframe, it alternates between simulta‐neously between

• receiving a row on the input portand producing a row of data onthe output port

• just producing a row of data onthe output port without readingany data from the input port

The delay from input to output is justa few clock cycles.

• While a field is being discarded, inputis read at the maximum rate and nooutput is generated.

• Weave algorithm

• The IP core may stall for longer thanthe usual periods between eachoutput row of the image.

• The delays may possibly stretch up to45 clock cycles due to the time takenfor internal processing in betweenlines.

• Motion-adaptive algorithm

• The IP core may stall up to 90 clockcycles.

• Receiving an endofpacket signal tooearly or too late is relative to the fielddimensions contained in the lastcontrol packet processed.

• Receiving an endofpacket signal toolate—discards extra data in allconfigurations.

• Receiving an early endofpacketsignal when it is configured for nobuffering—the IP core interrupts itsprocessing within one or two linessending undefined pixels, beforepropagating the endofpacket signal.

• Receiving an early endofpacketsignal when it is configured to bufferdata in external memory—the inputside of the IP core stops processinginput pixels. It is then ready toprocess the next frame after writingundefined pixels for the remainder ofthe current line into external RAM.The output side of the IP coreassumes that incomplete fields havebeen fully received and pads theincomplete fields to build a frame,using the undefined content of thememory.



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Deinterlacer II/

BroadcastDeinterlacer

Stores input video fields in the externalmemory and concurrently uses these inputvideo fields to construct deinterlacedframes.

• Stalls up to 50 clock cycles for the firstoutput frame.

• Additional delay of one line for secondoutput frame because the IP coregenerates the last line of the outputframe before accepting the first line ofthe next input field.

• Delay of two lines for the followingoutput frames, which includes the oneline delay from the second output frame.

• For all subsequent fields, the delayalternates between one and two lines.

• Receiving an endofpacket signal tooearly :

• The IP core generates a line withthe correct length.

• The video data in the outputframe is valid up to the pointwhere the IP core receives theendofpacket signal.

• The IP core then stops generatingoutput until it receives the nextstartofpacket signal.

• Receiving a late endofpacket signal:

• The IP core completes generatingthe current output frame with thecorrect number of lines asindicated by the last controlpacket.

• The IP core discards thesubsequent input lines.

• Once it receives a startofpacketsignal, the IP core performs a softreset and it loses the storedcadence or motion values.

• The IP core resumes deinterlacingwhen it receives the nextstartofpacket signal.

Frame Reader • Stalls the output for several tens of cyclesbefore producing each video data packet.

• Stalls the output where there iscontention for access to externalmemory.

The IP core can be stalled due tobackpressure, without consequences andit does not require error recovery.


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Frame Buffer/

Frame Buffer II• May stall frequently and read or write

less than once per clock cycle duringcontrol packet processing.

• During data processing at the input or atthe output, the stall behavior of the IPcore is largely decided by contention onthe memory bus.

• Does not rely on the content of thecontrol packets to determine the sizeof the image data packets.

• Any early or late endofpacket signaland any mismatch between the sizeof the image data packet and thecontent of the control packet arepropagated unchanged to the next IPcore.

• Does not write outside the memoryallocated for each non-image andimage Avalon-ST video packet—packets are truncated if they arelarger than the maximum sizedefined at compile time.

GammaCorrector

• Stalls only between frames and notbetween rows.

• Has no internal buffering aside from theregisters of its processing pipeline— onlya few clock cycles of latency

• Processes video packets until the IPcore receives an endofpacket signal—non-image packets are propagatedbut the content of control packets isignored.

• Any mismatch of the endofpacketsignal and the frame size ispropagated unchanged to the next IPcore.

Interlacer • Alternates between propagating anddiscarding a row from the input portwhile producing an interlaced outputfield—the output port is inactive everyother row.

• The delay from input to output is a fewclock cycles when pixels are propagated.

• Receiving endofpacket signal laterthan expected—discards extra data.

• Receiving an early endofpacketsignal—the current output field isinterrupted as soon as possible andmay be padded with a singleundefined pixel.



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Scaler II • The ratio of reads to writes isproportional to the scaling ratio andoccurs on both a per-pixel and a per-linebasis.

• The frequency of lines where reads andwrites occur is proportional to thevertical scaling ratio.

• For example scaling up vertically by afactor of 2 results in the input beingstalled every other line for the length oftime it takes to write one line of output;scaling down vertically by a factor of 2results in the output being stalled everyother line for the length of time it takesto read one line of input.

• In a line that has both input and outputactive, the ratio of reads and writes isproportional to the horizontal scalingratio. For example, scaling from 64×64to 128×128 causes 128 lines of output,where only 64 of these lines have anyreads in them. For each of these 64 lines,there are two writes to every read.

The internal latency of the IP core dependson the scaling algorithm and whether anyrun time control is enabled. The scalingalgorithm impacts stalling as follows:

• Bilinear mode: a complete line of inputis read into a buffer before any output isproduced. At the end of a frame thereare no reads as this buffer is drained.The exact number of possible writesduring this time depends on the scalingratio.

• Polyphase mode with Nv vertical taps: Nv– 1 lines of input are read into linebuffers before any output is ready. Thescaling ratio depends on the time at theend of a frame where no reads arerequired as the buffers are drained.

• Receiving an early endofpacketsignal at the end of an input line—theIP core stalls its input but continueswriting data until it has sent onfurther output line.

• Receiving an early endofpacketsignal part way through an input line—the IP core stalls its input for aslong as it would take for the openinput line to complete; completingany output line that may accompanythat input line. Then continues tostall the input, and writes one furtheroutput line.

• Not receiving an endofpacket signalat the end of a frame—the IP corediscards extra data until it finds anend of packet.


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Enabling run-time control of resolutionsaffects stalling between frames:

• With no run-time control: about 10cycles of delay before the stall behaviorbegins, and about 20 cycles of furtherstalling between each output line.

• With run-time control of resolutions:about additional 25 cycles of delaybetween frames.

Switch/

Switch II• Only stalls its inputs when performing

an output switch.• Before switching its outputs, the IP core

synchronizes all its inputs and the inputsmay be stalled during this synchroniza‐tion.

—

Test PatternGenerator/


• All modes stall for a few cycles after afield control packet, and between lines.

• When producing a line of image data,the IP core produces one sample outputon every clock cycle, but it can be stalledwithout consequences if other functionsdown the data path are not ready andexert backpressure.

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Interfaces 22015.05.04

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The IP cores in the Video and Image Processing Suite use standard interfaces for data input and output,control input, and access to external memory. These standard interfaces ensure that video systems can bequickly and easily assembled by connecting IP cores together.

The IP cores use the following types of interface:

• Avalon-ST interface—a streaming interface that supports backpressure. The Avalon-ST Videoprotocol transmits video and configuration data. This interface type allows the simple creation of videoprocessing data paths, where IP cores can be connected together to perform a series of videoprocessing functions.

• Avalon-MM slave interface—provides a means to monitor and control the properties of the IP cores.• Avalon-MM master interface—when the IP cores require access to a slave interface, for example an

external memory controller.

Figure 2-1: Abstracted Block Diagram Showing Avalon-ST and Avalon-MM Connections

The figure below shows an example of video processing data paths using the Avalon-ST and Avalon-MMinterfaces.

Clocked Video Input IP Core

DeinterlacerIP Core

DDR 2 SDRAMController with UniPHY

IP Core

Nios IIProcessor

Avalon ST Connection

Avalon MM Master to Slave Connection

Scaler II IP Core

Clocked Video Output IP Core

Note: This abstracted view is similar to that provided in the Qsys tool, where interface wires are groupedtogether as single connections.

© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos aretrademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified astrademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performanceof its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to anyproducts and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of devicespecifications before relying on any published information and before placing orders for products or services.

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The Clocked Video Input and Clocked Video Output IP cores also have external interfaces that supportclocked video standards. These IP cores can connect between the function’s Avalon-ST interfaces andfunctions using clocked video standards such as BT.656.

Related InformationAvalon Interface SpecificationsProvides more information about these interface types.

Video FormatsThe Clocked Video Output IP cores create clocked video formats, and Clocked Video Input IP coresaccept clocked video formats.

The IP cores create and accept the following formats:

• Video with synchronization information embedded in the data (in BT656 or BT1120 format)• Video with separate synchronization (H sync, V sync) signals

The CVO IP cores create a video frame consisting of horizontal and vertical blanking (containing syncs)and areas of active picture (taken from the Avalon-ST Video input).

• Video with synchronization information embedded in the data (in BT656 or BT1120 format)• Video with separate synchronization (H sync, V sync) signals

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Figure 2-2: Progressive Frame Format

Vertical Blanking

F0 Active Picture

Horiz

onta

l Blan

king

Horizontal Sync

Verti

cal S

ync

Width

Heigh

t

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Figure 2-3: Interlaced Frame Format

Vertical Blanking

F0 Active Picture

Horiz

onta

l Blan

king

Horizontal Sync

Verti

cal S

ync

F0 Vertical Blanking

F1 Active Picture

Width

Heigh

t

Width

Heigh

t

Field

For CVI and CVO IP cores, the BT656 and BT1120 formats use time reference signal (TRS) codes in thevideo data to mark the places where synchronization information is inserted in the data.

Figure 2-4: Time Reference Signal Format

The TRS codes are made up of values that are not present in the video portion of the data, and they takethe format shown in the figure below.

3FF XYZ00

TRS (10bit)


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Clocked Video Output IP Cores

For the embedded synchronization format, the CVO IP cores insert the horizontal and vertical syncs andfield into the data stream during the horizontal blanking period.

The IP cores create a sample for each clock cycle on the vid_data bus.

There are two extra signals only used when connecting to the SDI IP core. They are vid_trs, which ishigh during the 3FF sample of the TRS, and vid_ln, which produces the current SDI line number. Theseare used by the SDI IP core to insert line numbers and cyclical redundancy checks (CRC) into the SDIstream as specified in the 1.5 Gbps HD SDI and 3 Gbps SDI standards.

The CVO IP cores insert any ancillary packets (packets with a type of 13 or 0xD) into the output videoduring the vertical blanking. The IP cores begin inserting the packets on the lines specified in itsparameters or mode registers (ModeN Ancillary Line and ModeN F0 Ancillary Line). The CVO IPcores stop inserting the packets at the end of the vertical blanking.

Clocked Video Input IP Cores

The CVI IP cores support both 8 and 10-bit TRS and XYZ words. When in 10-bit mode, the IP coresignore the bottom 2 bits of the TRS and XYZ words to allow easy transition from an 8-bit system.

Table 2-1: XYZ Word Format

The XYZ word contains the synchronization information and the relevant bits of its format.Bits 10-bit 8-bit Description

Unused [5:0] [3:0] These bits are not inspected by the CVI IP cores.

H (sync) 6 4 When 1, the video is in a horizontal blanking period.

V (sync) 7 5 When 1, the video is in a vertical blanking period.

F (field) 8 6 When 1, the video is interlaced and in field 1. When 0,the video is either progressive or interlaced and in field0.

Unused 9 7 These bits are not inspected by the CVI IP cores.

For the embedded synchronization format, the vid_datavalid signal indicates a valid BT656 or BT1120sample. The CVI IP cores only read the vid_data signal when vid_datavalid is 1.

Figure 2-5: Vid_datavalid Timing

D0 D1vid_data

vid_datavalid

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The CVI IP cores extract any ancillary packets from the Y channel during the vertical blanking. Ancillarypackets are not extracted from the horizontal blanking.

• Clocked Video Input IP core—The extracted packets are produced through the CVI IP cores’ Avalon-ST output with a packet type of 13 (0xD).

• Clocked Video Input II IP core— The extracted packets are stored in a RAM in the IP core, which canbe read via the control interface.

The extracted packets are produced through the CVI IP cores’ Avalon-ST output with a packet type of 13(0xD).

For information about Avalon-ST Video ancillary data packets, refer to Ancillary Data Packets on page2-19.

Separate Synchronization Format

The separate synchronization format uses separate signals to indicate the blanking, sync, and fieldinformation.

The CVO IP cores create horizontal and vertical syncs and field information through their own signals.The CVO IP cores create a sample for each clock cycle on the vid_data bus. The vid_datavalid signalindicates when the vid_data video output is in an active picture period of the frame.

Table 2-2: Clocked Video Input and Output Signals for Separate Synchronization Format Video

Signal Name Description

vid_h_sync When 1, the video is in a horizontal synchronization period.vid_v_sync When 1, the video is in a vertical synchronization period.vid_f When 1, the video is interlaced and in field 1. When 0, the video is

either progressive or interlaced and in field 0.vid_h When 1, the video is in a horizontal blanking period, (only for Clocked

Video Output IP core).vid_v When 1, the video is in a vertical blanking period, (only for Clocked

Video Output IP core).vid_de When asserted, the video is in an active picture period (not horizontal

or vertical blanking).

Note: Only for Clocked Video Input IP cores.

vid_datavalid When asserted, the video is in an active picture period (not horizontalor vertical blanking).

Note: Only for Clocked Video Output IP cores.


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Figure 2-6: Separate Synchronization Signals Timing Diagram

vid_de/vid_datavalid (1)

D0 DNvid_data

(1): vid_datavalid: Clocked Video Output IP core vid_de: Clocked Video Input IP core

D1 Dn+2Dn+1

vid_v_sync

vid_h_sync

vid_f

The CVI IP cores only read the vid_data, vid_de, vid_h_sync, vid_v_sync, and vid_f signals whenvid_datavalid is 1. This allows the CVI IP cores to support oversampling where the video clock isrunning at a higher rate than the pixel clock.

Video Locked Signal

The vid_locked signal indicates that the clocked video stream is active. When the signal has a value of 1,the CVI IP cores take the input clocked video signals as valid, and read and process them as normal.When the signal has a value of 0 (if for example the video cable is disconnected or the video interface isnot receiving a signal):

• Clocked Video Input IP core: The IP core takes the input clocked video signals as invalid and do notprocess them.

• Clocked Video Input II IP core: The vid_clk domain registers of the IP core are held in reset and novideo is processed. The control and Avalon-ST Video interfaces are not held in reset and will respondas normal. The vid_locked signal is synchronized internally to the IP core and is asynchronous to thevid_clk.

If the vid_locked signal goes invalid while a frame of video is being processed, the CVI IP cores end theframe of video early.

Avalon-ST Video ProtocolThe Avalon-ST Video protocol is a packet-oriented way to send video and control data over Avalon-STconnections. The IP cores in the Video and Image Processing Suite use the Avalon-ST Video protocol.

Using the Avalon-ST Video protocol allows the construction of image processing data paths whichautomatically configure to changes in the format of the video being processed. This minimizes theexternal control logic required to configure a video system.

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Table 2-3: Avalon-ST Video Protocol Parameters

Parameter Values

IP Cores Frame Width/Height

Interlaced/Progressive

Bits per ColorSample

Color Pattern

2D FIR Filter User-defined—throughparameter editor

Progressive User-defined—throughparameter editor

One, two, or threechannels in sequence.

Alpha Blending Mixer Run-timecontrolled


Specifiedseparately forimage data andalpha blending.

• din and dout: One,two or threechannels insequence

• alpha_in: A singlecolor planerepresenting thealpha value for eachpixel

Mixer II No run-timecontrol


Two or three channelsin parallel.

Chroma Resampler Run-timecontrolled


User-defined—throughparameter editor

Clipper/Clipper II Run-timecontrolled

Either one—interlaced inputsare accepted buttreated asprogressiveinputs.


Any combination ofone, two, three, or fourchannels in each ofsequence or parallel.

Color Plane Sequencer Run-timecontrolled

Either one User-defined—throughparameter editor


Color Space Converter Run-timecontrolled


Three color planes inparallel or sequence

Color Space ConverterII

No run-timecontrol


Three color planes inparallel or sequence

Control Synchronizer Run-timecontrolled

Run-timecontrolled


Up to four color planesin parallel, with anynumber of color planesin sequence.

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Parameter Values




Color Pattern

Deinterlacer Run-timecontrolled

Interlaced inputand progressiveoutput (plusoptionalpassthroughmode forprogressiveinput)


• One, two, or threechannels insequence

• alpha_in: A singlecolor planerepresenting thealpha value for eachpixel

Deinterlacer II Run-timecontrolled

Interlaced inputand progressiveoutput (pluspassthroughmode forprogressiveinput)


Any combination oftwo or three channelsin each of parallel.

Broadcast Deinterlacer Run-timecontrolled

Interlaced inputand progressiveoutput (pluspassthroughmode forprogressiveinput)


Two channels inparallel (4:2:2 only)

Frame Reader User-defined—through Avalon-MM slavecontrol port

User-defined—through Avalon-MM slavecontrol port


Up to four color planesin parallel, with up tothree color planes insequence.

Frame Buffer Run-timecontrolled

Progressive; insome casesinterlaced dataaccepted


Any combination ofone, two, three, or fourchannels in each ofsequence or parallel.

Frame Buffer II No run-timecontrol

Progressiveinputs only


Any combination ofone, two, three, or fourchannels in each ofparallel.

Gamma Corrector Run-timecontrolled


One, two or threechannels in sequenceor parallel.

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Parameter Values




Color Pattern

Interlacer Run-timecontrolled

Progressive;interlaced data iseither discardedor propagatedwithout changein parametereditor



Test Pattern Generator User-defined—throughparameter editoror run-timecontrolled




Test Pattern GeneratorII

User-defined—throughparameter editoror run-timecontrolled



RGB 4:4:4 or YCbCr4:4:4, 4:2:2 or 4:2:0 inparallel or sequence.

Packets

The packets of the Avalon-ST Video protocol are split into symbols—each symbol represents a singlepiece of data. For all packet types on a particular Avalon-ST interface, the number of symbols sent inparallel (that is, on one clock cycle) and the bit width of all symbols is fixed. The symbol bit width andnumber of symbols sent in parallel defines the structure of the packets.

The functions predefine the following three types of packet:

• Video data packets containing only uncompressed video data• Control data packets containing the control data configure the cores for incoming video data packets• Ancillary (non-video) data packets containing ancillary packets from the vertical blanking period of a

video frame

Anoth

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Video and Image Processing Suite User Guide · 2021. 1. 29. · Video and Image Processing Suite Overview 1 2015.05.04 UG-VIPSUITE Subscribe Send Feedback The Altera® Video and Image