-
8/6/2019 VHDL Lecture Series - II
1/20
VERYHIGH SPEED INTEGRATED CIRCUIT
HARDWARE DESCRIPTION LANGUAGE
LECTURE - II
Presented By :Parag Parandkar
Assistant Professor,
Chameli Devi School of Engg., KhandwaRoad, Indore (M.P.), India
452020
Email: [email protected],[email protected]
Contact: +919826139931
-
8/6/2019 VHDL Lecture Series - II
2/20
ACKNOWLEDGEMENT
The Presenter would like to thank and
acknowledge the power point presentation
slides of VHDL A Comprehensive tutorial
by anonymous.
-
8/6/2019 VHDL Lecture Series - II
3/20
COURSE COVERAGE
Subprogram Function and Procedure
Package
Package declaration and Package
Body Use Clause
Analysis Rule for Units
Objects and Data Types
Scalar Type
Literal
-
8/6/2019 VHDL Lecture Series - II
4/20
SUBPROGRAMS
Subprograms are of two types :
- functions and procedures A subprogram consists of a sequence
of
declarations and statements which can be repeatedfrom different
locations in VHDL descriptions
subprograms can be overloaded
functions can be used for operator overloading
procedures can assign values to its parameter
objects while functions can not A subprogram can be separated
into its
subprogram declaration and subprogram body
-
8/6/2019 VHDL Lecture Series - II
5/20
SUBPROGRAMS (CONTD.)
Full form of subprogram declaration is
subprogram-specification;
Two forms ofsubprogram - specification
procedure identifier interface_list
[pure | impure] function identifier interface_listreturn
type_mark
Full form of subprogram body is
subprogram-specification is
declarations
begin
statements
end identifier;
-
8/6/2019 VHDL Lecture Series - II
6/20
FUNCTIONS
Intended to be used strictly for computing values and not
for changing value of any objects associated with thefunctions
formal parameters
All parameters must be of mode in and classsignalorconstant or
File.
If no mode is specified, the parameter is interpreted ashaving
mode in. If no class is specified parameters areinterpreted as
being of class constant. Parameter of typeFILE has no mode.
Examples of function declaration Object class of parameter is
implicit
function Mod_256 (X : Integer) return Byte;
Object class of parameter is explicit
function Mod_256(constant X : in Integer) return Byte;
-
8/6/2019 VHDL Lecture Series - II
7/20
EXAMPLE
Function declaration
function Min (X, Y : Integer) return Integer;
-- Function Specification
function Min (X, Y : Integer) return Integer is
beginif(X < Y) then
returnX;
elsereturnY;
end if;
end Min;
-
8/6/2019 VHDL Lecture Series - II
8/20
PROCEDURES
Procedures are allowed to change the values of the
objects associated with its formal parameters Parameters of
procedures may of mode in, outorinout
If no mode is specified the parameter is interpreted ashaving
mode in. If no class is specified parameters of
mode in are interpreted as being of class constantandparameters
of mode outorinoutare interpreted as beingof class variable.
Parameter of type FILE has no mode.
Examples of procedure declaration
Object class of parameter is implicitprocedure Mod_256 (X :
inout Integer);
Object class of parameter is explicit
procedure Mod_256(variable X : inout Integer);
-
8/6/2019 VHDL Lecture Series - II
9/20
EXAMPLE
Procedure declaration
--- X is of class variable
Procedure ModTwo (X : inout Integer);
-- Procedure SpecificationProcedure ModTwo (X : inout Integer)
is
begin
case X is
When 0 | 1 => null;
When others X := X mod 2;
end case;
end ModTwo;
-
8/6/2019 VHDL Lecture Series - II
10/20
PACKAGES
Allows data types, subprograms, object
declarations (signal, constants, shared variables andfiles),
component declarations etc. to be sharedby multiple design
units.
package identifier is
declarations
end [package] [identifier];
Example :
package logic is type Three_level_logic is (0, 1, z);
function invert (Input : Three_level_logic) return
Three_level_logic;
end logic;
-
8/6/2019 VHDL Lecture Series - II
11/20
PACKAGE BODY
Package declarations and bodies are separately
described
Package declarations contain public and visibledeclarations
Items declared inside package body is not visibleoutside the
package body
Package body has the same name as thecorresponding package
declaration
package body identifieris
declarations
end [package body] [identifier];
-
8/6/2019 VHDL Lecture Series - II
12/20
PACKAGE BODY (CONTD.)
Example of a package body for package logic
package body logic is
-- subprogram body offunction invert
function invert (Input: Three_level_logic) return
Three_level_logic isbegin
case Input is
when 0 => return 1;
when 1 => return 0;
when Z => return Z;
end invert;
end logic;
-
8/6/2019 VHDL Lecture Series - II
13/20
USE CLAUSE
Use clause preceding an unit makes all the elements of a
package or a particular element of a package visible tothe
unit
An architecture body inherits the use clauses of itsentity. So
if those use clauses are sufficient for the
descriptions inside the architecture, then no explicit useclause
is necessary for the architecture
Simple examples :
Makes all items of package std_logic_1164 in library
ieee visible use ieee.std_logic_1164.all;
Makes Three_level_logic in package Logic in librarywork
visible
use work.Logic.Three_level_logic;
-
8/6/2019 VHDL Lecture Series - II
14/20
USE CLAUSE (CONTD.)
library my_lib;use my_lib.Logic.Three_level_logic;
use my_lib.Logic.Invert;
entity Inverteris
port (X : in Three_level_logic;
Y : out Three_level_logic);
end inverter;
-
8/6/2019 VHDL Lecture Series - II
15/20
ANALYSIS RULES FOR UNITS
Units can be separately analyzed provided following rules
are
obeyed a secondary unit can be analyzed only after its primary
unit is
analyzed
a library unit that references another primrary unit can
beanalyzed only after the referred unit has been analyzed
an entity, architecture, configuration referenced in
aconfiguration declaration must be analyzed before theconfiguration
declaration is analyzed
A library clause makes library visible and an use clause
makes
the units inside the library visible to other units library
Basic_Library;
Use Basic_Library.Logic;
Use Logic.all;
-
8/6/2019 VHDL Lecture Series - II
16/20
OBJECTS AND DATATYPES
Something that can hold a value is an object (e.g signal)
In VHDL, every object has a type, the type determiningthe kind
of value the object can hold
VHDL is strongly typed language
The type of every object and expression can bedetermined
statically. i.e the types are determined prior
to simulation.
Three basic VHDL data types are
integer types
floating point types
enumerated types
Data types can be user defined
-
8/6/2019 VHDL Lecture Series - II
17/20
DATATYPES
Data type
Scalar Type Composite TypeAccess Type File Type
Integer
Float
Physical
Enumeration
Record
Array
Integer and enumeration types are called discrete types
Integer, Real and Physical types are called numeric types
-
8/6/2019 VHDL Lecture Series - II
18/20
DATATYPES(CONTD.)
ScalarType
Most atomic Can be ordered along a single scale
Integer types
type Byte is range -128 to 127;
type Bit_pos is range 7 downto 0;
Floating types
type fraction_type is range 100.1 to 200.1;
Enumerated Types consists of enumeration literal
a literal is either an identifier or a character literal
type Three_Level_Logic is (0, 1, z);
type Color_set is (RED, GREEN, BLUE);
-
8/6/2019 VHDL Lecture Series - II
19/20
DATATYPES : SCALAR TYPE
(CONTD.)
Physical Type
Values of physical type represent measurement of some
physicalquantity such as time, distance etc.
Any value of a physical type is an integral multiple of the
primary unit of measurement for the type
Example
type Time is range -(2**31 -1) to (2**31 -1)
units
fs ; --- primary unit ps = 1000 fs; --- secondary unit
ns = 1000 ps; --- secondary unit
end units;
-
8/6/2019 VHDL Lecture Series - II
20/20
LITERAL
These are symbols whose value is immediately evident
from the symbol Six Literal Types
integer, floating, characters, strings,
bit_string and physical literal;
Examples 2 19878 16#D2# 8#720#
2#1000100
1.9 65971.3333 8#43.6#e+4 43.6E-4
ABC()%
B1100 XFf O70
15 ft 10 ohm 2.3 sec
