vhdl lab

1. Write HDL code to realize all the logic gatesVerilog:

module allgates(i1,i2,o1,o2,o3,o4,o5,o6,o7);

input i1,i2;

output o1,o2,o3,o4,o5,o6,o7;

assign o1=i1 &i2;

assign o2= i1|i2;

assign o3=~(i1 & i2);

assign o4=~(i1 | i2);

assign o5= i1 ^ i2;

assign o6= ~(i1 ^ i2);

assign o7= ~i1;

endmodule

VHDL:

module allgates(i1,i2,o1,o2,o3,o4,o5,o6,o7);

input i1,i2;

output o1,o2,o3,o4,o5,o6,o7;

assign o1=i1 &i2;

assign o2= i1|i2;

assign o3=~(i1 & i2);

assign o4=~(i1 | i2);

assign o5= i1 ^ i2;

assign o6= ~(i1 ^ i2);

assign o7= ~i1;

endmodule

2. Write a HDL program for the following combinational designs:

a] 2 to 4 Decoder

Verilog:

//Behavioral

module dec2to4_df(ebar,a,y);

input ebar;

input[1:0]a;

output[3:0]y;

reg y;

always@(a,ebar)

begin

if(ebar==0)

begin

case(a)

2'd0:y=4'd1;

2'd1:y=4'd2;

2'd2:y=4'd4;

2'd3:y=4'd8;

endcase

end

else

y=4'd0;

end

endmodule

//Dataflow

module dec2to4_df(ebar,a,y);

input ebar;

input[1:0]a;

output[3:0]y;

assign y[0]=(~a[1])&(~a[0])& ebar;

assign y[1]=(~a[1]) & (a[0]) & ebar;

assign y[2]=(a[1])&(~a[0])& ebar;

assign y[3]=(a[1]) &(a[0]) & ebar;

endmodule

//Structural

module dec2to4_structural(ebar,a,y);

input ebar;

input[1:0]a;

output[3:0]y;

wire[3:1] abar; /*abar- not a*/

not(ebar,e);

not(abar(0),a(0));

not(abar(1),a(1));

and(y(0),e,abar(1),abar(0));

and(y(1),e,abar(1),a(0));

and(y(2),e,a(1),abar(0));

and(y(3),e,a(1),a(0));

endmodule

VHDL:

//Behavioral

library ieee;

use ieee.std_logic_1164.all;

entity dec2to4 is

port(a: in std_logic_vector(1 downto 0);

ebar:in std_logic;

y:out std_logic_vector(3 downto 0));

end dec2to4;

architecture dec2to4_behave of dec2to4 is

begin

process(ebar,a)

begin

if(ebar='0')then

case a is

when"00"=>yyyynull;

end case;

else y end if;

end process;

end dec2to4_behave;

//Dataflow

library ieee;


entity dec2to4 is


ebar:in std_logic;


end dec2to4;

architecture dec2to4_df of dec2to4 is

begin

y(0) y(1) y(2) y(3) end dec2to4_df;

//Structural

library ieee;


entity dec2to4 is


ebar:in std_logic;


end dec2to4;

architecture dec2to4_struct of dec2to4 is

component not1

port(x:in std_logic; xbar:out std_logic);

end component;

component and3ip

port(p,q,r:in std_logic; s:out std_logic);

end component;

signal e,abar1,abar0:std_logic;

begin

n1:not1 port map(ebar,e);

n2:not1 port map(a(0),abar0);

n3:not1 port map(a(1),abar1);

a0:and3ip port map(e,abar1,abar0,y(0));

a1:and3ip port map(e,abar1,a(0),y(1));

a2:and3ip port map(e,a(1),abar0,y(2));

a3:and3ip port map(e,a(1),a(0),y(3));

end dec2to4_struct;

library ieee;


entity not1 is

port(x:in std_logic;xbar:out std_logic);

end not1;

architecture notgate of not1 is

begin

xbar end notgate;

library ieee;


entity and3ip is

port(p,q,r:in std_logic;s:out std_logic);

end and3ip;

architecture andgate of and3ip is

begin

send andgate;

b] 8 to 3 Encoder

//Behavoral

module npenc8to3(a,y);

input[7:0] a;

output[2:0]y;

reg[2:0]y;

always@(a)

begin

case(a)

8'd1:y=3'd0;

8'd2:y=3'd1;

8'd4:y=3'd2;

8'd8:y=3'd3;

8'd16:y=3'd4;

8'd32:y=3'd5;

8'd64:y=3'd6;

8'd128:y=3'd7;

default:$display("not a valid input");

endcase

end

endmodule

//Dataflow


input[7:0] a;

output[2:0]y;

assign y[0]=a[1]|a[3]|a[5]|a[7];

assign y[1]=a[2]|a[3]|a[6]|a[7];

assign y[2]=a[4]|a[5]|a[6]|a[7];

endmodule

//Structural


input[7:0] a;

output[2:0]y;

or(y[0],a[1],a[3],a[5],a[7]);

or(y[1],a[2],a[3],a[6],a[7]);

or(y[0],a[4],a[5],a[6],a[7]);

endmodule

VHDL:

//Behavoral

library ieee;


entity npenc8to3 is

port(a:in std_logic_vector(7 downto 0);ebar:in std_logic;


end npenc8to3;

architecture npenc8to3_behave of npenc8to3 is

begin

process(ebar,a)

begin

if ebar='0' then

case a is

when "00000001"=>yyyyyyyyreport"not a valid input"severity note;

end case;

else y end if;

end process;

end npenc8to3_behave ;

<strong>//Dataflow</strong>

library ieee;


entity npenc8to3 is

port(a:in std_logic_vector(7 downto 0);


end npenc8to3;

architecture npenc8to3_df of npenc8to3 is

begin

y(0) y(1) y(2) end npenc8to3_df;

//Structural

library ieee;


entity npenc8to3 is



end npenc8to3;

architecture npenc8to3_struct of npenc8to3 is

component or4ip

port(p,q,r,s:in std_logic;

t:out std_logic);

end component;

begin

or1:or4ip port map(a(1),a(3),a(5),a(7),y(0));



end npenc8to3_struct;

library ieee;


entity or4ip is

port(p,q,r,s:in std_logic;t:out std_logic);

end or4ip;

architecture orgate of or4ip is

begin

t end orgate;

c] 8 to 1 Multiplexer

Verilog:

//Behavoral

module mux8x1 (a,e,s,y);

input[7:0]a;

input[2:0]s;

input e;

output y;

reg y;

always@(a,e,s)

begin

if(e==1)

begin

case(s)

3'd0:y=a[0];

3'd1:y=a[1];

3'd2:y=a[2];

3'd3:y=a[3];

3'd4:y=a[4];

3'd5:y=a[5];

3'd6:y=a[6];

3'd7:y=a[7];

endcase

end

else

y=1'bz;

end

endmodule

//Dataflow

module mux8x1 (a,s,y);

input[7:0]a;

input[2:0]s;

output y;

assign y=(a[0]&(~(s[2]))&(~(s[1]))&(~(s[0])))|

(a[1]&(~(s[2]))&(~(s[1]))&(s[0]))|

(a[2]&(~(s[2]))&(s[1])&(~(s[0])))|

(a[3]&(~(s[2]))&(s[1])&(~(s[0])))|

(a[4]&(s[2])&(~(s[1]))&(~(s[0])))|

(a[5]&(s[2])&(~(s[1]))&(s[0]))|

(a[6]&(s[2])&(s[1])&(~(s[0])))|

(a[7]&(s[2])&(s[1])&(s[0]));

endmodule

//Structural

module mux8x1 (a,s,y);

input[7:0]a;

input[2:0]s;

output y;

wire n0,n1,n2,a0,a1,a2,aa3,a4,a5,a6,a7;

not(n0,s[0]);

not(n1,s[1]);

not(n2,s[2]);

and(a0,n2,n1,n0,a[0]);

and(a1,n2,n1,s[0],a[1]);

and(a2,n2,s[1],n0,a[2]);

and(a3,n2,s[1],s[0],a[3]);

and(a4,s[2],n1,n0,a[4]);

and(a5,s[2],n1,s[0],a[5]);

and(a6,s[2],s[1],n0,a[6]);

and(a7,s[2],s[1],s[0],a[7]);

or(y,a0,a1,a2,a3,a4,a5,a6,a7);

endmodule

VHDL:

//Behavoral

library ieee;


entity mux is

port(i:in std_logic_vector(7 downto 0);

s:in std_logic_vector(2 downto 0);

y:out std_logic);

end mux;

architecture mux_bh of mux is

begin

process(i,s)

variable temp:std_logic;

begin

case(s) is

when "000"=>temp:=i(0);

when "001"=>temp:=i(1);

when "010"=>temp:=i(2);

when "011"=>temp:=i(3);

when "100"=>temp:=i(4);

when "101"=>temp:=i(5);

when "110"=>temp:=i(6);

when "111"=>temp:=i(7);

when others=>temp:='z';

end case;

y end process;

end mux_bh;

//Dataflow

library ieee;


entity mux8x1 is



y:out std_logic);

end mux8x1;

architecture mux8x1_df of mux8x1 is

begin

y (a(1) and(not(s(2))) and(not(s(1))) and s(0)) or

(a(2) and(not(s(2))) and s(1)and s(0)) or

(a(4) and s(2) and(not(s(1))) and(not(s(0)))) or

(a(5) and s(2) and (not(s(1))) and s(0)) or

(a(6) and s(2) and s(1) and(not(s(0)))) or

(a(4) and s(2) and s(1) and s(0));

end mux8x1_df;

//Structural

library ieee;


entity mux8x1 is



y:out std_logic);

end mux8x1;

architecture mux8x1_strt of mux8x1 is

component not1


end component;

component and4ip

port(p,q,r,s:in std_logic; t:out std_logic);

end component;

component or8ip

port(p0,p1,p2,p3,p4,p5,p6,p7:in std_logic;q:out std_logic);

end component;

signal s2bar,s1bar,s0bar,y0,y1,y2,y3,y4,y5,y6,y7:std_logic;

begin

n1:not1 port map(s(2),s2bar);



a0:and4ip port map(s2bar,s1bar,s0bar,a(0),y0);

a1:and4ip port map(s2bar,s1bar,s(0),a(1),y1);

a2:and4ip port map(s2bar,s(1),s0bar,a(2),y2);

a3:and4ip port map(s2bar,s(1),s(0),a(3),y3);

a4:and4ip port map(s(2),s1bar,s(0),a(5),y5);

a5:and4ip port map(s(2),s1bar,s0bar,a(4),y4);

a6:and4ip port map(s(2),s(1),s0bar,a(6),y6);

a7:and4ip port map(s(2),s(1),s(0),a(7),y7);

or8:or8ip port map(y0,y1,y2,y3,y4,y5,y6,y7,y);

end mux8x1_strt;

library ieee;


entity not1 is


end not1;


begin

xbar end notgate;

library ieee;


entity and4ip is

port(p,q,r,s:in std_logic;t:out std_logic);

end and4ip;


begin

t end andgate;

library ieee;


entity or8ip is

port(p0,p1,p2,p3,p4,p5,p6,p7:in std_logic; q:out std_logic);

end or8ip;

architecture orgate of or8ip is

begin

q end orgate;

d] 4 Bit binary to gray converter

Verilog:

//Behavoral

module bin2gray(b,g);

input[3:0]b;

output[3:0]g;

reg g;

always@(b)

begin

case(b)

4'd0:g=4'd0;

4'd1:g=4'd1;

4'd2:g=4'd3;

4'd3:g=4'd2;

4'd4:g=4'd6;

4'd5:g=4'd7;

4'd6:g=4'd5;

4'd7:g=4'd4;

4'd8:g=4'd12;

4'd9:g=4'd13;

4'd10:g=4'd15;

4'd11:g=4'd14;

4'd12:g=4'd10;

4'd13:g=4'd11;

4'd14:g=4'd9;

4'd15:g=4'd8;

endcase

end

endmodule

//Dataflow


input[3:0]b;

output[3:0]g;

assign g[3]=b[3];

assign g[2]=b[3] ^b[2];

assign g[1]=b[2] ^ b[1];

assign g[0]=b[1] ^b[0];

endmodule

//Structural


input[3:0]b;

output[3:0]g;

xor(g[3],b[3],'0');

xor(g[2],b[3],b[2]);

xor(g[1],b[2],b[1]);

xor(g[0],b[1],b[0]);

endmodule

VHDL:

//Behavoral

library ieee;


entity bin2gray is

port(b:in std_logic_vector(3 downto 0);

g:out std_logic_vector(3 downto 0));

end bin2gray;

architecture bin2gray_behave of bin2gray is

begin

process(b)

begin

case(b) is

when "0000"=>ggggggggggggggggnull;

end case;

end process;

end bin2gray_behave;

//Dataflow

library ieee;


entity bin2gray is



end bin2gray;

architecture bin2gray_df of bin2gray is

begin

g(3) g(2) g(1) g(0) end bin2gray_df;

//Structural

library ieee;


entity bin2gray is



end bin2gray;

architecture bin2gray_strt of bin2gray is

component xor2

port(p,q:in std_logic; r:out std_logic);

end component;

begin

x3:xor2 port map(b(3),'0',g(3));

x2:xor2 port map(b(3),b(2),g(2));



end bin2gray_strt;

library ieee;


entity xor2 is

port(p,q:in std_logic;r:out std_logic);

end xor2;

architecture xorgate of xor2 is

begin

r end xorgate;

e] 1 to 4 DeMux

Verilog:

//behavioral

module demux1x4(a,e,s,y);

input s,e;

input[1:0]a;

output[3:0]y;

reg y;

always@(a,e,s)

begin

if(e==1)

begin

case(s)

2'd0:y=a;

2'd1:y=a;

2'd2:y=a;

2'd3:y=a;

endcase

end

end

endmodule

//DataFlow

module demux1x4(a,s,y);

input a;

input[1:0]s;

output[3:0]y;

assign y[0]=a&(~s[1])&(~s[0]);

assign y[1]=a&(~s[1])&(s[0]);

assign y[2]=a&s[1] &(~s[0]);

assign y[0]=a &s[1] &s[0];

endmodule

//Structural

module demux1x4(a,s,y);

input a;

input[1:0]s;

output[3:0]y;

wire n0,n1;

not(n0,s[0]);

and(y[0],n1,n0,a);

and(y[0],n1,s[0],a);

and(y[2],s[1],n0,a);

and(y[3],s[1],s[0],a);

endmodule

VHDL:

//behavioral

library ieee;


entity demux1x4 is

port(a:in std_logic;



end demux1x4;

architecture demux1x4_beh of demux1x4 is

begin

process(a,s)

begin

case s is

when "00"=>y(0)y(1)y(2)y(3)null;

end case;

end process;

end demux1x4_beh;

//DataFlow

library ieee;


entity demux1x4 is




end demux1x4;

architecture demux1x4_df of demux1x4 is

begin

y(0) y(1) y(2) y(3) end demux1x4_df;

//Structural

library ieee;


entity demux1x4 is




end demux1x4;

architecture demux1x4_strt of demux1x4 is

component not1


end component;

component and3ip


end component;

signal s0bar,s1bar:std_logic;

begin



a0:and3ip port map(s1bar,s0bar,a,y(0));

a1:and3ip port map(s1bar,s(0),a,y(1));

a2:and3ip port map(s(1),s0bar,a,y(2));

a3:and3ip port map(s(1),s(0),a,y(3));

end demux1x4_strt;

library ieee;


entity not1 is


end not1;


begin

xbar end notgate;

library ieee;


entity and3ip is


end and3ip;


begin

s end andgate;

3. Write a HDL code to describe the functions of a Full Adder Using three modeling styles.

Verilog:

//Behavoral

module fa_beh(xyz,sum,carry);

input[2:0]xyz;

output sum ,carry;

reg sum,carry;

always@(xyz)

begin

case(xyz)

3'd0:begin

sum=0; carry=0;

end

3'd1:begin

sum=1; carry=0;

end

3'd2:begin

sum=1; carry=0;

end

3'd3:begin

sum=0; carry=1;

end

3'd4:begin

sum=1; carry=0;

end

3'd5:begin

sum=0; carry=1;

end

3'd6:begin

sum=0; carry=1;

end

3'd7:begin

sum=1; carry=1;

end

endcase

end

endmodule

//Dataflow

module fa_data_flow(x,y,cin,sum,carry);

input x,y,cin;

output sum,carry;

wire s1,s2,s3;

assign s1=y^cin;

assign s2=y & cin;

assign sum=x^s1;

assign s3=x &s1;

assign carry=s2|s3;

endmodule

//Structural

module fa_strt(x,y,cin,sum,carry);

input x,y,cin;

output sum,carry;

half_add h1(s1,s2,y,cin);

half_add h2(sum,s3,s1,x);

or(carry,s2,s3);

endmodule

module half_add(o1,o2,i1,i2);

input i1,i2;

output o1,o2;

xor(o1,i1,i2);

and(o2,i1,i2);

endmodule

VHDL:

//Behavoral

library ieee;


entity fa_beh is

port(xyz:in std_logic_vector(2 downto 0);

sum, carry:out std_logic);

end fa_beh;

architecture behave of fa_beh is

begin

process(xyz)

variable temp1,temp2:std_logic;

begin

case xyz is

when "000"=>temp1:'0'; temp2:='0';

when "001"=>temp1:'1'; temp2:='0';

when "010"=>temp1:'1'; temp2:='0';

when "011"=>temp1:'0'; temp2:='1';

when "100"=>temp1:'1'; temp2:='0';

when "101"=>temp1:'0'; temp2:='1';

when "110"=>temp1:'0'; temp2:='1';

when "111"=>temp1:'1'; temp2:='1';

when others=>null;

end case;

sum carry end process;

end behave;

//Dataflow

library ieee;


entity fa is

port(a,b,cin:in std_logic;

s,cout:out std_logic);

end fa;

architecture fa_df of fa is

begin

s cout end fa_df;

//Structural

library ieee;


entity fa_strt is

port(x,y,cin:in std_logic_vector(2 downto 0);

sum, carry:out std_logic);

end fa_strt;

architecture strt of fa_strt is

component half_adder

port(i1,i2:in std_logic;o1,o2:out std_logic);

end component;

for all:half_adder use entity work.bind22(half_add);

for all:or2 use entity work.bind2(or_gate);

signal s1,s2,s3;std_logic;

begin

h1:half_adder port map(y,cin,s1,s2);

h2:half_adder port map(x,s1,sum,s3);

or1:or2 port map(s2,s3,carry);

end strt;

library ieee;

use ieee.std_logic_1164.all

entity bind2 is

port(i1,i2:in std_logic;

o1:out std_logic);

end bind2;

architecture or_gate of bind2 is

begin

o1 end or_gate;

library ieee;


entity bind22 is

port(i1,i2:in std_logic;

o1,o2:out std_logic);

end bind22;

architecture half_add of bind22 is

begin

o1 o2 end half_add;

4. Write a model for 32 bit ALU

Verilog:

module alu32(a,b,opcode,enable,o1);

input[31:0]a,b;

input[2:0]opcode;

input enable;

output[63:32]o1;

reg[63:0]o1;

always@(a,b,opcode,enable)

begin

if(enable==1)

begin

case(opcode)

3'd0:begin

o1[31:0]=a+b;

o1[63:32]=32'd0;

end

3'd1:begin

o1[31:0]=a-b;

o1[63:32]=32'd0;

end

3'd2:begin

o1=a*b;

end

3'd3:begin

o1[31:0]=~a;

o1[63:32]=32'd0;

end

3'd4:begin

o1[31:0]=a&b;

o1[63:32]=32'd0;

end

3'd5:begin

o1[31:0]=a|b;

o1[63:32]=32'd0;

end

3'd6:begin

o1[31:0]=~(a&b);

o1[63:32]=32'd0;

end

3'd7:begin

o1[31:0]=a^b;

o1[63:32]=32'd0;

end

endcase

end

else

$display("alu disabled");

end

endmodule

VHDL:

library ieee;


use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

entity alu32 is

port(a,b:in std_logic_vector(31 downto 0);

opcode:in std_logic_vector(2 downto 0);

enable:in std_logic;

output:out std_logic_vector(63 downto 0));

end alu32;

architecture behavioral of alu32 is

begin

process(enable,opcode,a,b)

begin

if(enable='1')then

case opcode is

when"000"=>output(31 downto 0)output(31 downto 0) output(63 downto

32)'0');

when"010"=>outputoutput(31 downto 0) output(63 downto 32)'0');

when"100"=>output(31 downto 0) output(63 downto 32)'0');




when others=>null;

end case;

else

report"alu disabled";

end if;

end process;

end behavioral;

5. FlipFlops

a]D flip-flop

Verilog:

module dff(d,clk,q,qb);

input d,clk;

output q,qb;

reg temp;

always@(posedge clk)

begin

temp=d;

end

assign q=temp;

assign qb=~temp;

endmodule

VHDL:

library ieee;


entity dff is

port(d,clk:in std_logic;q,qb:out std_logic);

end dff;

architecture dff of dff is

signal temp:std_logic;

begin

process(clk)

begin

if(clk='1' and clk'event)then

temp end if;

end process;

q end dff;

b]JK FlipFlop

Verilog:

module jkff(jk,clk,q,qb);

input[1:0]jk;

input clk;

output q,qb;

reg q,qb;


begin

case(jk)

2'd0:q=q;

2'd1:q=0;

2'd2:q=1;

2'd3:q=~q;

endcase

qb=~q;

end

endmodule

VHDL:

library ieee;


entity jk_ff is

port(jk:in std_logic_vector(1 downto 0);

clk:in std_logic;

q,qbar:out std_logic);

end jk_ff;

architecture jkarch of jk_ff is

begin

process(clk)

variable temp:std_logic;

begin

if rising_edge(clk) then

case(jk) is

when "01"=>temp:='0';

when "10"=>temp:='1';

when "11"=>temp:=not (temp);

when others=>null;

end case;

q qbar end if;

end process;

end jkarch;

c]SR FlipFlop

Verilog:

module srff(sr,clk,q,qb);

input[1:0]sr;

input clk;

output q,qb;

reg q,qb;


begin

case(sr)

2'b00:begin q=q;qb=~q;end

2'b01:begin q=0;qb=1;end



default:begin q=q;qb=qb;end

endcase

end

endmodule

VHDL:

library ieee;




entity sr_ff is

port(sr:in bit_vector(1 downto 0);

clk:in std_logic;

q,qbar:out std_logic);

end sr_ff;

architecture sracrh of sr_ff is

signal clk_div:std_logic_vector(12 downto 0):=(others=>'0');

signal use_clk:std_logic;

begin

p1:process(clk)

begin

if rising_edge(clk)then

clk_div end if;

end process p1;

use_clkqqqqnull;

end case;

end if;

end process;

end sracrh;

d]T FlipFlop

Verilog:

module tff(t,clk,q,qb);

input clk,t;

output q,qb;

reg temp;


begin

temp=~temp;

end

assign q=temp;

assign qb=~temp;

endmodule

VHDL:

library ieee;


entity tff is

port(t:in std_logic;

clk:in std_logic;

q,qb:out std_logic);

end tff;

architecture tff of tff is

begin

process(clk)

variable temp:std_logic:='0';

begin

if(clk='1' and clk'event)then

temp:=not(temp);

end if;

q qb end process;

end tff;

6. n-Bit Counter

VHDL:

library ieee;




entity counter is

generic(n:integer:=4);

port(clk,reset:in std_logic;count:out std_logic_vector(n-1 downto 0));

end counter;

architecture counter_behave of counter is



signal q:std_logic_vector(n-1 downto 0 ):=(others =>'0');

begin

p1:process(clk)

begin


clk_div end if;

end process p1;

use_clk p2:process(use_clk,reset)

begin

if reset='1' then q'0');

elsif falling_edge(use_clk) then

q end if;

end process p2;

count end counter_behave;

7]BCD Counter

VHDL:

library ieee;




entity counter is

port(clk,reset:in std_logic;

count:out std_logic_vector(3 downto 0));

end counter;

architecture counter_behave of counter is



signal q:std_logic_vector(3 downto 0 ):=(others =>'0');

begin

p1:process(clk)

begin


clk_div end if;

end process p1;

use_clk p2:process(use_clk,reset)

begin

if falling_edge(use_clk)then

if reset='1' then q'0'); --synchronous reset

else q end if;

if q="1010" then q end if;

end process p2;

count end counter_behave;

7. Stepper Motor

a] Half Step

VHDL:

library ieee;




entity step_motorhs is

port(clk,rst,dir:in std_logic;

bit_ptrn:out std_logic_vector(3 downto 0));

end step_motorhs;

architecture behavioral of step_motorhs is

type state_type is(hs0,hs1,hs2,hs3,hs4,hs5,hs6,hs7);

signal state_hs:state_type;

signal div_clk:std_logic_vector(12 downto 0):=(others=>'0');

signal speed:std_logic;

begin

p1:process(clk,rst)

begin

if (rst='1') then

div_clk'0');

elsif(clk'event and clk='1')then

div_clk end if;

end process p1;

speed div_clk end if;

end process p1;

speed count end if;

end process;

dac_clk dac_in process(dac_clk,rst)

begin

if rst='1' then

sine_count elsif

dac_clk='1' and dac_clk'event then

if(sine_count=79)then

sine_count else

sine_count end if;

end if;

end process;

with sine_count select

sine_out "10000000" when 0,

"10000000" when 0,

"10000000" when 0,

"10000000" when 0,

"10000000" when 0,

"10000000" when 0,

v

v

"10000000" when 0,

v

"10000000" when 0,

v

"10000000" when 0,

"10000000" when 0,

"10000000" when 0,

"10000000" when 0,

"10000000" when 0,

"10000000" when 0,

"10000000" when 0,

"10000000" when 0,

"10000000" when 0,

"10000000" when 0,

"10000000" when 0,

"10000000" when 0,

"10000000" when 0,

"10000000" when 0,

"10000000" when 0,

"10000000" when 0,

"10000000" when 0,

"10000000" when 0,

"10000000" when 0,

"10000000" when 0,

"10000000" when 0,

b]Square Wave

VHDL:

library ieee;




entity dac1 is

port(clk,rst:in std_logic;

dac_in:out std_logic_vector(7 downto 0));

end dac1;

architecture dac_arch of dac1 is

signal count:std_logic_vector(4 downto 0);

signal dac_clk:std_logic;

signal square_count:integer range 0 to 255;

signal delay_count:integer range 0 to 255;

begin

process(clk,rst)

begin

if rst='1' then

count'0');

elsif

clk='1' and clk'event then

count end if;

end process;

dac_clk dac_in square_count126 else 0;

process(dac_clk,rst)

begin

if rst='1' then

delay_count elsif


delay_count end if;

end process;

end dac_arch;

c]Ramp

VHDL:

library ieee;




entity dac3 is



end dac3;




signal ramp_count:integer range 0 to 255;

begin

process(clk,rst)

begin

if rst='1' then

count'0');

elsif


count end if;

end process;


begin

if rst='1' then

ramp_count elsif


ramp_count end if;

end process;

end dac_arch;

d]Triangular Wave

VHDL:

library ieee;




entity dac4 is



end dac4;




signal trang_count:integer range 0 to 255;

signal ud:std_logic;

begin

process(clk,rst)

begin

if rst='1' then

count'0');

elsif


count end if;

end process;


begin

if rst='1' then

trang_count elsif


if(ud='0') then

trang_count else

trang_count end if;

end if;

end process;

process(dac_clk,rst)

begin

if rst='1' then

ud elsif


if(trang_count=254)then

ud elsif(trang_count=1)then

ud end if;

end if;

end process;

end dac_arch;

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