VHDL Basics and System Design

8/13/2019 VHDL Basics and System Design

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AN 1602 ADVANCED DIGITAL SYSTEM DESIGN

System Design using VHDL

A. Jawahar,Assistant Professor, ECE Dept.

SSN College of EngineeringPhone: 044 32909855 275 (Extn : 359)

91-9444067484 (cellphone)

Email: [email protected]


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REFERENCES:

Donald G. Givone Digital principles and Design Tata McGraw Hill 2002. John M Yarbrough Digital Logic applications and Design Thomson

Learning, 2001 Nripendra N Biswas Logic Design Theory Prentice Hall of India, 2001

Charles H. Roth Jr. Digital System Design using VHDL ThomsonLearning, 1998. Charles H. Roth Jr. Fundamentals of Logic design Thomson Learning,

2004.

Stephen Brown and Zvonk Vranesic Fundamentals of Digital Logic withVHDL Design Tata McGraw Hill, 2002.

Navabi.Z. VHDL Analysis and Modeling of Digital Systems. McGrawInternational, 1998

Parag K Lala, Digital System design using PLD BS Publications, 2003 Peter J Ashendem, The Designers Guide to VHDL Harcourt India Pvt Ltd,

2002 Mark Zwolinski, Digital System Design with VHDL Pearson Education,

2004


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Prerequisite

What you should know:

Minimum: Digital logic circuits, gates, flip-flops, registers,counters, simple logic functions, etc.

Helpful: computer architecture, finite state machinelogic minimization, truth tables, other hardwaredescription languages, etc

Helpful: Programming knowledge, Ada, Pascal, C, etc


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Expectations for Students

What you should learn in this chapter:

Logic design review

Write VHDL models (five design units)

Most of the seven concurrent statements

Most of the thirteen sequential statements

Arrays VHDL operators

Modeling using VHDL


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Terminology

Function - Input to output relationship Timing - Delays representing real digital circuits

Structure (structural)- Description as an interconnection oflower level components (Often represented by a net-list)

Behavior (behavioral) Definition 1 - Function plus timing

Definition 2 - Description as logical or arithmetic operationsversus structure

Definition 3 - High-level operations versus lower-level RTL


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Design Automation Industry

Terminology

DA=Design Automation

EDA = Electronic Design Automation

CAD = Computer Aided Design (often implies layout/routing,one of the earliest design automation tools)

LBD = Language Based Design (mostly VHDL and Verilog, but Cand C++ getting lots of attention)


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Logic Introduction

Logic circuits use two (i.e. binary) values: 0/1, low/high, orfalse/true

Logic functions give outputs based on the values of the inputs(common operators are AND, OR, NOT, NAND, NOR, XOR, XNOR)

Logic element: gate Hardware implementation of function -

Output depends on the current values of the inputs

Logic element: flip-flop or latch - Output depends on thesequence of inputs rather than only the current state.


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Simple Function Truth Tables

A B AND OR XOR NAND NOR XNOR

0 0 0 0 0 1 1 1

0 1 0 1 1 1 0 0

1 0 0 1 1 1 0 0

1 1 1 1 0 0 0 1

A BUF NOT

0 0 1

1 1 0


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Y


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Storage with Latch

S

R

Y

Y

R

Y

Y

SA latch (or flip-flops)

stores one bit (binarydigit)


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Latch with Enable

En

D Y

Y

En

D

Y

Y


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Clocked Flip-Flop

Clock

Data

There is a window of time around the clockactive edge. The window begins at time Tsubefore clock active edge and ends at time Thafterward. If D changes at any time during thesetup- and hold-time window, the output of the

FF is unpredictable (metastable).


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Clk

QD

C

D Q

Latch vs. Flip-flop

QD

EEn

D Q

Latch

Edge-sensitive

Level sensitive

Flip-flop

En

D

Y

Clk

D

Q


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VHDL Design Units

Basic Language Elements


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!"#$% !&$'( ) *

!""+ ,"+ * %* * -,#$.


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VHDL provides five different types of

primary constructs called Design Units. Entity Declaration

Architecture Body

Configuration Declaration Package Declaration

Package Body


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!"#!$%

&!'() (*+, -' .!%%/) (*+0,!"#!$%,


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! " Internal details of an entity are specified

Structural Modeling As a set of interconnected components to represent

structure.

Data Flow Modeling

As as set of concurrent assignments statements torepresent data flow.

Behavioral Modeling

As a set of sequential assignment statements to

represent behavior.


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" # An entity is described as a set of

interconnected components Architecture body composed of two parts

Declarative part

Specify the interface of the components Statement part

Instantiate the declared components


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Appears in declaration part of an architecture body.

Declares the name and interface of a component in a structuraldescription.

Interface specifies the mode and the type of ports.

component-name

may or may not refer to the name of an entity already existing in a library

if it does not exists, it must be explicitly bound to an entity.

list-of-interface-ports

specify the name, mode & type for each port (similar in entity declaration).


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'% (

Represents an entity/architecture pair.

Instantiations of components in architectures is a

method to define hierarchy because architectures ofcomponents can have within them othercomponents.

Defines sub-component of the entity in which it appears.

Associates the signals in the entity with the ports of thatsub-component.

Associates values with generics of that sub-component.

Is equivalent to plugging a hardware component into a

board and making the electrical connections betweenthe pins of the component and the signals of the circuitboard.


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component-label: name of the instance (legal identifier).

component-name: must be the name of the a componentdeclared earlier using a component declaration.

association-list: associates signals in the entity, calledactuals, with the ports of a component, called formals.

actuals

may be a signal, an expression for an input port, the keyword opento indicate a port that is not connected.

formals two ways to perform association of formals with actuals: positional

association and named association.


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Association list of the form:

actual1, actual2, actual3, , actualn

Each actual in the component instantiation is mapped byposition with each port in the component declaration.

---- signal declaration

signal s1, s2, s3;

---- component declaration

component nand2

port (a, b: in std_logic; z: out std_logic);end component;

---- component instantiation

n1: nand2 port map (s1, s2, s3);


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)

Association list of the form:

formal1 =>actual1, , formaln => actualn

Each actual in the component instantiation is mapped byposition with each port in the component declaration.

---- signal declaration

signal s1, s2, s3;

---- component declarationcomponent nand2

port (a, b: in std_logic; z: out std_logic);

end component;

---- component instantiationn1: nand2 port map (a => s1, b => s2, z => s3);


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The types of the formal and actual being associated must be thesame.

The modes of the ports must conform to the rule that if the formal isreadable, so must the actual be, and if the formal is writable, somust the actual be.

Since a locally declared signal is considered to be both readableand writable, such a signal may be associated with a formal of anymode.

If an actual is a port of mode in, it may not be associated with aformal of mode out or inout.

If an actual is a port of mode out, it may not be associated witha formal of mode in or inout.

If an actual is a port of mode inout, it may be associated with aformal of mode in, out or inout.

*


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%

If a port in a component instantiation is notconnected to any signal, the key word open can

be used to signify that the port is not connected.---- signal declaration

signal s1, s2, s3;

---- component declarationcomponent nand2

port (a, b: in std_logic; z: out std_logic);

end component;---- component instantiation

n1: nand2 port map (s1, open, s3);

"


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Declarative Part

Statement Part


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- # Structure of the model is not explicitly

specified, but implicitly deduced.

Concurrent signal assignments are used.

The ordering of the concurrent signalassignments are not important.

Symbol (


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architecture mux2to1_df of mux2to1 isbegin

with s selectz


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' "

library ieee;use ieee.std_logic_1164.all;entity srff is

port (s, r: in std_logic; q: out std_logic);end srff;architecture srff_assert of srff isbegin

assert not (s = 0 and r = 0)report no valid inputsseverity error;

end srff_assert;


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3 # Specifies the behavior of an entity as a set ofstatements that are executed sequentially in thespecified order.

Do not explicitly specify the structure of the entity butits functionality.

The behavior of an entity is expressed using processstatements.

A process statement is itself a concurrent statement that can appear

within an architecture body.

Has sensitivity list and declarative part.

consists of sequential signal assignmentstatements.


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[process-label :] process [(sensitivity-list)] [is]

[process-item-declarations]

begin

process_statement_part ::={sequential-statements}

end process [process-label];

process_item_declarations ::=

subprogram_declaration |

subprogram_body | type_declaration

| subtype_declaration | constant_declaration

| variable_declaration | file_declaration

| attribute_declaration | use_clause


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entity halfadd is


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entity halfadd isport (a, b: in bit; sum, cout: out bit);

end halfadd;architecture halfadd_be of halfadd isbegin

process (a, b)if (a xor b) then

sum


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All three modeling styles are also mixed in a singlearchitecture body.

An architecture body consists of

Component instantiation statements.

Concurrent signal assignment statements.

Process statements

entity full_adder isport (a b cin: in bit; sum cout: out bit);


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y port (a, b, cin: in bit; sum, cout: out bit);end full_adder;

architecture full_adder_mix of full_adder is--- structural model

component xor2port (p, q: in bit; r: out bit);

end component;signal s1: bit;beginx1: xor2 port map (a, b, s1);

--- data flow modelsum


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A configuration declaration is used

to select one of the possibly manyarchitectures bodies that an entity has

to bind components, which are used torepresent structure in that architecturebody, to entities represented by an entity-architecture pair or by a configuration,which reside in a design library.

'


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#' #,# #

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Used to store frequently used declarations such ascomponents, types, procedures and subprograms

(procedures and functions). Declarations can then be imported into other designunits using a use clause.

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2


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All items in the package declarative part are visibleto any package body that uses the packagedeclaration.

Possible to selectively import declarations from apackage declaration into other design units.

Items declared in a package are immediatelyvisible to all subsequent declarations in the samepackage.

The items in a package declaration and packagebody are visible to any other design unit which hasbeen given explicit access through a use clause.

2


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Stores the definitions of functions and procedures that were declared in thecorresponding package declarations and also the complete constantdeclarations.

A package body canot exist without package declaration. A package declaration can have atmost one package body associated withit.

Package body is not necessary if the corresponding package declarationshas no function or procedure declarations and no deferred constantdeclarations.

The identifier is the same as the identifier in the package declaration.

package_body ::=package body identifier is

package_body_declarative_part;

end [package body] [identifier];

.&&/ #%$

0


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&

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+&&/ #%$library ieee;


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use ieee.std_logic_1164.all;

entity mux2to1 is

port (a, b, s: in std_logic;z: out std_logic);

end mux2to1;

architecture mux of mux2to1 is

begin

with s select

z


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Fundamental structures of the language

P Identifiers, Delimiters, LiteralsP Data Objects (Constants, Variables,

Signals, Files)

P Data Types and Its subtypes

P Operators

"$

The pattern or structure of the word order in a


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The pattern or structure of the word order in aphrase.

Refers to rules for statements spelled out in theLRM (Language Reference Manual) andverified by a VHDL analyzer or compiler.

Latitude in the rules allows a programmer the

choice of syntax for particular programstatements that reflects his style.

This can cause significant variations in style

and can affect the overall readability of aprogram.

(

The names that identify various objects procedures


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The names that identify various objects, procedures,functions, processes, etc.

Two kinds of identifiers

P Basic Identifiers

P Extended Identifiers.

": " #

) #J' B##7

) *' :##7' ##' T

(

Composed of a sequence of one or more characters.


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Composed of a sequence of one or more characters. Can only contain letters, numbers and underscores. Can be of any length as long as the entire identifier appears within a

line. No distinction between upper & lower case letters. Cannot have the same name as a keyword. Must begin with a letter. Cannot have underscore at the beginning, end or side by side.

Underscores are significant. No special characters allowed. No space is allowed since it is a separator.

$

A sequence of characters written between two


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A sequence of characters written between twobackslashes.

Used to integrate VHDL code with other tools which

use extended identifiers. Case sensitive and special characters like ., !, @,>,

and $ can also be used.e.g. legal identifiers: /TEST/, /Q@BCD/

illegal identifiers: /TeSt/, Abc@Def. Avoid the use of extended identifiers because

P They reduce the readability

P They cause errors since they are case sensitive.

(

Port names should not exceed 16 characters


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Port names should not exceed 16 charactersincluding size of array - Tool specific requirement.

Port names should be same as name of theconnecting signal in next level architectures and mustbe same as port names in other connecting entities.

For large designs, port names should identify theorigin of the design partition.

Port names should identify polarity of signals. Port names may identify a registered or delayed

version of an original, non delayed signal.

'%

Lower case should be used for all VHDL


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reserved words and VHDL attributedefinitions.

Mixed case should be used for all otheridentifiers, with consistent casing in all code.

User defined key words should not depend

on capitalization to be readable ormeaningful.

When user identifiers are in mixed or

uppercase, they stand out.

Delimiters are the symbols that have special meaning withinVHDL


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VHDL.

These symbols are used as operators and statement terminators.

There are single delimiters (only one symbol) and double

delimiters (two symbols). No spacing is allowed before or after the following delimiters

P The sharp # -- 16#E45F#

P The period . -- data.enable

P The single quote> -- clk>event (bus`transaction) Bit literals must be bracketed with double quotes with no spaces

inside the quotes

Avoid using spacing before the following delimiters:

P Semicolon ;


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P Semicolon ;

P Colon : --- after a label only, use spacing elsewhere

P Parenthesis ( ) --- may be started on a continuation line

For all other delimiters, use one or more spacing before and afterusing the delimiter.

P These rules enhance code readability.

P The semicolon is a terminator and needs no separator.P The colon after a label can be thought of as part of the label.

Long lines are more readable when elements embraced in

parenthesis are started on a new continuation line.

A value, directly specified in the description of a design.


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Types

P decimal literals

P based literalsP character literals

P string literals

P bit string literals.

Use underscores for numerical literals to enhance readability


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'

A letter of character type


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A letter of character type.

Formed by enclosing one of thegraphics characters between twoapostrophe () characters.

Eg. A, *

"

A sequence of graphics characters or possibly none,l d b i k ( )


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enclosed between quotation marks ().

Its type is determined from the context

This is a string A string must fit on one line

Longer sequences can be obtained by concatenationof string literals.

First part of a sequence of characters thatcontinues on next line --- one string literal

"

"


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Formed by a sequence of extended digits enclosed between twoquotations and preceded by a base specifier.

Its type is determined from the context. Its length is the length of its string literal value.

An underscore character inserted between adjacent characterdigits of a bit does not affect the value of this literal

* %0 > > 0?9@ A( 0 ? BC ? *

04

A data object holds a value of a specified type.


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j p yp

Created by means of an object declaration

variable COUNT:INTEGER; Every data object belongs to one of the

following four classes.

Constant

Signal

variable

File

'

An object whose value may not change, i.e. constants are used tohold a static value.


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Value is assigned to the constant before simulation starts andthe value cannot be changed during the course of the

simulation.

For a constant declared within a subprogram, the value isassigned to the constant every time the subprogram is called.

Play very important role in VHDL because they create more

readable and maintainable code.

Use constants to define data parameters and table lookups.

'

"


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(

my_process: process (rst, clk)constant amount: std_logic_vector (3 downto 0) =

0000;

begin

wait until clk = 1;if (rst = 1) then q


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M # ; 5: #) )= 5:, M # ; 5: ## ) , ;

6 ; 6

" Most commonly used data objects in synthesis designs

All basic designs and many large designs can be fully described usingsignals as the only kind of data object.

Signals have projected output waveforms


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Signals have projected output waveforms.

Signal assignment are scheduled, not immediate.

They update projected waveforms.

# #

5' 3' 7) #,

!) D7 &' ' #' 0,

!) 3 &' ' 50,

1) 3 &' #' 30,

!) 3 &' #' 70,

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#,

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A signal is defined in The declarative part of a package.

The declarative part of an architecture


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The declarative part of an architecture.

The declarative part of a block.

The formal parameters of a subprogram. A signal has three properties attached to it, including:

Type and type attributes

Type insures consistency in operations on objects

Attribute defines characteristics of objects. Value - Includes current, future and past value.

Time - Represents a time associated with each value.

Future values can be assigned to a signal using a signalassignment statement.

"

6) , M 6


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M ; ; >:?

#) )= 5: , M #

; ; 5:) ##; &7 :0 )=

& : =A >5?'=A >?0, 9

##; ; ; : ; >?

0

A variable is defined in The declarative part of a process.

The declarative part of a subprogram.


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p p g

A variable is also defined as a shared variable in

The declarative part of a package. The declarative part of an architecture.

A signal has two properties attached to it, including:

Type and type attributes

Like signal properties but no attributes associated with time.

Value - No time history.

Different values can be assigned to the variable at different timesusing variable assignment statement.

0

*) #; &9 :0, ; M


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M #; J

*) : 5:: )=5:, ; M

; ; 5: * ; ' ; ;

" ! 0

Use signals as channels ofcommunication between concurrent


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communication between concurrent

statements (e.g. components, processes). To describe storage elements , usevariables instead.

Signals occupy storage two time asvariables do during simulation.

An object belonging to a file class, contains a sequence of values. Values can be read or written to the file using read procedures

and write procedures, respectively.


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a d te p ocedu es, espect e y

Used to represent objects in files in the host environment.

(

string-expression:= Interpreted by the host environment as thephysical name of the file.

mode:= Specifies whether the file is to be used as read-only or write-only or in the append mode.

$ $


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(


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VHDL has a set of predefined types in the std_package.e.g. type bit is (0, 1);

type Boolean is (true, false);type integer is range defined

The language also provides the facility to define new types by using type

declarations

define a set of operations on these types by writing functionsthat return values of this new type.

5%

Four categories.

Scalar types

Values belonging to these types appear in a sequential order


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Values belonging to these types appear in a sequential order.

Composite types

These are composed of elements of single type (an arraytype) or elements of different type (a record type).

Access types

These provide access to objects of given types (via

parameters). File types

These provide access to objects that contain a sequence ofvalues of a given type.

" %

Values belonging to these objects areordered i e relational operators can be


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ordered, i.e. relational operators can be

used on these values. Four kinds

Enumeration

Integer

Floating point.

Physical

" %

Enumeration Types Defines a type that has a set of user-defined values

consisting of identifiers and character literals


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type new is (U, 0, 1, Z);

-- new is enumeration type that has a set of ordered values U,0, 1 and Z

Integer Types

Defines a type whose set of values fall within a specifiedinteger range

type new is range 0 to 15;

-- new is integer type that includes integer values from 0 to 15

" %

Floating Point Types Have a set of values in a given range of real numbers

variable new is real_data range -1.0 to 14;


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-- new is a variable of object type real_data whose values will be

real values from -1.0 to 14 Physical Types

Contain the values to represent the measurement of somephysical quantity (time, length, voltage or current).

These type values are expressed as integer multiples of abase unit.

type current is range 0 to 1E9;

units

nA; -- base unit.

uA = 1000nA;

mA = 1000uA;

Amps = 1000mA;

end units;

'% %

Represent a collection of values

Tow types:


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Array types

Record types

Array types Represent a collection values all belonging to a

single typetype address_bus is array (0 to 63) of bit;

-- address_bus is a one-dimensional array object thatconsists of 64 elements of type bit.

'% %

Record types Represent a collection values that may belong to different

types


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Analogous to the record data type in PASCAL and the struct

declaration in C.

: 5:,

B ) 3: 5::,# ) ,*# ) ,# ) ,

,

%

Values belonging to access types arepointers to dynamically allocated some other


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type.

Analogous to the pointers in PASCAL and C.

type new is access module;

-- new is an access type whose values areaddresses that point to objects of typemodule.

%

Represent files in the host environment.

Provide mechanism by which a VHDL design


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communicates with the host environment.

,)= + ;

; ;,

; 8

; #;

"0%

Subtype is a type with a constraint, which specifies thesubset of values for the subtype.

The type is called base type of the subtype. The set of


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The type is called base type of the subtype. The set ofoperations belonging to a subtype is the same as thatassociated with its base type.

An object is said to belong to to a subtype if it is of thebase type and if satisfies constraints.

Subtype declarations are used to declare subtypes. Subtypes are useful for range checking and for imposing

additional constraints on types.

%

Logical operators

Relational operators


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p

Shift operators Adding operators

Multiplying operators Miscellaneous Operators

%

Operators: not , and , or , nand , nor , xor , xnor

P Used frequently to generate Boolean equations.

P Predefined types bit and Boolean


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Predefined types bit and Boolean.

P Are also defined for one dimensional arrays of bit and Boolean. During evaluation, bit values >0?and >1?are treated as HfalseIand

HtrueIvalues of the Boolean type respectively.

The result of a logical operation has the same type as its operands.

The not operator is a unary operator and has same precedence asthat of miscellaneous operators.

% nand and nor operators are not associative

The syntax of an expression with a sequence of nandand nor operators is illegal


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and nor operators is illegal.

' ' ' ) #, @= ,

Parenthesis can be used to avoid this problem

d =

U d f l f i


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P Used frequently for comparisons.

P = (equality) and /= (inequality) operators arepredefined for any type except file type.

P The remaining four operators are predefined on

scalar type or discrete array type. When operands are discrete array type, comparisonis performed one element at a time from left to right.

bit_vector (0, 1, 1) < bit_vector (1, 1, 1)

" %

Operators: sll , srl , sla , sra , rol , ror

P Used occasionally.

Each of the operator takes an array of bit or Boolean as


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Each of the operator takes an array of bit or Boolean as

the left operand and an integer value as the rightoperand and performs the specified operation.

If the integer value is negative number, the oppositeaction is performed.

(i.e. left shift or rotate => right shift or rotate)

%

Operators: + , - , & Used frequently to describe increments, decrements,

adders and subtractors.

+ (addition) and - (subtraction) operators


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+ (addition) and - (subtraction) operators

The operands must be of same numeric type and the result isalso same numeric type.

Also used as unary operators, where the operand and result isalso same type.

& (concatenation) operator

The operands can be either a one dimensional array type or anelement type. The result is always an array type.

0 & 1 - results in an array of characters 01

#% %

F > The * (multiplication) and / (division) operators

They are predefined for both operands being of same integer or floatingpoint type. The result is of the same type.

* operator is also defined for the case when one of the operands isphysical type and second operand is of integer or real type.


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p y yp p g yp

For / operator,

The division of a value of physical type by either an integer or realvalue is allowed and the result type is physical type.

The division of a value of physical type by another object of thesame physical type is also defined and the result type is integertype.

*' ) : 3JJ,

@= R 3,

#% %

The rem (remainder) and mod (modulus)operators operate on operands of integer typesand the result is also of the same type


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and the result is also of the same type.

The result of rem operation has the sign of itsfirst operand.

= &O0 R ,E 9 ; 7&E0 9 ; 7

" %

Operators: + , -

Rarely used for synthesis.


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Predefined for any numeric type(floating-point or integer)

*' ) : 3JJ,

@= & L 30,

# %

Operators: ** , abs

The abs (absolute) operator, defined for numerictype


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type.

the ** (exponentiation) operator is defined for theleft operand to be of integer or floating point typeand for the right operand (i.e. the exponent) to be

of integer type only. The not logical operator has the same

precedence as above two operators.

' "' "

*1*1

Code must abide by the VHDL language rules.

Code should have a common look and feel


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Code should have a common look and feel.

Code should be easily readable andmaintainable.

Code must yield expected results

Simulatable code should be efficient from asimulation viewpoint.

Synthesizable code must abide to vendors

synthesis rules.

Thank You


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Any Queries ?

Please [email protected]

Documents

VHDL Basics and System Design