1394 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-27, NO. 8, AUGUST 1980

tor layouts of a CML gate designed in the two methods. In this figure, the PSA transistors are delineated by the 3 - ~ m design rule, while the dimensions of the APSA transistors are those of the newly developed technology. The areas occupied by the transistors are about 1500 pmZ in bothmethods. Consequently, the packing density of the APSA LSI’s will be comparable with that of the PSA LSI’s composed of the down-scaled transistors.

VI. CONCLUSION A bipolar LSI technology called the APSA method has

realized small-size transistors for high performance. In partic- ular, the overlapping structure for the double polysilicon elec- trodes narrows the width of the emitter window and the spac- ing from the edge of the emitter area to the base electrode. As a result, a smaller base resistance is obtained. Another signifi- cant characteristic for this method is the control to form a shallow base junction. This approach has easily brought a higher fr. By these technological developments, a CML cir- cuit composed of the APSA transistor with 1 pm X 3 pm emit- ter area displays a minimum propagation delay time of 0.29 ns/gate with power of 1.48 mW/gate. This higher transistor performance is achleved while retaining the advantages of the PSA method for LSI fabrication. Furthermore, through the

miniaturized transistor, the APSA method is shown to be able to realize higher packing density LSI’s than the conventional PSA method.

ACKNOWLEDGMENT

The authors would like to thank Y. Matsukura, H. Sasaki, and T. Okada for their encouragement.

REFERENCES

D. Peltzer and B. Herndon, “Isolation method shrinks bipolar cells for fast, dense memories,” Electronics, pp. 52-55, Mar. 1, 1971. T. Sakai et al., “A loops bipolar logic,”inISSCCDig. Tech. Papers, pp. 196-197,Feb. 1975. K. Okada et al.. “A 4K static biuolar TTL RAM.” in ISSCC Din. Tech. Papers, pp. 100-101, Feb. i978. T. Takahashi et al., “A high speed 1600-gate bipolar LSI processor,” in ISSCCDig. Tech. Papers, pp. 208-209, Feb. 1978. K. Okada et al., “A new polysilicon process for a bipolar device- PSA technology,” IEEE Trans. Electron Devices, vol. ED-26, pp.

K. Kimura et al . , “A low-power frequency divider with a new swal- lowing technique for FM receiver,” IEEE Trans. Consumer Elec- tron., vol. CE-25, pp. 636-641, Aug. 1979. K. Aomura, “A new transistor for high speed bipolar IC,” in ESSDERC Tech. Dig., p. 78, Sept. 1979. I. Ishida et al., “An advanced PSA process for high speed bipolar VLSI,” in 1979 Int. Electron. Devices Meet., Dig. Tech. Papers (Washington, DC), pp. 336-339.

385-389, Apr. 1979.

Vertical p-n-p for Complementary Bipolar Technology

INGRID E. MAGDO

Abstract-A process to fabricate high-performance vertical p-n-p devices has been developed. The use of a high-dose boron-implanted poly-Si layer to form the emitter is essential to obtain shallow emitters with high emitter gradient. The devices exhibit very high current gain (>200) and a calculated cutoff frequency of 3.6 GHz. The process as developed is compatible with the n-p-n process and, thus, suitable for fabrication of complementary bipolar devices.

Manuscript received January 21, 1980; revised March 28, 1980. The author is with the Data Systems Division, IBM Corporation,

East Fishkill, NY 12533.

T INTRODUCTION

HE TREND in the semiconductor industry is to achieve high circuit density and high performance. In general, the

limits on density and performance are dictated by thermal considerations. For VLSI applications, it is desirable to reduce the power-delay product. This can be accomplished by using complementary bipolar technology.

Complementary bipolar circuits were not utilized because the quality of the p-n-p devices was poor cfT 3: 500 MHz). In this paper we describe the processing and characterization

0018-9383/80/0800-1394$00.75 0 1980 IEEE

MAGDO: VERTICAL pn-p FOR COMPLEMENTARY BIPOLAR TECHNOLOGY 1395

of hgh-performance p-n-p devices. The use of boron-im- planted poly-Si is essential to form the highly doped emitter region because the Si remains defect free, and very shallow junctions can be obtained. Shallow junctions are desired because high-performance devices utdize thin epitaxial layers and shallow junctions to increase device performance.

STRUCTURE AND PROCESSING

For high-performance p-n-p devices, it is essential to obtain shallow high-concentration steep emitters with accurate junc- tion depth control. First, simple structure devices were built using p substrate as a subcollector. Then, after patterning for the base, phosphorus was implanted through an 80-nm Si02 layer. After annealing, Si3N4 was deposited, and all contacts were defined. The emitter and collector windows were opened. Two approaches were pursued in forming the emitter.

A. High-Dose Boron Implant Directly into Si Substrate

A high dose (5 X 1015 and 1 X 1016/cm2) of boron at an energy of 40 keV was implanted into bare Si. The wafer was capped with 100-nm CVD-Si02 and annealed at 970°C for 30 min. Transmission electron microscope (TEM) specimens were prepared to examine possible residual defects associated with high-dose implant. The depth distribution of the defects was revealed by a chemical sectioning technique where elec- tron-transparent foils were made after removing layers of various thcknesses from the implanted surface [l] . We ob- served that a very high density of dislocation loops exists 50 nm below the implanted surface. With increasing depth, these loops coagulate into very dense tangles of dislocations to a depth of -200 nm. The next region extending -500 nm from the surface revealed high density of stacking faults. These stacking faults are located in a volume that had not been im- planted, but doped by boron drive-in diffusion. Devices fabri- cated with this process displayed a large number of emitter- to-collector shorts. Fig. 1 shows typical profiles of devices processed in this manner.

B. High-Dose Boron Implant into Poly-Si Layer

The thickness of the poly-Si layer was 250 nm, deposited in the low-pressure CVD system at 625°C. Boron was implanted at 40 keV and at aldose of 1 X 1016/cm2, followed by 100- nm CVD-pyrolytic Si02 deposition. The drive-in cycle was the same as in the bare-Si implant case at 970°C for 30 min in argon. The CVD-pyrolitic SiOz was patterned using a standard photoresist technique, and the poly-Si was reactive-ion etched.

The thickness of the poly-Si layer was larger than that of the defect layer centered around the projected range. Although the tail of the boron implant did penetrate the single-crystal silicon, nevertheless, no defects were found in the single crys- tal. In comparison with monocrystalline silicon, the poly-Si consisted almost entirely of stacking faults. However, this sort of damage did not propagate into the single-crystal wafer, in contrast to the direct implant case. Devices fabricated with the poly-Si-implanted emitters displayed no emitter-collector shorts, and we measured current gains between 200 and 300.

thickness [nml

Fig. 1. p n - p device profile with high-dose boron implanted into bare Si.

P- substrate

Fig. 2. Cross-sectional view of a typical n-p-n device.

100 300 500 700 900 1100

thickness [nm]

Fig. 3. Typical n-p-n device profile. Dashed line indicates the out- diffused isolation profile.

Furthermore, the objective in the development was to be able to integrate the p-n-p devices with n-p-n devices. The author has chosen the 2-pm epitaxial technology, shown in Fig. 2, and which is now briefly outlined. On p-oxidized sub- strate, windows are opened and we diffuse As, which forms the subcollector region. Next, boron is diffused in selected areas which serves as part of the isolation region. An expitaxial layer 2 pm thick, n-doped, is deposited, and the recessed oxide isolation (ROI) region is formed [2]. Next, the base is either diffused or implanted, and a layer of Si3N4 is deposited and contacts are defined. Finally, the emitter window is opened and As is either diffused or implanted. Subsequently, the other contacts are opened. The resulting p-n-p device profile is shown in Fig. 3, together with a dashed line indicating the isolation diffusion profile. As can be seen, the isolation profile can be used for the p-n-p subcollector in order t o simplify the processing, as long as the p-n-p structure can be made shallow. The use of boron-implanted poly-Si permits the shal- low-emitter structure without damage anneal because the underlying single crystal is defect free. The only heat cycle needed is the diffusion from the poly-Si layer into the silicon. By this method, a very shallow emitter-base junction (- 100 nm) is obtained.

1396 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-27, NO. 8, AUGUST 1980

100 300 500 700 900 1100

thickness [nml

Fig. 4. p-n-p device profile with poly-Si emitter.

”B + doped polySi

I

P-

Fig. 5. Cross-sectional view of a p-n-p device.

After the epitaxial layer deposition, and the ROI formation, the n-p-n device base is formed. Next, the base of the p-n-p device is implanted with phosphorus through 80 nm of oxide at 70-keV energy and a dose of 2 X 1014/cm2. The n-p-n emitter heat cycle (lOOO”C, 130 min) activates and drives in the p-n-p base. A thin (-25-nm) oxide is thermally grown in the n’-contact windows and the p-n-p emitter window is opened. A layer of 250-nm-thick low-pressure CVD-poly-Si is deposited and implanted with boron at an energy of 40 keV and a dose of 1 X 1016/cm2. The poly-Si layer is capped with -100-nm pyrolitic Si02 and drive-in follows at 1000°C for 30 min. The pyrolitic SiOz is patterned, and the poly-Si is etched. This drive-in cycle results in an emitter-base-junction depth of 250 nm from the single-crystal surface. The emitter, base, and collector profile of the p-n-p device is shown in Fig. 4, and the device cross section is shown in Fig. 5. Note that the junction depths of the p-n-p devices are comparable to the n-p-n devices if the surface of the poly-Si is taken as the origin. Comparing the n-p-n and p-n-p emitters, one observes a higher emitter gradient for the boron emitters than for arsenic emitters.

ELECTRICAL CHARACTERIZATION The devices fabricated with the profile shown in Fig. 4 had

an intrinsic base sheet resistance of 4 kfL/n. Fig. 6 shows the current gain (0) as a function of collector current (Zc) for both a 100-pm X 127-pm and a 3-pm X 7-pm emitter transistors. Table I summarizes the other parameters of these devices.

A device model based on measured parameters and profiles was generated and used in formulating an ASTAP [3] model. From this model, one can calculate the cutoff frequency f~ of the transistor. At the operating point, VcE = -2 V and

100 x 120pm 300- X-%

2:- --\ 3 x 7pm

BVEBO (lopa) = 5.4V BVCBO (lopa) = 28V BVCES (lopa) =28V BVCEO (10pa)=5.8V -

10pa 100pa l m a 10mA -Ic

Fig. 6. Current gain of p-n-p devices and typical device characteristics.

TABLE I DEVICE PARAMETERS

BVCBO at 10 pA = 18 V BVCES at 10 pA = 18 V BVEBO at 10 pA = 5.4 V BVCEO at 10 pA = 5.8 V

Zc = 600 pA, the calculated value offT was approximately 3.6 GHz.

CONCLUSIONS We have shown that high-performance p-n-p devices, with a

calculated fT of 3.6 GHz, can be fabricated in shallow (2-pm) epitaxial layer technology. The key to the fabrication is the use of a poly-Si layer withm which a high dose of boron is implanted and where implantation damage is located. The poly-Si thus serves as a doping source for the single-crystal beneath, which remains defect-free, and shallow junctions are realized. Devices with excellent 0 (E200) and other dc charac- teristics were obtained without changing the n-p-n device characteristics.

ACKNOWLEDGMENT The author wishes to thank Dr. S. Mader who carried out the

TEM analysis. She also gratefully acknowledges L. Kando for carrying out the experiment, E. Gorey for the spreading resis- tance measurements, and S. Weitzel, H. Bhatia, S. Gaur, and H. C. Hammel for modeling work. Appreciation is extended to Dr. S. Abbas for his encouragement in writing this paper.

REFERENCES S. Mader and I. Magdo, “Residual defects after annealing of boron implanted Si,” presented at the Ion Beam Conf., IBM, Yorktown Heights, NY, 1977. I. Magdo and A. Bohg, “Framed recessed oxide scheme for disloca- tion-free planar Si structures,” J. Electrochem. Soc., vol. 125, no. 6 , June 1978. ASTAP Users Manual, FH20-1118, IBM, Mechanicsburg, PA.