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8/10/2019 verilog Q & A
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8/10/2019 verilog Q & A
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Q#3. Given the following snipet of Verilog code,
draw out the waveforms for clk and a
always @(clk) begin
a = 0;#5 a = 1;
end
A:
10 30 50 70 90 110 130___ ___ ___ ___ ___ ___ ___
clk ___| |___| |___| |___| |___| |___| |___| |___
a
___________________________________________________________
This obviously is not what we wanted, so to get closer, you
could use"always @ (posedge clk)" instead, and you'd get
10 30 50 70 90 110 130___ ___ ___ ___ ___ ___ ___
clk ___| |___| |___| |___| |___| |___| |___| |___
___ ___a _______________________| |___________________|
|_______
Q#4. What is the difference between the following two lines of
Verilog code?
#5 a = b;a = #5 b;
A:
#5 a = b;Wait five time units before doing the action for "a =
b;".The value assigned to awill be the value ofb5 time units
hence.
a = #5 b;The value ofbis calculated and stored in an internal
tempregister.
After five time units, assign this stored value to a.
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8/10/2019 verilog Q & A
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Q#5. What is the difference between:
c = foo ? a : b; and if (foo) c = a; else c = b;
A:
The ? merges answers if the condition is "x", so for instance if
foo = 1'bx,a = 'b10, and b = 'b11,you'd get c = 'b1x.
On the other hand, iftreats Xs or Zs as FALSE, so you'd always
get c = b.
Q#6. Using the given, draw the waveforms for the following
versions of a (each version is separate, i.e. not in the same
run):
reg clk;reg a;
always #10 clk = ~clk;
(1) always @(clk) a = #5 clk;(2) always @(clk) a = #10 clk;(3)
always @(clk) a = #15 clk;
Now, change a towire, and draw for:
(4) assign #5 a = clk;(5) assign #10 a = clk;(6) assign #15 a =
clk;
A:
10 30 50 70 90 110 130___ ___ ___ ___ ___ ___ ___
clk ___| |___| |___| |___| |___| |___| |___| |___
___ ___ ___ ___ ___ ___ ___(1)a ____| |___| |___| |___| |___|
|___| |___| |_
___ ___ ___ ___ ___ ___ ___
(2)a ______| |___| |___| |___| |___| |___| |___|
(3)a
__________________________________________________________
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8/10/2019 verilog Q & A
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Since the #delay cancels future events when it activates, any
delayover the actual 1/2 period time of the clk flatlines...
With changing a to awireand using assign, wejust accomplish the
same thing...
10 30 50 70 90 110 130___ ___ ___ ___ ___ ___ ___
clk ___| |___| |___| |___| |___| |___| |___| |___
___ ___ ___ ___ ___ ___ ___(4)a ____| |___| |___| |___| |___|
|___| |___| |_
___ ___ ___ ___ ___ ___ ___(5)a ______| |___| |___| |___| |___|
|___| |___|
(6)a
__________________________________________________________
Q#7. Explain the differences between "Direct Mapped", "Fully
Associative",
and "Set Associative" caches.
If each block has only one place it can appear in the cache, the
cacheis said to be direct mapped. The mapping is usually
(block-frame address)modulo (number of blocks in cache).
If a block can be placed anywhere in the cache, the cache is
said to befully associative.
If a block can be placed in a restricted set of places in the
cache, thecacheis said to be set associative. A setis a group of
two or moreblocks in the cache. A block is first mapped onto a set,
and then the blockcan be placed anywhere within the set. The set is
usually chosen by bitselection; that is, (block-frame address)
modulo (number of setsin cache).If there are nblocks in a set, the
cache placement is
called n-way set associative.
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8/10/2019 verilog Q & A
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Q#7. Draw the state diagram to output a "1" for one cycleif the
sequence "0110" shows up (the leading 0s cannot beused in more than
one sequence).
Basically, you can tie the inputs of a NAND gate together to get
an inverter,so write the coding in verilog
