# Verilog Lab Programs

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VERILOG LAB PROGRAMS

And gate: Module andgate(A,B,Y); Input A,B; Output Y; Assign Y=A&B; EndModule OR GATE: Module orgate(A,B,Y); Input A,B; Output Y; Assign Y=A|B; EndModule NOT GATE: Module Notgate(x,y); Input x; Output y; Assign y=~x; EndModule XOR GATE: Module XORGATE(A,B,Y); Input A,B; Output Y;

Assign Y=A^B; EndModule

NAND GATE: Module nandgate(A,B,Y); Input A,B; Output Y; Assign Y=~(A&B); EndModule NOR GATE: Module norgate(A,B,Y); Input A,B; Output Y; Assign Y=~(A|B); EndModule X-NOR GATE: Module XNORgate(A,B,Y); Input A,B; Output Y; Assign Y=~(A^B); EndModule

ADDER AND SUBTRACTORS: Half Adder: Module halfadder(A,B,SUM,CARRY); Input A,B; Output SUM,Carry; Assign SUM=A^B; Assign CARRY=A&B; Endmodule Full adder: Module fulladder(A,B,CIN,S,COUT); Input A,B,CIN; Output S,COUT; Assign S=(A^b)^CIN; Assign COUT=((A&b)|(A&CIN)|(B&CIN); Endmodule Half subtractor: Module halfsubtractor(A,B,diff,borrow); Input A,B; Output diff,borrow; Assign diff=A^B; Assign borrow=(~A)&B; Endmodule

Full subtractor: Module fullsubtractor(A,B,C,S,d,b); Input A,B,C; Output d,b; Assign d=(A^b)^C; Assign b=((B&C)|(~A)&C|~(A)&B); Endmodule Flip Flops: D-Flip Flops Module diff_br(clk,reset,D,Q); Input clk,reset,D; Output Q; Reg Q; Always @(POSEDGE clk or POSEDGE reset) Begin If(reset) Q

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