Verilog_ Finite State Machines

Verilog For Finite state machines

O tliOutlineThree Verilog code styles for FSMsThree Verilog code styles for FSMsVerilog codes for Moore and MealyTwo examplesTwo examples

Sequence detectorControl circuit for swapping

Design process by problem 8.9SpecificationsState diagramCodesimulationsimulation

Verilog template for Moore FSMsmodule FSM_name (Clock, Resetn, input_signal, output_signal);

input Clock, Resetn, input_signal;output output_signal;reg [n:1] state_present, STATE_NEXT;g [ ] _p _parameter [n:1] STATE1 = 2'b00, STATE2 = 2'b01…. ;

// Define the next state combinational circuitalways @(input_signal or state_present)

case (state present)

3 parallel blocks:1) always block:

combinational circuit forcase (state_present)STATE1: if (input_signal) STATE_NEXT = …;

else STATE_NEXT = …;STATE2: if (input_signal) STATE_NEXT = …;

else STATE_NEXT = …;

combinational circuit for next state

2) always block:update states

3) i…… default: STATE_NEXT = n'bxx;

endcase

// Define the sequential block

3) assign: combinational circuit foroutput

// Define the sequential blockalways @(negedge Resetn or posedge Clock)

if (Resetn == 0)y <= STATE1;elsey <= Y;

// D fi t t

Next statecircuit Flip-flops Output

circuitY y

zw

// Define outputassign output_signal = ….;

endmoduleclock resetn

Example: sequence detectort t tmodule simple (Clock Resetn w z); y: present state

Y: next state

State assignment

module simple (Clock, Resetn, w, z);input Clock, Resetn, w;output z;reg [2:1] y, Y;parameter [2:1] A = 2'b00, B = 2'b01, C = 2'b10; State assignment// Define the next state combinational circuitalways @(w or y)

case (y)A: if (w) Y = B;A: if (w) Y B;

else Y = A;B: if (w) Y = C;

else Y = A;C: if (w) Y = C;

else Y = A;default: Y = 2'bxx;

endcase


Next state Output

// e e t e seque t a b ocalways @(negedge Resetn or posedge Clock)

if (Resetn == 0)y <= A;elsey <= Y;

// D fi t tY y

zNext statecircuit Flip-flops Output

circuit// Define outputassign z = (y == C);

endmodule

w z

clock resetn

Second Verilog templatemodule FSM_name (Clock, Resetn, input_signal, output_signal);

input Clock, Resetn, input_signal;output output_signal;reg [n:1] state_present, STATE_NEXT;g [ ] _p _parameter [n:1] STATE1 = 2'b00, STATE2 = 2'b01…. ;

// Define the next state combinational circuitalways @(input_signal or state_present)

begin


combinational circuit forbegincase (state_present)

STATE1: if (input_signal) STATE_NEXT = …;else STATE_NEXT = …;

STATE2: if (input_signal) STATE_NEXT = …;

combinational circuit for next stateoutput

2) always block:d t t telse STATE_NEXT = …;

…… default: STATE_NEXT = n'bxx;

endcase

update states

merge

// Define outputoutput_signal=….;

end// Define the sequential block

l @( d R t d Cl k)


circuitY y

zw

always @(negedge Resetn or posedge Clock)if (Resetn == 0)y <= STATE1;elsey <= Y;


Example: sequence detectort t tmodule simple (Clock Resetn w z); y: present state

Y: next state

State assignment

module simple (Clock, Resetn, w, z);input Clock, Resetn, w;output z;reg z;reg [2:1] y, Y; State assignmentparameter [2:1] A = 2'b00, B = 2'b01, C = 2'b10;

// Define the next state combinational circuitalways @(w or y)beginbegin

case (y)A: if (w) Y = B;

else Y = A;B: if (w) Y = C;

else Y = A;C: if (w) Y = C;

else Y = A;default: Y = 2'bxx;

endcase

Next state Output

e dcase// Define outputz = (y == C);

end// Define the sequential block

l @( d R t d Cl k)Y y

zNext statecircuit Flip-flops Output

circuitalways @(negedge Resetn or posedge Clock)

if (Resetn == 0)y <= A;elsey <= Y;

endmodule

w z

clock resetn

Third Verilog templatemodule FSM_name (Clock, Resetn, input_signal, output_signal);

input Clock, Resetn, input_signal;output output_signal;reg [n:1] state; // don’t need state_present, STATE_NEXT;

2 parallel blocks:1) always block:g [ ] _p _

parameter [n:1] STATE1 = 2'b00, STATE2 = 2'b01…. ;


always @(negedge Resetn or posedge Clock)

1) always block: sequential circuit for next stateand update

2) i bl kalways @(negedge Resetn or posedge Clock)if (Resetn == 0) state <= STATE1;elsecase (state)

STATE1: if (input_signal) state < = …;

2) assign block:for output

assign cannot be put inside else state < = …;

STATE2: if (input_signal) state <= …;else state < = …;

…… default: state <= n'bxx;

merge

the always block

default: state n bxx;endcase

// Define outputassign output_signal=….;


circuitY y

zw


Example: sequence detectormodule simple (Clock, Resetn, w, z);

input Clock, Resetn, w;output z;reg [2:1] y;parameter [2:1] A = 2'b00, B = 2'b01, C = 2'b10;// Define the sequential blockalways @(negedge Resetn or posedge Clock)

if (Resetn == 0) y <= A;else

case (y)A: if (w) y <= B;

else y <= A;B: if (w) y <= C;

else y <= A;C: if (w) y <= C;

else y <= A;default: y <= 2'bxx;

endcase

// Define output assign z = (y == C);

endmodule

S f V il f FSMSummary of Verilog for FSMsNo standard way for writing code thatNo standard way for writing code that represents an FSM.However there are 3 templates we can useHowever, there are 3 templates we can use to code, based on state diagram.The 3 templates provide identicalThe 3 templates provide identical functionality, but may produce different circuits.The first two templates are recommended.Similar templates exist for Mealy FSMs

Example: control of swappingd l t l (Cl k R t R1i R1 tmodule control (Clock, Resetn, w, R1in, R1out,

R2in, R2out, R3in, R3out,Done);input Clock, Resetn, w;output R1in, R1out, R2in, R2out,

R3i R3 t DR3in, R3out, Done;reg [2:1] y, Y;parameter [2:1] A = 2'b00, B = 2'b01,

C = 2'b10, D = 2'b11;

// Define the next state combinational circuitalways @(w or y)

case (y)A: if (w)Y B;A: if (w)Y = B;

else Y = A;B: Y = C;C: Y = D;D: Y = A;

// Define outputsD: Y = A;

endcase


assign R2out = (y == B);assign R3in = (y == B);assign R1out = (y == C);assign R2in = (y == C);

always @(negedge Resetn or posedge Clock)if (Resetn == 0) y <= A;else y <= Y;

assign R3out = (y == D);assign R1in = (y == D);assign Done = (y == D);

endmodule

V il f M l FSMVerilog for Mealy FSMsSimilar to Moore FSMsSimilar to Moore FSMsThe main difference between Mealy and Moore:

For Moore, the output is defined independent of inputs, so the code for output is separated from the code for state transitions, e.g. caseFor Mealy, the code for output is written within the case statement that also defines the state transitions.

Two parallel blocks: always @ (inputs or current states) defines the next statealways @ (inputs or current_states) defines the next state and output.alwasy @ (negedge resetn or posedge clock) defines flip-flopsflops.

Example: Verilog for Mealymodule mealy (Clock Resetn w z);module mealy (Clock, Resetn, w, z);

input Clock, Resetn, w;output z;reg y, Y, z;parameter A = 0, B = 1;


// Define the next state and output //combinational circuitsalways @(w or y)

case (y)A: if (w)

y @( g g p g )if (Resetn == 0) y <= A;else y <= Y;

endmoduleA: if (w)

beginz = 0; Y = B;end

else beginz = 0; Y = A;end

B: if (w)begin

Reset w 1 = z 0 = ⁄

begz = 1; Y = B;end

else begin

0 Y A

A

w 0 = z 0 = ⁄ w 1 = z 1 = ⁄

B

w 0 = z 0 = ⁄ z = 0; Y = A;end

endcase

Verilog template for Mealy FSMsmodule FSM_name (Clock, Resetn, input_signal, output_signal);

input Clock, Resetn, input_signal;output output_signal;

[ 1] S Areg [n:1] state_present, STATE_NEXT;parameter [n:1] STATE1 = 2'b00, STATE2 = 2'b01…. ;

// Define the next state combinational circuit and outputsalways @(input signal or state present)


combinational circuit fory @( p _ g _p )case (state_present)

STATE1: if (input_signal) define output and next state;else define output and next state;

STATE2: if (input_signal) define output and next state;else define o tp t and ne t state;

combinational circuit for next state and output

2) always block:update states

else define output and next state;…… default: define output and next state;

endcase


if (Resetn == 0)y <= STATE1;elsey <= Y;


circuitY y

zw

endmodule clock resetn

D i lDesign example:a sequential circuit has two inputs, w1 and w2, and an output, z.q p , , p ,Its function is to compare the input sequences on the two inputs. If w1 =w2 during any four consecutive clock cycles, the circuit produces z=1; otherwise, z=0.For example

w1: 0 1 1 0 1 1 1 0 0 0 1 1 0w1: 0 1 1 0 1 1 1 0 0 0 1 1 0w2: 1 1 1 0 1 0 1 0 0 0 1 1 1

z: 0 0 0 0 1 0 0 0 0 1 1 1 0

t t distate diagramresetn

www ⊕=W=1

A21 www ⊕=

W1 != w2

W=0Mealy FSM

B 1 equal

W 0

W=1

C 2 equal

W=0

W=1

D 3 equal

W=0W=1

D 3 equal

W=0 / z=1 4 equal

: Verilog codemodule prob8_9 (Clock, Resetn, w1, w2, z);

input Clock, Resetn, w1, w2;output z;reg z;

[2 1] Yreg [2:1] y, Y;wire w;parameter [2:1] A = 2'b00, B = 2'b01, C = 2'b10, D = 2'b11;// Define the next state and output combinational circuitsassign w = w1 ^ w2;g ;always @(w or y)

case (y)A: if (w) begin Y = A; z = 0; end

else begin Y = B; z = 0; endB: if (w) begin Y = A; z = 0; endB: if (w) begin Y = A; z = 0; end

else begin Y = C; z = 0; endC: if (w) begin Y = A; z = 0; end

else begin Y = D; z = 0; endD: if (w) begin Y = A; z = 0; end

else begin Y = D; z = 1; endendcase

// Define the sequential blockalways @(negedge Resetn or posedge Clock)always @(negedge Resetn or posedge Clock)

if (Resetn == 0) y <= A;else y <= Y;

endmodule

i l tisimulationSpecify input signals w1 and w2:Specify input signals w1 and w2:

Assume that w1 and w2 may change their values only after the positive edges of clock with a small delay.This assumption is reasonable because w1 and w2 most likely come from a circuit with the same clock.Otherwise the simulation result may be not what youOtherwise, the simulation result may be not what you expected.

i l tisimulation

i l ti blsimulation problemIf inputs are not specified appropriately.

W1, w2, clock change at the same timeconfusedconfused

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Verilog_ Finite State Machines