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Verilog – digitalni dizajn
Modelovanje, predstavljanje, simulacija digitalnog hardvera Konkurentno izvršavanje Paralelni tok podataka signali i vreme
Specijalne jezičke konsrtrukcije Prelazi na okidnu ivicu kašnjenja Provera tajminga
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Moduli
Definicija
module module_name ( port_list );port declarations;…variable declaration;…description of behavior
endmodule
primer
module HalfAdder (A, B, Sum Carry);input A, B;output Sum, Carry;assign Sum = A ^ B; //^ znači XORassign Carry = A & B; // & znači ANDendmodule
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Načini opisa
Strukturni: Verilog gate primitive
Primer multiplekser:not n1(sel_n, sel);and a1(sel_b, b, sel_b);and a2(sel_a, a, sel);or o1(out, sel_b, sel_a);
selb
a outsel_n
sel_b
sel_a
n1 a1
a2
o1
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Načini opisa
Dataflow: specificiraju se izlazni signali u funkciji ulaznih
primer:assign out = (sel & a) | (~sel & b);
sel
b
a
outsel_n
sel_b
sel_a
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Načini opisa
Behavioral: algoritamski
Example:if (select == 0) begin
out = b;endelse if (select == 1) begin
out = a;end a
b
sel
outBlack Box
2x1 MUX
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Načini opisa
Switch lewel: elektronicarski, nema u VHDLu
module mynot (input x, output f); // internal declaration supply1 vdd; supply0 gnd; // NOT gate body
pmos p1 (f, vdd, x); nmos n1 (f, gnd, x);
endmodule
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Leksičke konvencije
Comentari: sintaksa iz jezika C// Single line comment/* Another single line comment *//* Begins multi-line (block) comment
All text within is ignoredLine below ends multi-line comment
*/ Brojevi
decimalni, hex, oktalni, binarniunsized decimalnisize base forma
String" između navodnika"
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Leksičke konvencije
IdentifikatoriA ... Za ... z0 ... 9Underscore
Stringovi limitirani na 1024 karaktera
Prvi karakter nemože biti cifra
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Ključne reči
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Tipovi podataka
net (wire, wand, wor, tri, triand, trior, trireg) reg vektor ceo broj realan broj niz (array)
(nije string!) memorija parametar
Oznaka Logičko stanje0 logička nula1 logička jedinicax nepoznato (neodređeno stanje)z stanje velike impedanse
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Tpovi podataka
Net Tipovi: fizicka veza između strukturnih elemenata
Register Tip: apstraktni memorijski element
Default vrednosti Net Types : z Register Type : x
Net Tipovi: wire, tri, wor, trior, wand, triand, supply0, supply1
Register tipovi : reg, integer, time, real, realtime
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Tipovi podataka
Net Type: Wire wire [ msb : lsb ] wire1, wire2, …
Examplewire Reset; // A 1-bit wirewire [6:0] Clear; // A 7-bit wire
Register Type: Regreg [ msb : lsb ] reg1, reg2, …
Examplereg [ 3: 0 ] cla; // A 4-bit registerreg cla; // A 1-bit register
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Restrikcije
Data Flow and Structural Modeling Can use only w ire data type Cannot use reg data type
Behavioral Modeling Can use only reg data type (within initial and always
constructs) Cannot use w ire data type
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Memories
An array of registers
reg [ msb : lsb ] memory1 [ upper : lower ];
Examplereg [ 0 : 3 ] mem [ 0 : 63 ];// An array of 64 4-bit registersreg mem [ 0 : 4 ];// An array of 5 1-bit registers
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Operatori
Podela: unarni, binarni, ternarni operatori.Primeri:
a = ~b; // ~ je unarni operator. b je operand.a = b && c; // && je binarni operator. b i c su// operandi.a = b ? c : d; // ?: je ternarni operator. b, c i d su// operandi.
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Operatori
Tipovi: dele se na
Aritmetičke (+ − * / %)logičke (&& || !)Relacione (> < >= <= )jednakosti ( == != === !==)Bitwise ( ~ & | ^ ~^)Redukcione ( & ~ & | ~| ^ ~^) polazi se od MSBPomeračke (>> <<)pridruživanja (primer)Umnožavanja (primer)Uslovni (primer)
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Pridruživanje
Spaja više operanada(mogu biti vektori i skalari).Dužina vektorskihoperanada treba da jeunapred definisana.I delovi vektora mogu bitioperandi.
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Umnožavanje
Prvi operand konstantaodređuje koliko puta trebanapisati drugi operand jedaniza drugog.. Umno.avanje se mo.ekombinovati sapridru.ivanjem.
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? USLOVNA OPERACIJA
Ako je uslov neodređen (x) rezultantni vektor se sastoji izpoklapajućih bitova operanada i x-ova na mestima gde se ne poklapaju vrednosti. Radi kao multiplekser 2/1 ali može da se koristi i kao kolo zasprezanje sa tri stanja.
// Opisivanje multipleksera 2/1 assign out = control ? in1 : in2;// Modeliranje kola za sprezanje sa tri stanja assign addr_bus = drive_enable ? addr_out : 32’bz;
// Rekurzivno korišćenje uslovne operacije.reg [1:0] A, B; // Podaci A, B su reg tipa, veličine 2 bita.assign out = A[0] ? ( B[0] ? 1’b1 : 1’b0 ) : ( B[0] ? 1’b0 : 1’b1);
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Prioritet operatora
Operator i simbol
Unary, Multiply, Divide, Modulus !, ~, *, /, %
Add, Subtract, Shift +, - , <<, >>
Relation, Equality <,>,<=,>=,==,!=,===,!==
Reduction &, !&,^,^~,|,~|
Logic &&, ||
Conditional ? :
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Verilog gate primitive
The gates have one scalar output and multiple scalar inputs. The 1st terminal in the list of gate terminals is an output and the other terminals are inputs.Gate DescriptionAnd N-input AND gateNand N-input NAND gateOr N-input OR gateNor N-input NOR gateXor N-input XOR gateXnor N-input XNOR gate
Za sintezu konsultovati alat koji se koristi!
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Verilog gate primitive
Gate Description Not N-output inverter Buf N-output buffer. Bufif0 Tristate buffer, Active low en. Bufif1 Tristate buffer, Active high en. Notif0 Tristate inverter, Low en. Notif1 Tristate inverter, High en. Tristate gates have three ports: the first is an output port, the second is a data port,
and the third is a control port. The control port is used to set gates in high-impedance state. https://www.utdallas.edu/~akshay.sridharan/index_files/Page4933.htm
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Logička stanja i fan-out
Logic Value Description 0 zero, low, false 1 one, high, true z or Z high impedance, floating x or X unknown, uninitialized, contention
Verilog Strength LevelsStrength Level Specification Keyword 7 Supply Drive supply0 supply1 6 Strong Pull strong0 strong1 5 Pull Drive pull0 pull1 4 Large Capacitance large 3 Weak Drive weak0 weak1 2 Medium Capacitance medium 1 Small Capacitance small 0 Hi Impedance highz0 highz1
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Transmisioni gejtovi
Transmission gates are bi-directional and can be resistive or non-resistive. Resistive devices reduce the signal strength which appears on the output by one level. All the switches only pass signals from source to drain, incorrect wiring of the devices will result in high impedance outputs.
ASIC digital design Retko za FPGA sintezu Verolog AMS −nije sinteza Nije analogna simulacija
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Prekidači i transmisioni gejtovi
There are six different switch primitives (transistor models) used in Verilog, nmos, pmos and cmos and the corresponding three resistive versions rnmos, rpmos and rcmos. The cmos type of switches have two gates and so have two control signals.Syntax: keyword unique_name (drain. source, gate)
Gate Description1. pmos Uni-directional PMOS switch1. rpmos Resistive PMOS switch2. nmos Uni-directional NMOS switch2. rnmos Resistive NMOS switch3. cmos Uni-directional CMOS switch3. rcmos Resistive CMOS switch4. tranif1 Bi-directional transistor (High)4. tranif0 Bi-directional transistor (Low)5. rtranif1 Resistive Transistor (High)5. rtranif0 Resistive Transistor (Low)6. tran Bi-directional pass transistor6. rtran Resistive pass transistor7. pullup Pull up resistor8. pulldown Pull down resistor
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Prekidači:nmos, pmos, rnmos, rpmos, cmos, rcmos
The instantiation of these MOS switches can contain zero, one, two, or three delays
The strength declaration is illegal. The nmos, pmos and cmos switches reduce supply strength of the signals to strong strength. Signals with others strengths are passed from input to output without a strength reduction. The rnmos, rpmos and rcmos switches reduce supply and strong strength of signals to pull strength. Thepull strength of signals is reduced to weak. The large and weak strength of signals are reduced to medium. The medium strength of signals is reduced to small. Signals with other strengths are passed from input to output without strength reduction.
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rtranif0, rtranif1, tranif0 and tranif1
The instantiation of these bi-directional pass switches can contain zero, one, two, or three delays.
The strength declaration is illegal. The tranif0 and tranif1 switches reduce supply strength of signals to strong. Signals with others strengths are passed from input to output without strength reduction. The rtranif0 andrtranif1 switches reduce supply and strong strength of signals to pull. The pull strength of signals is reduced to weak. The large and weak strength of signals are reduced to medium. The medium strength of signals is reduced to small. Signals with other strengths are passed from input to output without strength reduction.
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tran and rtran
The instance of these bidirectional switches cannot contain delay and strength declaration.
The tran switches reduce supply strength of signals to strong strength. Signals with others strengths are passed from input to output without strength reduction. The rtran switches reduce supply and strong strength of signals to pull. The pull strength of signals is reduced to weak. The large and weak strength of signals are reduced to medium. The medium strength of signals is reduced to small. Signals with other strengths are passed from input to output without strength reduction.
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pullup and pulldown
The instantiation pullup and pulldown sources cannot contain delay declaration. The pullup can contain only strength1 specification (the strength0 declaration is optional). The pulldown can contain only strength0specification (the strength1 declaration is optional).
The pullup source places a logic value 1 on connected signals. The pull down source places a logic value 0 on connected signals.
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Slabljenje intenziteta signala
Na osnovu otpornosti veze
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Smanjenje intenziteta signala
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Switch level dizajn, NAND
module my_nand (input x, y, output f);supply1 vdd;supply0 gnd;wire a;// NAND gate body
pmos p1 (f, vdd, x);pmos p2 (f, vdd, y);nmos n1 (f, a, x);nmos n2 (a, gnd, y);
endmodule
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Pseudo nMOS NOR
module pseudo_nor(input x, y, output f);supply0 gnd;// Pseudo nMOS gate body
nmos nx (f, gnd, x);nmos ny (f, gnd, y);pullup (f);
endmodule
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CMOS prekidač, digitalni!
cmos [instance_name] (output, input, ncontrol, control);
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2/1 Multiplexer
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Bidirekcioni prekidači
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Kašnjenja MOS/CMOS prekidača
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Kašnjenja bidirekcionih prekidača
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trireg Nets, states: Driven, Capacitive
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trireg Nets, states: Driven, Capacitive
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Strukturno modelovanje ponovo
Izvršenje: konkurentno (paralelno) Format (Primitive Gates, ugrađeni) slično kao VHDL
and G2(Carry, A, B); prvi parametar (Carry) – Output Ostali prametri (A, B) – Inputs Ožičena logika kašnjenja
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Ožičena logika
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Kašnjenja
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Kašnjenja
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kašnjenja
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Gate Delay Specifications
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Hazardi
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A Static Hazard Example
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A Dynamic Hazard Example
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primer
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MININIMALNE, TIPIČNE I MAKSIMALNEVREDNOSTI KAŠNJENJA - PRIMERI
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Dataflow Modelovanje Continuous assignment statement
Format: assign [ delay ] net = expression; Example: assign sum = a ^ b; Na ovaj način dajemo vrednost nosiocima podataka tipa net. Sa leve
strane može i reg
Delay: Time duration between assignment from RHS to LHS All continuous assignment statements execute concurrently Order of the statement does not impact the design Implicitni assign
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Dataflow Modelovanje
Kašnjenje primer: assign #2 sum = a ^ b; “#2” znači 2 time-units Ako se ne specificira : 0 (podrazumevano)
Associate time-unit with physical time `timescale time-unit/time-precision Example: `timescale 1ns/100 ps
Timescale`timescale 1ns/100ps 1 Time unit = 1 ns Time precision is 100ps (0.1 ns) 10.512ns is interpreted as 10.5ns
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Dataflow Modeling (cont.)
Example:
`timescale 1ns/100psmodule HalfAdder (A, B, Sum, Carry);
input A, B;output Sum, Carry;assign #3 Sum = A ^ B;assign #6 Carry = A & B;
endmodule
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Dataflow Modeling (cont.)
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KAŠNJENJA U IMPLICITNIM DODELAMA
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ZADAVANJE KAŠNJENJA PRIDEKLARISANJU NOSIOCA PODATKA TIPA net
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Behavioral Modeling-OPIS NA NIVOU PONAŠANJA
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Behavioral Modeling
Example:
module mux_2x1(a, b, sel, out);input a, a, sel;output out;always @(a or b or sel)beginif (sel == 1)
out = a;else out = b;
endendmodule
Sensitivity List
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Behavioral Modeling-OPIS NA NIVOU PONAŠANJA
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Procedural Constructs
Two Procedural Constructs initial Statement always Statement
initial Statement : Executes only once always Statement : Executes in a loop Example:
…initial beginSum = 0;Carry = 0;
end…
…always @(A or B) beginSum = A ^ B;Carry = A & B;
end…
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PROCEDURA TIPA initial
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PROCEDURA TIPA initial -PRIMER
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PROCEDURA TIPA always
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Behavioral Modeling (cont.)
always statement : Sequential Block
Sequential Block: All statements within the block are executed sequentially
When is it executed? Occurrence of an event in the sensitivity list Event: Change in the logical value
Statements with a Sequential Block: Procedural Assignments
Delay in Procedural Assignments Inter-Statement Delay Intra-Statement Delay
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Behavioral Modeling (cont.)
Inter-Assignment Delay Example:
Sum = A ^ B;#2 Carry = A & B;
Delayed execution
Intra-Assignment Delay Example:
Sum = A ^ B;Carry = #2 A & B;
Delayed assignment
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DODELE U initial I always PROCEDURAMA
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BLOKIRAJUĆE DODELE
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BLOKIRAJUĆE DODELE
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Event Control
Event Control Edge Triggered Event Control Level Triggered Event Control
Edge Triggered Event Control@ (posedge CLK) //Positive Edge of CLK
Curr_State = Next_state;
Level Triggered Event Control@ (A or B) //change in values of A or B
Out = A & B;
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Loop Statements
Loop Statements RepeatWhile For
Repeat Loop Example:
repeat (Count)sum = sum + 5;
If condition is a x or z it is treated as 0
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Loop Statements (cont.)
While Loop Example:
while (Count < 10) beginsum = sum + 5;Count = Count +1;
end If condition is a x or z it is treated as 0
For Loop Example:
for (Count = 0; Count < 10; Count = Count + 1) beginsum = sum + 5;
end
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Conditional Statements
if Statement Format:
if (condition)procedural_statement
else if (condition)procedural_statement
elseprocedural_statement
Example:if (Clk)
Q = 0;else
Q = D;
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Conditional Statements (cont.)
Case Statement Example 1:
case (X)2’b00: Y = A + B;2’b01: Y = A – B;2’b10: Y = A / B;
endcase Example 2:
case (3’b101 << 2)3’b100: A = B + C;4’b0100: A = B – C;5’b10100: A = B / C; //This statement is executed
endcase
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Conditional Statements (cont.)
Variants of case Statements: casex and casez
casez – z is considered as a don’t care
casex – both x and z are considered as don’t cares
Example:casez (X)2’b1z: A = B + C;2’b11: A = B / C;
endcase
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Compiler Directives
`define – (Similar to #define in C) used to define global parameter
Example: `define BUS_WIDTH 16reg [ `BUS_WIDTH - 1 : 0 ] System_Bus;
`undef – Removes the previously defined directive
Example:`define BUS_WIDTH 16
…reg [ `BUS_WIDTH - 1 : 0 ] System_Bus;…
`undef BUS_WIDTH
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Compiler Directives (cont.)
`include – used to include another file
Example`include “./fulladder.v”
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System Tasks
Display tasks $display : Displays the entire list at the time when
statement is encountered $monitor : Whenever there is a change in any argument,
displays the entire list at end of time step
Simulation Control Task $finish : makes the simulator to exit $stop : suspends the simulation
Time $time: gives the simulation
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Type of Port Connections
Connection by Positionparent_mod
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Type of Port Connections (cont.)
Connection by Nameparent_mod
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Empty Port Connections
If an input port of an instantiated module is empty, the port is set to a value of z (high impedance).
module child_mod(In1, In2, Out1, Out2) module parent_mod(…….)input In1; input In2; child_mod mod(A, ,Y1, Y2); output Out1; //Empty Inputoutput Out2; endmodule
//behavior relating In1 and In2 to Out1endmodule
If an output port of an instantiated module is left empty, the port is considered to be unused.module parent_mod(…….)child_mod mod(A, B, Y1, ); //Empty Output
endmodule
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Test Bench
`timescale 1ns/100psmodule Top;
reg PA, PB;wire PSum, PCarry;
HalfAdder G1(PA, PB, PSum, PCarry);
initial begin: LABELreg [2:0] i;for (i=0; i<4; i=i+1) begin{PA, PB} = i;
#5 $display (“PA=%b PB=%b PSum=%b PCarry=%b”, PA, PB, PSum, PCarry);
end // forend // initial
endmodule
Test Bench
DesignModule
Apply Inputs
Observe Outputs
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Test Bench - Generating Stimulus
Example: A sequence of values
initial beginClock = 0;#50 Clock = 1;#30 Clock = 0;#20 Clock = 1;
end
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Test Bench - Generating Clock
Repetitive Signals (clock)
Clock
A Simple Solution:wire Clock;assign #10 Clock = ~ Clock
Caution: Initial value of Clock (w ire data type) = z ~z = x and ~x = x
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Test Bench - Generating Clock (cont.)
Initialize the Clock signalinitial begin
Clock = 0;end
Caution: Clock is of data type w ire, cannot be used in an initial statement
Solution:reg Clock;…initial beginClock = 0;
end…always begin#10 Clock = ~ Clock;end
forever loop can also be used to generate clock
