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AKGEC INTERNATIONAL JOURNAL OF TECHNOLOGY, Vol. 6, No. 1

Variation of the Capacitance of Supercapacitors

with Current and Frequency

Abstract -- In this work, the charge and discharge cycle of a

supercapacitor was examined from which it was observed that

the capacitance of the supercapacitor changes while charging

and discharging. So also, the capacitance was observed to vary

with frequency when frequency response analysis was performed

on it.

Keywords: Supercapacitors, Energy-Density, Charge-Discharge

Testing.

I. INTRODUCTION

AS A result of the rapid development in technology and the

availability of portable devices, researches on energy storage

devices are under process in order to obtain storage devices

that have higher energy density as well as higher power

density. Batteries have higher energy density but with lower

power density. In the case of supercapacitors, the reverse is

the case [1]. Thus present researches are on how to improve

the energy density of supercapacitors so that it can replace

batteries in some applications [2]. The Ragone Plot below shows

the various forms of energy storage devices, their energy

density and power density.

Figure1: Ragone plot of energy storage devices [3].

In order to improve the energy density of supercapacitors,

various materials have been developed and some are still in

the process. The storage capability of these new materials can

only be examined by experimentation. Such experiments could

either be cyclic voltammetry, impedance spectroscopy or

Usman Sammani Sani1 and Ibrahim Haruna Shanono2

Department of Electrical Engineering,

Bayero University, Kano, P.M.B. 3011, Nigeria1usmanssani@live.com, 2ihshanono.ele@buk.edu.ng

charge/discharge testing [4], [5]. In this work, impedance

spectroscopy and galvanostatic charge/discharge cycling were

employed to see the frequency as well current behaviour of

supercapacitors.

II. METHODOLOGY

Step I: Galvanostatic Charge/ Discharge cycling was performed

on a capacitor, using an Arbin BT2000 multi channel battery

testing instrument along with its Arbin MITS Pro Software.

The galvanostatic current was set at 50mA. The results below

were obtained from the experiment.

The charts above were obtained by exporting the results of

the experiment to Microsoft Excel and subsequently plotting

the charts. Amongst the columns from the excel file there is

(1)

The current of a capacitor is [6]

(2)

Thus,

(3)

The value of C was then computed from equation (3) and

plotted against the testing time.

Step 2: Impedance spectroscopy was performed on another

supercapacitor using a VERSASTAT 3 device for a frequency

range of 10 mHz to 10 KHz. The plot of capacitance was

obtained.

III. DISCUSSION OF RESULTS

The results from the galvanostatic charge/ discharge showed

how the current and voltage in a capacitor are. When one of

them rose, the other one also rises and vice versa as shown in

figure 2. The charge energy also depended on them as shown

in figure 3. The capacitance of the supercapacitor was observed

to also change during the charging and discharging periods. It

increased while charging and decreased while discharging.

This is not in conformity with equation 3 in which the

capacitance is considered to be constant.

37

VARIATION OF THE CAPACITANCE OF SUPERCAPACITORS

Figure 2. Plot of current and voltage vs testing time.

Figure 3. Plot of Charging Energy vs Testing time(s).

Figure 4. Plot of Capacitance vs Testing time(s).

38

AKGEC INTERNATIONAL JOURNAL OF TECHNOLOGY, Vol. 6, No. 1

So also the result from impedance spectroscopy showed how

the capacitance varied with frequency. This implies that the

capacitance value is not constant but it varies with any of the

parameters voltage, current and frequency. As such

manufacturers of such kinds of capacitors now include plots

in their datasheets so that users can be able to make proper

choices.

IV. CONCLUSION

In this paper it has been shown that current, voltage and

frequency affect the value of the capacitance of a

supercapacitor. In order for users of such products to make

proper choices, manufacturers of supercapacitors include more

information in their datasheets regarding this issue.

V. REFERENCES[1]. Lingling Du, Study on Supercapacitor Equivalent Circuit

Model for Power Electronics Applications, Proc. 2009 2nd

International Conference on Power Electronics and Intelligent

Transportation System, 2009, pp. 51-54.

[2]. Xiaolai Liu & Jin Li, Study on the Electrode Materials of

Electrochemical Capacitor, International Journal of Chemistry,

Vol. 3, No. 2, June 2011, pp.198-200.

[3]. Patrik Johansson, Bjrn Andersson, Comparison of Simulation

Programs for Supercapacitor Modelling: Model Creation and

Verification, unpublished thesis, Chalmers University of

Technology, 2008, p. 3.

[4]. U. S. Sani, I. H. Shanono, A Study on Carbon Electrode

Supercapacitors, International Journal of Engineering Research

and Technology, Vol. 2, Issue 6, June 2013, pp. 2957-2964.

Figure 5. Plot showing the variation of capacitance with frequency.

Usman Sammani Sani graduated from

Bayero University, Kano in 2008, where he

obtained a bachelor degree of electrical

engineering. He then furthered his studies, in

which he obtained an MSc in Electronic

Communications and Computer Engineering

from The University of Nottingham Malaysia

Campus in 2011.

Usman is presently a lecturer in the

Department of Electrical Engineering, Bayero

University Kano. His research interests include

digital communications, digital circuits design and testing of fabricated

electronic components.

Ibrahim Haruna Shanono received his

B.Eng and MSc. degree from Bayero University

Kano and Nottingham University in 2008 and

2012 respectively. He is currently working with

the Department of Electrical Engineering,

Bayero University Kano, Nigeria. His research

interests are in the areas of Renewable Energy,

Power Electronics and Automatic Control

systems.

[5]. U. S. Sani, I. H. Shanono, An Equivalent Circuit of Carbon

Electrode Supercapacitors, Proc. 2014 Nigeria Engineering

Conference, pp. 631-639.

[6]. P.K. Rajan, A. Sekar, Linear Circuit Analysis, in W.K. Chen(ed),

39

AN EFFICIENT CARRY SELECT ADDER

An Efficient Carry Select AdderA Review

Abstract -- Adders are one of the widely used digital components

in digital integrated circuit design. Generally,addition is the

basic operation which isused in almost all calculation and

computational systems. So, the efficient implementation and

design of arithmetic units requires the binary adder structures

to be implemented efficiently. A ripple carry adder has smaller

area in design while it has less speed. A carry look ahead adder is

faster in operation as its area requirements are high. Carry

select adders lie in between the spectrum. Design of highly

efficient Carry Select Adder using Square-root technique

suggests many opportunities for increasing the speed and

reducing the area of any data processor. Generally, we have the

carry select adder (CSLA), the fastest adder which is used in

many data-processing processors to perform fast arithmetic

operations. If we study the structure of CSLA, we come to know

that there is scope in area reduction and delay. In this study, a

carry select adder for the computational process is explained

which has some modules to be implemented and synthesized

using HDL coding. Carry select adder (CSLA) is one of the fastest

adder in comparison to all other adders. This review undergoes

very simple and efficient gate-level modification to reduce the

area and delay of the CSLA. Based on this modification, 8-bit,

16-bit, 32-bit and 64-bit Square-Root CSLA (SQRT CSLA)

architecture have been developed having comparison with the

regular SQRT CSLA architecture. The proposed circuit design

has reduced area and delay as compared with the regular SQRT

CSLA.

Keywords: CSLA, RCA, BEC

I. INTRODUCTION

IN recent years, the increasing demand for high-speed

arithmetic units in micro-processors, image processing units

and DSP chips has paved the path for development of high-

speed adders as addition is an important operation in almost

every arithmetic unit, and it too acts as the general building

block for synthesis of all other arithmetic computations. If we

have to increase the portability of systems as well as the

reliability of the battery, area and power are the critical aspects

which are generally considered. In digital adders and

corresponding circuit designs, the speed of addition has

somerestrictions by the time required to propagate a carry

through the adder. The designs of area and high-speed data

path logic systems arethe most important areas of research&

study in VLSI system design. In electronic system and

applications adders are mostly used. As we know that in

Rishabh Rai1 and Rajni Parashar2

Department of Electronics & Communication Engineering, Ajay Kumar Garg Engineering College, Ghaziabad 201 009 UP, India.1rishabh.rahul001@gmail.com ,

22401.rajni@gmail.com

microprocessors, one can perform millions of instructions per

second. So, the speed of operation is most important factor to

be considered while designing multipliers. Even in servers and

personal computers (PC), power dissipation is an important

design parameter. In todays era, the designs of area-efficient

and power-efficient high-speed logic systems are one of the

crucial areas of research in VLSI design. In digital adders and

circuit design, the speed of addition is limited by the time

required by carry to propagate through the adder. The present

scenario signifies the field where computations need to be

performed using low-power and an area-efficient circuit that

must operate at greater speed which is achievable with lesser

delay; efficient adder implementation becomes a most important

factor as well as the necessity. The example of thedevices like

mobile, laptops etc. require more battery usage. So, one who

working in the field of VLSI has to optimize these three

parameters in a design. These controlling parameters are very

difficult to achieve so depending on demand or application

some compromise between constraints has to be made.

Ripple Carry Adders have most compact design but they are

having slow speed of operation. Whereas, the Carry Look

Ahead Adder has fast speed but it consumes more area. Carry

Select Adder solves both the problem as generated by that of

the Ripple Carry Adder and Carry Look Ahead Adder. A Carry-

Select Adder can be structured by using a single Ripple-Carry

Adder and an add-one circuit rather than using the dual Ripple-

Carry Adders.Based on the area, delay and power consumption

requirements, several adder structures have been proposed. A

multiplexer-based add-one circuit is proposed to reduce the

area with less speed penalty. This acts as the sum for each bit

position in an adder which is generated serially only after the

previous bit position has been summed and a carry is

propagated to the next position.

The CSLA is used in many calculation systems to avoid the

problem of carry propagation delay by independently

generating multiple carries and then select a carry to generate

the sum. However, the regular or conventional CSLA is not

area efficient as it uses multiple pairs of Ripple Carry Adders

(RCA) to generate partial sum and carry by taking carry input

Cin=0 and C

in=1,where the final sum and carry are selected by

the multiplexers.