V3 Backup Document G_TM_iBSC System Structure and Principle_R1.0

7/23/2019 V3 Backup Document G_TM_iBSC System Structure and Principle_R1.0

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Internal User Only▲

iBSC System Structure and Principles

Intended audience: staff with Skill Certificate Level III or lower

Issued y !U Product "ept#




$ersion "escription

参考资料

%# &'!%( iBSC)$*#+(#*(, -ardware "escription

+# &'!%( iBSC )$*#+(#*(, System "escription

$ersion "ate

.uthor Checked y /evision /ecord

$%#( +(%%0+0%1 Sun 2in34in3 Su Shaoli5 6ei .ipin35 Liu 7u5 8u&hilian35 Cai 9ai5Sun 2in3ye

6irst pulition




Purpose of this course

7ou are epected to know the followin3 knowled3e after

this course

6unctions5 features and specifications of iBSC

-ardware structure5 shelves and oards of iBSC

Interface desi3n and lo3ic units of iBSC

Control plane and user plane si3nal flow of iBSC

Internal cale connection of iBSC




Contents

iBSC System Overview

iBSC Hardware Structure

iBSC Board PrinciplesiBSC Interfaces and Logic units

Signal Flow on iBSC Control Plane and User Plane

iBSC Internal Cable Connection




S!S; !!S;

odeB

!C

odeB

B"S

BSC

B"S

<SC=$L/ !<SC

Inter#PL$

PS>;

<!8 !<!8

%b

IuPs

IuCs

&

$c

b

c

Iur#g

;etwork Structure




8hat does ?i? stand for@

intelligentintelligent identification of wireless

access intelligent error

self#correction

integrationintegrates multi#interfaces

'()S"$#()IP integrates multi

transmission supported

immensitylarge capability

supports *+,- "!. and (/+++ 'rl

wit0 only two rac1s

intensifyintensified design

supports F!)'F!)H!)&$!)2B#&$!3

innovative etSpeed wireless

en0anced tec0nology

IP&ll#IP platform

supports IP bearer

i B S C




Based on $A universal hardware platform .ll IP hardware architecture

Lar3e capacity and stron3 processin3capailities

<odular desi3n with 3ood scalar

Separation of control streams from mediastreams

Supportin3 6le . and 6le !

Codin3 scheme: 6/=-/=6/=6/0./<=-/0 .</

>ransmission interface: %=>%=6=S><0% asy and smooth up3rade

6leile networkin3 modes

-i3h inte3ration and low power consumption

&'!%( iBSC Product 6eatures




Universal

-ardware Platform

.ll IPSmooth

Up3rade<odularity

!S< = 8C"<.

;!;

>"0SC"<.

C"<. +(((

>otally 16 oards

Universal .ll IP -ardware Platform




<odular "esi3n

Boards "ifferent software can e used to define

different functions for the same oard#

.IU5 BIU5 PCU and >CU are lo3ical units .ll

interface units are in the resource shelf#

'asy Scalability >he system can e

epanded via

addin3 /CBUs#

A /CBUs=+ racks#




<ultiple .ccess <odes and Smooth volution

iBSC supports multiple access modes %=>% S><0% 6=!

volution

BSC

BSC

/;C

/;C

/;CDBSC

/;CDBSC

/;CDBSC

/;CDBSC

BSC

BSC

BSC

iBSC iBSC iBSC &dvantagesE Saves +(F space when +! and

A! modules are inte3rated into the

same site#E Shares cainets5 spare parts5

transmission and O<<#

E Saves power consumptionE Saves en3ineerin3 and network

up3rade cost




iBSC Interfaces

o4Logical

InterfaceLin1 Ob5ect Interface "ype

%# . <SC S><0%5%56=!

+# ! S!S; %56=!

A# .is B>S %5 S><0%5 6=!

G# .ter i>C S><0%、 %




&#Interface '(6"(7 & S"$#( & IP &

&bisInterface

Cabinetumber of

CarriersInterfaceCapacity

umber ofCarriers

Interface Capacityumber of

CarriersInterface Capacity

'(6"(7 &bis

& SingleCabin

et(+-8

&bis9-+: '(6"(7(+-8

&bis9-+: '(6"(7(+-8

&bis9-+: '(6"(7

&9(::'(6"(7 &98 pairs of S"$#( &9( pair of %'

;ualCabin

ets*+,-

&bis9<-8 '(6"(7*+,-

&bis9<-8 '(6"(7*+,-

&bis9<-8 '(6"(7

&9,++'(6"(7 &9(( pairs of S"$#( &9- pairs of %'

S"$=( &bis

& SingleCabin

et(+-8

&bis9* pairs ofS"$#( (+-8

&bis9* pairs of S"$#((+-8

&bis9* pairs of S"$#(

&9(::'(6"(7 &98 pairs of S"$#( &9( pair of %'

;ualCabin

ets*+,-

&bis9> pairs ofS"$#( (+-8

&bis9> pairs of S"$#(*+,-

&bis9> pairs of S"$#(


IP &bis

& SingleCabin

et(+-8

&bis9( pair of %'(+-8

&bis9( pairs of %'-+8:

&bis9( pair of %'

&9-/-'(6"(7 &98 pairs of S"$#( &9( pair of %'

;ualCabin

ets*+,-

&bis 9- pairs of%' *+,-

&bis9- pairs of %'*+,-

&bis9- pairs of %'


IPo' &bis6'IPI?;"B7

& SingleCabin

et(+-8

&bis9(<+ '(6"(7(+-8

&bis9(<+ '(6"(7(+-8

&bis9(<+ '(6"(7

&9(::'(6"(7 &98 pairs of S"$#( &9( pair of %'

;ualCabin

ets*+,-

&bis98:+ '(6"(7*+,-

&bis98:+ '(6"(7*+,-

&bis98:+ '(6"(7


IPo' &bis6'IPI?S;"B-

7

& SingleCabin

et @

@(+-8

&bis9* pairs of S"$#((+-8

&bis9* pairs of S"$#(

@ &98 pairs of S"$#( &9( pair of %'

;ualCabinets

@ @ *+,- (( pairs of S"$#( *+,- &9- pairs of %'

iBSC Interface Specifications




Item Specification;imensions 6HA;A27 6mm7 -3+++ A :++ A <++

2eig0t-,+g6( rac17/8+g6- rac17

Power Consumption

&ll '(9-3//:2)( rac13 <3*<:2)- rac1

&ll IP9-3/8-2)( rac13*3:+:2)- rac1

Power Source !eDuirements #8:E ;C 6#8+E ;C #/,E ;C7

Operating "emperature

Long#term temperature9 +GC8+GC4

S0ort#term temperature9 #/GC

8/GC4

Operating Humidity9Long#term 0umidity9 -+>+4

S0ort#term 0umidity9 />/4

iBSC Physical Specifications




>he all0IP architecture conforms to the trend towards

an IP0ased network

Lar3e capacity and stron3 processin3 capailities

Supports %5 >%5 S><0% and IP interfaces and

fleile networkin3 modes

Item SpecificationBHC& 8-++

$aJimum traffic (/+++'rl

$aJimum t0roug0put over %binterface

'( %b9 -/<$bps

IP %b9 <++$bps

$aJimum "!.s supportedOne !ac19 (3+-8

"wo !ac19 *3+,-

&'!%( iBSC Performance Specifications




Contents



iBSC Board Principles

iBSC Interfaces and Logic units






-ardware .rchitecture Introduction

8ork Planes

Control Plane D User Plane

<a4or Interfaces .is H IP over %5 %5 IP

. H >"< )%5 S><0%,5 IP ! H >"< )%,5 IP

).ter,

Levels of Shelves Shelf >ypes Control shelf )BC>C,5 resource shelf )B!S;,5 switch shelf

)BPS;,

Boards




iBSC Shelves

Control Shelf )BC>C,

System control and mana3ement

Clock capture and distriution

Processin3 of control plane si3nalin3

System operation and maintenance /esource Shelf )B!S;,

System eternal access

Processin3 of universal services

Switch Shelf )BPS;,

Lar3e0capacity IP switch platform on the user plane




S0elf Board Full ame Functions

BC>C

UI<CUniversal Interface <odule forControl plane

Level + switch of control plane si3nalin3

C<P Control <ain ProcessorControl and mana3ement of CS and PS services5 processin3 ofBSS.P and BSS!P protocols5 and resource mana3ement of thesystem

C-UB Control -UB Switch and conver3ence of control plane si3nalin3

O<P Operation <ain ProcessorOperation and maintenance5 system control5 mana3ement andmonitorin3

SBC' '1* Sin3le Board Computer OD< server

CL9! Clock !eneration Clock 3eneration and distriution

IC< Inte3rated Clock <odule Clock 3eneration and distriution )with !PS,

BPS;

!LI !i3ait Line Interface Level % switch5 interface with the resource shelf

PS; Packet Switch ;etworkProvides i0directional user plane data switch with a capacity of G(!ps on each direction

B!S;

SPB- Signaling Processing BoardSignaling processing3 interface board 6(< '( lines for &)%b3eig0t '( lines for &bis7

!UI< !i3a it User Interface <odule Level + switch etween the control plane and the user plane5resource shelf mana3ement

%UP- %S$ Universal Processing Processing of user plane protocols3 suc0 as "C3 PCU and !"P

">B "i3ital >runk Board Provides A+ %=>% trunk interfaces

S">B+ Sonet "i3ital >runk Board + Provides two S><0% interfaces

%IPI %' IP Interface Provides four F' interfaces or one %' interfaces for &bis)&)%b

IPI % IP Interface provides % or >% ased IP connection

&'!%( iBSC Boards




P0ysicalBoard

Logical Board Functions

!IPI

IPBBCompletes IP access over the .is interface5 and sever the controlplane from the user plane

IPICompletes IP access over the . interface5 and sever the controlplane from the user plane )si3nalin3 from service,

IP!BCompletes IP access over the ! interface5 and sever the controlplane from the user plane

!UP+

BIPB+

Search +( ms >/U frames accordin3 to the channels and form IP

packets6or IP access over the .is interface5 it also processes />P#

.IPB It processes />P and forms IP packets

UPPB+ User plane protocol processin3 in the PS field

"/>B+Completes the transcodin3 and rate adaptation of >/.U frames5 andprovides 6/5 6/5 .</ and >6O functions

SPB+

L.P"+ L.P" si3nalin3 processin3

SPB+ <>P+ protocol processin3

!IPB+Provides ! interface functions5 and processes the 6/5 ;S andpartial BSS!P of !P/S#

Physical and Lo3ical Boards of &'!%( iBSC




o4 Board ame umber Slot o4 Bac1up

( O$P - (((- (?(

- C$P -8 (8 (?(

* CHUB - (/(< (?(

8 IC$ - (*(8 (?(

/ UI$C - >(+ (?(

< SBC. - /， , (?(

Introduction to BC>C Completes the 3loal operation

and maintenance of thesystem5 provides the 3loal

system clock5 mana3es the

control plane5 and responsile

for the switch etween the

control plane and the thernet

ach iBSC must e confi3uredwith one control shelf5 which is

located in Shelf + in /ack %




BC>C 8orkin3 Principles

>he clock 3eneration oard

)IC<, distriutes clock

si3nals to the switch shelf

and resource shelves throu3h

cales#

Ohe C-UB acts as the

control stream conver3ence

center for the control streams

from the switch shelf5 the

resource shelf and the control

shelf#

C-UB

CC

Outsidenetwork

UI<C

BPS;

!UI<

B!S;

19=%*<

thernet

-UB

SBC'

-UB





( %UI$ - >(+ %%

- %IPI # (#:3((#(, %%

* %UP- # -#:3((#(< 0

8 ;"B +#: (#:3((#(83(, 0

/ S;"B- # (#:3((#(< %%

< SPB- # (#:3((#(, 0

, 'IPI # (#:3((#(, 0

Introduction to B!S; Provides system eternal

interfaces#

Processes universal services#

.cts as the Level + switch center#

>he B!S; is confi3ured in Shelf

% and Shelf A of the main rack#

8hen a sin3le shelf constitutes

an office5 it is confi3ured in Shelf+#




B!S; 8orkin3 Principles

>he !UI< oard is the

conver3ence and switch center forvarious data in the resource shelf#

It completes the information

echan3e etween modules#

>he !UI< oard interconnects

with the !LI oard in the packet

switch shelf to carry out level %

switch etween different resource

shelves#

">Bs and SPBs provide %

interfaces5 and S">Bs provide

S><0% access# !IPI oards provide 6 and !

access#

Processes universal services

)conversion from >C and >"< to

IP packets5 processin3 of user

plane protocols,#





( PS - ,: Load s0aring

- %LI -< (< Load s0aring

* C$P +- (((8 (?(

8 UI$C - (/(< (?(

Introduction to BPS;

Interconnects B!S;s and

Level % switch centers on theuser plane#

ach iBSC should have one

BPS;5 which is confi3ured in

Shelf G#

If the iBSC has two B!S;s5then the BPS; is not

mandatory# -owever5 this can

affect the capacity epansion

of the system#




BPS; 8orkin3 Principles

>he !LI oard receivesuser plane data from the

!UI< oard#

>he PS; provides G(!ps

data switch capacity#

>he UI<C receives clock

and control si3nals from the

control shelf and distriutes

control D mana3ement

interfaces and clock si3nals

in the shelf#




Shelf Confi3uration )%,

.is Interface %

.0Interface %




.is Interface IP

.0Interface IP

Cainet Confi3uration )+,




Cainet Confi3uration )A,

.is Interface IPo

.0Interface IP




Contents










Ohe O<P oard processes the 3loal procedure5 performs OD<

related control of the entire system )includin3 OD< proy,5 andconnects to the O<< throu3h the %((< thernet#

.s the processin3 core of iBSC operation D maintenance5 the O<P

oard can directly or indirect monitor and mana3e all oards in the

system# It provides two links )thernet interface and /SG1J, for

confi3uration mana3ement of system oards#




Ohe -" "isk is a +! hard disk to store system data5 for eample5

oard software version files5 confi3uration files and lo3s#

8hat are the

functions of the

/PU@

%# nales intranet addresses within the

BSC to communicate with each other#

+# Provides routes for the operation and

maintenance of the B>S#




Che C<P oard controls and mana3es service calls in the PS

and CS fields5 and mana3es the resources of BSS.P5 BSS!Pand the system#

Its physical oard is <P1*=+5 the same as the O<P5 ut the

memory capacity is sli3htly different: %!B=CPU for the O<P5 and

+!B=CPU for the C<P5 and the Ohe UI<C is responsile for thernet Level + switch within the BC>C

and the BPS; and the mana3ement of the BC>C# >he UI<C provides the clock drive function inside the BC>C and the

BPS;# It inputs 19 and %*< si3nals5 which are sent to different slots

in the B!S; after phase lockup to provide %*< and 19 clocks for the

oards#

>he UI<C provides mana3ement interfaces for the BC>C and theBPS; it also provides oard resettin3 and resettin3 si3nal collection

functions for the BC>C and the BPS;#




UI<C

The UIMC provides one internal GE interface that is connected to

the CHUB.




C-UB

>he C-UB works to3ether with the UI<C=!UI< to e responsile for

control plane data stream echan3e and conver3ence in the system# >he control plane data from each shelf is sent to the thernet

switchin3 unit of C-UB oard throu3h the thernet cales on the

control plane#

>he data is then sent to UI<C oard of the BC>C throu3h ! for

level0+ switch5 and then distriuted to each Che /C-B% oard has three 6 uses5 on which 6 interfaces are

3rouped as 6%H15 6KH%* and 6%H+G# >he /C-B+ oard has three 6 uses5 on which 6 interfaces are

3rouped as 6+JHA+5 6AAHG( and 6G%HG*#




IC<

/esponsile for system clock supply and eternal synchroniMation#

>he oard etracts clock reference via the . interface and drivesmultiple channels of clock reference si3nals for use y each interfaceunit#

It receives !PS satellite si3nals and etract %PPS si3nals and related>O" messa3es# >he %PPS si3nals are used as reference for phaselockup in order to create PP+S5%K#**(1<-M and 1 9 clock

references for iBSC# Supports ack3round or manual selection of clock references5

includin3 BI>S5 line )1 9,5 !PS5 local )Level + or Level A, supportssoftware shieldin3 of manual switchover#

Supports four work modes: C.>C-5 >/.C5 -OL" and 6/#




IC< 1 9 reference input， when ">B=S">B+ provides the clock reference5

it connects with the 19OU>="BU!0+A+ interface of /!I<%#8hen

SPB+ provides the clock reference5 it connects with the 19OU>=CPU%0

/S+A+ interface of /SPB#

One CL9OU> interfaces outputs a one0to0si cale one shelf has two

UI<=!UI< oards with two clock sockets5 so one CL9OU> interface

can connect with three shelves# >he /C9!% oard has two CL9OU>

interfaces providin3 si clock output lines5 that is 5 it can connect with

si shelves#




SBC'

>he SBC' oard is the server oard# It mounts the server on the

rack# It provides the keyoard5 the mouse and the $!. interface#

Uses Sossaman dual0path dual0core CPU with a freNuency of +! -M#

Supports multiple operatin3 systems5 includin3 8indows

'P=+(((=+((A5 Linu and Solaris#

Provides three 6 interfaces5 two ! interfaces and one /S+A+

serial port#

Provides four universal USB interfaces#

Supports oot from hard disk and oot from USB drive#




SBC' OMC1(eth3) is set to an eternal net!or" address to co##$nicate !ith

%et%$#en M31 server. OM&1(eth') is set to an intranet address to co##$nicate !ith the OM&.




">B

Provides A+ %=>% links for eternal connections#

Supports etraction of 19 synchroniMation clock from the lines5 whichis transferred to the CL9!=IC< oard throu3h the cale as clock

reference#

Supports %+(=J impedance selection for % cales5 and supports

coaial cales and twisted0pair cales#

Supports %(( twisted0pair >% cales#

I t l U O l ▲




">B

I t l U O l ▲




">B "IP Switches

I t l U O l ▲




">B "IP Switch

;IPSwitc0

Purpose

Switc0 Configuration ;efault Location

$ode ( - * 8 ( - * 8

S%S*SK

S%+

Used to set theresistances thatmatch theimpedances of

different % paths toJ or %+( #

J O; O; O; O;

O; O; O; O;%+( O66 O66 O66 O66

SS1

Used for indicatin3the receivin3matchin3impedance ofcorrespondin3 %

chip to the CPU#

J O; O; O; O;

O; O; O; O;%+( O66 O66 O66 O66

S%(S%%

Used for reportin3the lon3=short wirestatus of each %chip to the CPU#

S-O/>-.UL

O; O; O; O;

O; O; O; O;LO;!-.UL

O66 O66 O66 O66





/">B 2umpers

On the /">B5 the % caleworks in the J unalancedcoaial transmission mode ydefault#

If the % line uses %+( alanced transmission mode5the short0circuit lock at 'KH'%*on the /">B needs to eremoved#

>he sendin3 end is 3roundedthrou3h the 4umper# >hereceivin3 end is connected to acapacitor and then 3roundedthrou3h the 4umper# 2umpers'KH'%* are used to completesuch settin3s#





/">B 2umpers

.>#.(< Pin Connection ;efinitions

%0+ Connect %Q>'（ ;） 0/ to the protection 3round )Path ;,

A0G Connect %Q/'（ ;） 0/ to the protection 3round )Path ;,

J0*Connect %Q>'（ ;%） 0/ to the protection 3round )Path;%,

01Connect %Q/'（ ;%） 0/ to the protection 3round )Path

;%,

K0%(Connect %Q>'（ ;+） 0/ to the protection 3round )Path;+,

%%0%+Connect %Q/'（ ;+） 0/ to the protection 3round )Path

;+,

%A0%GConnect %Q>'（ ;A） 0/ to the protection 3round )Path;A,

%J0%*Connect %Q/'（ ;A） 0/ to the protection 3round )Path;A,





S">B+

>he S">B+ acts as the di3ital trunk interface oard# It provides two

%JJ< S><0% standard interfaces# Supports C.S and CCS5 and provides an access processin3

capacity eNual to %+* % lines or %*1 >% lines#

Outputs one path of differential 1 9 synchronous clock si3nals for the

reference of the clock oard#





S">B+





SPB+

.ccordin3 to its functions5 the SPB+ oard can e classified into the

L.P" processin3 oard )L.P"+,5 the si3nalin3 processin3 oard )SPB+,and the ! interface processin3 oard )!IPB+,#

>he L.P"+ oard processes L.P" si3nalin3# L.P" si3nalin3 data from

the B>S are received y the ">B=SPB=SPB+ oard5 and then switched to

the L.P"+ oard throu3h the circuit switchin3 net on the UI< oard in

the local resource shelf or the !UI< oard in the local !i3ait resource

shelf# >he L.P"+ completes the processin3 of L.P" si3nalin3 data#

>he SPB+ oard processes <>P+ and '#+J protocols# It supports

etraction of 1 9 synchroniMation clock from the lines5 which is

transferred to the CL9! oard throu3h the cale as clock reference#

>he !IPB+ oard processes the 6/5 ;S and partial BSS!P protocols for

the !P/S5 and provides ! interfaces#





SPB+





SPB+

Interface unit5 which connects with the switchin3 unit and provides %

interfaces#

Circuit switch unit5 which implements the switchin3 etween interface

unit circuits and ackplane circuits#

CPU5 which implements si3nalin3 processin35 oard mana3ement and

internal connection control#

thernet Switch Unit5 which implements control plane and user plane

data switch and provides 6 interfaces#

Clock Unit5 which etracts line clock si3nals and sends them to the IC<

oard#

ach SPB+ oard contains four CPUs#

ach SPBs oard provides %* %=>% interfaces#




y

!IPI

>he !IPI oard provides IP interfaces etween iBSC and

the B>S5 the S!S; and the <SC=<!8# Implements Layer A protocol interface processin35

separates control plane data from user plane data5 and

sends the data respectively to the thernet interfaces on

the internal control plane and user plane# .ccordin3 to functions5 !IPI can e classified into four

functional oards:

.is interface !i3ait IP interface oard)IPBB,

. interface !i3ait IP interface oard IP.B)Si3nalin3, . interface !i3ait IP interface oard IPI （ si3nalin3 and service）

! interface !i3ait IP interface oard)IP!B,




y

!IPI

>he Interface Unit receives data and sends it to the service processin3

unit5 which separates user plane data from control plane data# Userplane data is then sent to the !UP+ throu3h the user plane switch

network5 and control plane data is sent to the Che !IPI oard can choose /!/ )providin3 one ! interface, or

/<I;IC )providin3 four 6 interfaces, as its rear oard#




IPI

>he IPI oard provides % or >% ased IP connection and works

to3ether with the ">B# It has no eternal interface and no rear oard#One IPI works to3ether with two ">Bs to provide up to *G % or >%

ports#




IPI >he interface unit receives -8 data and sends it to the -PS dau3hter card#

>he data is then processed accordin3 to the -"LC protocol and then sent to

the service processin3 unit# It sends user plane data throu3h the user plane

switch network to the !UP+ for processin35 and sends control plane data

throu3h the control plane switch network to the Che !UI< performs thernet Level + switchin3 etween the control plane

and the user plane in the !i3ait resource shelf5 the CS field timeslotmultiplein3 slot switchin3 and !i3ait resource shelf mana3ement# It

also provides eternal interfaces for the !i3ait resource shelf#

It has the capaility of %* 9 circuit switchin35 and provides an internal

circuit switchin3 network for the ! resource shelf#

It provides the clock drive in the resource shelf# It inputsPP+S5 19 and%*< si3nals5 which are sent to different slots in the resource shelf after

phase lockup to provide %*<5 1 9 and PP+S clocks for resource modules

in this shelf#

>he U!I< oard performs !i3ait resource shelf mana3ement and

provides /SG1J mana3ement interfaces in the !i3ait resource shelf It

also provides oard resettin3 and in0slot si3nal collection functions#




!UI<




!UP+ .ccordin3 to functions5 !UP+ oards are classified into five functional

oards: .is interface processin3 oard BIPB+5 . interface processin3 oard

.IPB5 user plane processin3 oard UPPB+5 dual rate transfer oard "/>B+and .ter interface processin3 oard >IPB+# Over the S><0% or % .is interface5 CS and PS services from the B>S are

switched to the BIPB+ oard throu3h the UI< oard in the local resource shelf orthe !UI< oard in the local !i3ait resource shelf# >he BIPB+ oard searches+(ms >/U frames or PCU frames and form them into IP packets5 which are sentto the >CU or the UPU for processin3# Over the IP .is interface5 the BIPB+oard is also used to process />P#

>he "/>B+ implements code conversion5 finishes >/.U frame conversion andrate adaptation5 and provides 6/=6/=-/=.</=>6O function#

>he .IPB oard processes />P and forms data into IP packets over the .interface#

>he UPPB+ processes user plane protocols such as BSS!P5 P"CP and !>PQU

under the .=! mode# >he >IPB+ processes user plane data of the .ter interface#




!UP+

ach !UP+ oard has %J "SPs#




!UP+

CPU: responsile for oard mana3ement5 and provides control plane

6 interfaces for eternal connection#

"SP: processes universal services5 includin3 functions of BIPB+5

.IPB5 "/>B+5 UPPB+ and >IPB+#

Circuit Switch Unit: connects the serial ports of multiple0chip "SP

with the circuit switchin3 network#

thernet Switch Unit: implements the thernet connections formultiple0chip "SP and provides the user plane 6 interface for

eternal devices#

Clock Unit: provides necessary clock si3nals for the units on the

oard#




!LI

>he !B Line Interface )!LI, oard is located at level % switchin3

susystem of iBSC# It finishes physical layer adaptation5 IP packa3eNuery5 se3mentation5 forwardin35 and flow mana3ement functions5

processes i0directional +#J!ps forwardin35 and implements the

interfaces to different resource shelves and eternal interface

functions#




!LI

Interface Unit: provides ! optical interface and supports physical

ackup# S"%HS"+5 S"AHS"G5 S"JHS"* and S"HS"1 are ackup

3roups#

Processin3 Unit: implements i0directional IP packet tale look0up5

fra3mentin35 forwardin3 and traffic mana3ement#

Rueue <ana3ement Unit: implements i0directional Nueue

mana3ement# >he ! optical interface receives user plane data from the !UI< and

sends it throu3h the ackplane to the PS; oard for user plane data

echan3e#




PS;

Provides i0directional

user plane data switch

with a capacity of G(

!ps on each direction

>he data from each !LI

oard is sent to the <atri

Switchin3 Unit throu3h

the hi3h0speed serial

links on the ackplane# It

is switched and then sent

to the destination !LI

oard#




Peripheral <onitor Unit )P<U,

Includes the P8/" oard and the alarm o P8/" is responsile for collectin3 some peripheral and environment

oard information within the cainet5 includin3 the power distriutor

and fan status as well as some environment alarms like

temperature=humidity5 smo35 water and infrared alarms# ach cainet

has one P8/" oard# >he .larm Bo ).LB, can report system alarms at different levels

accordin3 to system fault 3rades to facilitate timely interference and

handlin3 y eNuipment mana3ement personnel#




Board Summary %


S +



Board Summary +


B d S A



Board Summary A


C t l Pl d U Pl I t ti



Control Plane and User Plane Interconnection


. ti =St d B d " i



.ctive=Standy Board "esi3n 9ey oards have %% ackup#

9ey interface oards such as !IPI and S">B can have%% ackup if necessary#

!LI and PS; oards work in the load sharin3 mode#


! l " i ti f B d



!eneral "escription of Boards

6ront oard and rear oard

/ear oards are passive oards that provides calin3 fromthe ackplane )such as % and network cales, in order to

work to3ether with correspondin3 front oards#

6ront oards are physical oards that process resources#

.ll system optical cales are led from the front oard

panels#

.ll front oards have four indicators on their panels

)/U;5 ;U<5 .C>5 .L<, to indicate oard status#


I di t B d P l



Indicators on Board Panels

Indicator Color $eaning ;escription

/U; !reen /unnin3indicator

6lashin3 at % -M: the oard is runnin3 normally

6lashin3 at J -M: version downloadin3 is in process#

.L< /ed .larmindicator

6lashin3 at J -M: version download fails oard self testfails ecause of inconsistency etween oard andconfi3uration

;U< 7ellowBoardetractionindicator

Solid on: the microswitch is opened the oard is not inposition or version files are not downloaded#

6lashin3 at J -M )Nuickly,: the microswitch 3enerates analarm ecause it is opened when the oard is still runnin3#

6lashin3 at % -M )slowly,: the oard can e etracted# >hemicroswitch is opened when the oard is runnin35 and the

oard is in standy mode or release the resource#

Solid off: the microswitch is normal#

.C> !reen .ctive=standy statusindicator

On: the oard is active#

Off: the oard is standy#


C



Contents








iBSC L i l $i



iBSC Lo3ical $iew


iBSC t l Ph i l I t f



iBSC ternal Physical Interfaces


.ccess Unit .is Interface Unit )BIU,



.ccess Unit H .is Interface Unit )BIU,

% .is % orne >"< link

IP .is 6=! orne IP link

IPo .is % orne IP link


BIU % .is



BIU 0 % .is

The interface oard can e the TB or *TB+ oard. The access capacit,

of *TB+ is fo$r ti#es that of the TB.


BIU IP .is



BIU 0 IP .is


BIU IPo .is



BIU 0 IPo .is


.ccess Unit . Interface Unit ).IU,



.ccess Unit 0 . Interface Unit ).IU,

% . % orne >"< link

IP . 6=! orne IP link


.IU % .



.IU 0 % .


.IU IP .



.IU 0 IP .


.ccess Unit ! Interface Unit )!IU,



.ccess Unit H ! Interface Unit )!IU,

% ! % orne >"< link

IP ! 6=! orne IP link


!IU % !



!IU 0 % !


!IU IP !



!IU 0 IP !


OD< Unit



OD< Unit

Ohe networkin3 mode of SBC' is as follows: iBSC Ohe SBC')omc% port,5 O<<=<S Client and <S Server form a sunet# >he

local O<< usually consists of the SBC' )O<< Server,5 the O<<

Client )PC,#

8hen the iBSC needs to mana3e S"/ B>Ss5 the O<CB server

mana3es all S"/ confi3urations )physical5 transmission and radioconfi3urations,5 links5 alarms and versions# >he O<CB pro3ram is

installed on the SBC' and a pair of !IPI oards must e confi3ured#







Processin3 Units D <onitorin3 Units



Processin3 Units D <onitorin3 Units

Processin3 Unit 0 C<PU Che P8/" oard collects the environment monitorin3 information

of peripheral devices5 includin3 temperature and humidity5 smoke5

water and infrared alarms#


UPU D >CU



UPU D >CU

Processin3 Unit H UPU UPPB+: Processes PS protocols

>ransCoder Unit H >CU "/>B+: code transfer and rate adaptation


IP Switch Unit )PSU,




Level % switch: !LI and PS;5 G(! lar3e0capacity user plane data switch#

Level + switch: UI<U5!UI<5 UI<C5 and C-UB5 responsile for the switch andconver3ence of control plane and user plane data in the system#






If there are only two resource shelves5 the Level0% switch susystem

is not needed on the user plane# >he two resource shelves can edirectly interconnected usin3 !i3ait optical interfaces#


Contents



Contents








User Plane Si3nal 6low in the CS "omain



User Plane Si3nal 6low in the CS "omain

>he BIU severs user plane data from control plane data5 and then

sends user plane data to the >CU5 which processes such dataand then sends it to the .IU# Si3nal flow %+#


User Plane Si3nal 6low in the PS "omain



User Plane Si3nal 6low in the PS "omain

>he BIU severs CPU frames from all frames and sends them to

the UPU)UPPB+, throu3h the user plane switchin3 network# >heUPU then separates PS field user plane data from CPU frames

received for further processin3# .fter data processin3 is complete5

the data is sent to the !IU throu3h the user plane switchin3

network#


Control Plane Si3nal 6low in the CS "omain



Control Plane Si3nal 6low in the CS "omain .is interface si3nal flow .is interface unit )BIU, sends si3nalin3 in the

L.P" channel to the Che C<P

processes such data and sends some of it directly ack to the BIU )flowdirection: %%,# Some si3nalin3 data will e sent to the .IU in the form of

.0interface si3nalin3 flow )flow direction: %+,#

.0interface si3nal flow: >he .IU processes the <>P+ part of .0interface

si3nalin35 and then sends it to the CPA and layers aove# Some 3loal processes need the participation

of the O<P# >he data flow direction is +AA+ or ++#


Control Plane Si3nal 6low in the PS "omain



Control Plane Si3nal 6low in the PS "omain 6or some control plane si3nalin3 in the PS field5 the system

reNuests resources from the C<P oard5 and then sends the

si3nalin3 to the UPPB+ for processin3#

8hen the <S is processin3 PS services5 control plane si3nalin3

should e separated from UPPB+ and then sent to the Che .is interface unit sent )BIU, sent control plane data in the

L.P" channel to the Che C<P processes such

data5 such as the immediate assi3nment messa3e5 and sends

it directly ack to the BIU )flow direction: %%,# Some data5

such as the packet assi3nment messa3e5 are sent to the UPU5

which processes then and send them to the BIU throu3h the

user plane switchin3 network )flow direction:: %A+,# "ata from the .is interface unit are sent to the UPU throu3h

the user plane switchin3 network# >he UPU processes the data

and separates control si3nalin3 packets5 which are sent to the

control plane processin3 oard )C<P,# >he data flow direction

is: +AA+






! interface si3nalin3 flow >he !IU sends B$C channel data as control plane data to the

active C<P# >he CP B$C restart, to other C<Ps and some )such

as si3nalin3 B$C restart, to the O<P# >he CP B$C restart acknowled3ement and si3nalin3

B$C restart acknowled3ement5 is sent to the ! interface

throu3h the !UI5 with the data flow as JJ or **#

>he !UI routes data from other B$C channels to the user

plane processin3 unit5 which separates control plane data andsends it to the C<P# >he CP pa3in3 messa3es5 is sent to the !

interface throu3h the !IU with the data flow as GAJ

some si3nalin3 3enerates the .is si3nalin3 flow5 such as

location messa3es5 with the data flow as GA%#


User Plane Board Si3nal 6low in the CS "omain




% .is， % .

>he BIU severs user plane data from control plane data5 and then sends userplane data to the >CU5 which processes such data and then sends it to the

.IU#


Control Plane Board Si3nal 6low in the CS "omain



3

% .is， % .

>he .is interface unit )BIU, sends si3nalin3 in the L.P" channel to the C<Poard as control plane data# >he Che BIU severs user plane data from control plane data5 and then sends userplane data to the >CU5 which processes such data and then sends it to the

.IU#


Control Plane Board Si3nal 6low in the CS "omain



3

IP .is， IP .

>he .is interface unit )BIU, sends si3nalin3 in the L.P" channel to the C<Poard as control plane data# >he Che BIU severs CPU frames from all frames and sends them to the UPU)UPPB, throu3hthe user plane switchin3 network# >he UPU then separates PS field user plane data from

CPU frames received for further processin3# .fter data processin3 is complete5 the data

is sent to the !UI throu3h the user plane switchin3 network#


Control Plane Board Si3nal 6low in the PS "omain



3

% .is， % !

>he .is interface unit )BIU, sends control plane data in the L.P" channel to the C<Poard# >he Che UPU processes such data and then sends it to the BIU

throu3h the user plane switch network#





3

% .is， % !

>he !IU sends B$C channel data as control plane data to the main C<P# >heChe BIU severs PCU frames from all frames and sends them to the UPU)UPPBs,throu3h the user plane switchin3 network# >he UPU then separates PS field user plane

data from CPU frames received for further processin3# .fter data processin3 is complete5

the data is sent to the !UI throu3h the user plane switchin3 network#





IP .is IP !

>he .is interface unit )BIU, sends control plane data in the L.P" channel to theChe Che UPU processes such data and then

sends it to the BIU throu3h the user plane switch network#





IP .is IP !

>he !IU sends B$C channel data as control plane data to the main C<P# >he C<Pprocesses the data and some si3nalin3 3enerates the .is si3nalin3 flow5 such as pa3in3

messa3es in the PS or CS field


Contents










System Interconnection <odes



<ost oards are mana3ed y the Ohe CL9!=IC< oard are connected to the UI<C via the /SG1J us5 and

then mana3ed y the O<P#

>he P8/" oard is directly mana3ed y the Ohe CL9 oard is responsile

for supplyin3 clock si3nals and

eternal synchroniMationfunctions#

Clock level: Level A clock

>he oard etracts clock

reference via . Iu interface and

drives multiple channels of

timin3 reference si3nals for

use y each interface shelf

after intra0oard

synchroniMation#

Level + forwardin3 of the UI<

oard

">B5 S">B+ and SPB+ can

e used to etract linereference

>he BPS; does not need a

clock reference


Intra0shelf Cale Connection



Clock etraction and distriution cales

Control plane and thernet interconnection cales User plane optical cale connection

<onitorin3 cale#


Clock traction and "istriution Cales



>he clock etraction cale

connects the 19OU> interfaceon the ">B rear oard to the

19I; interface on the IC<#

>he IC< can also etract !PS

si3nals as the clock reference#

>he clock distriution calesconnect the CL9OU>

interface on the IC< rear

oard to the CL9I; interfaces

on UI< oards in each shelf#

>o use the clock reference of

the . interface5 please etract

it from the %st % of the .

interface#


Control Plane and thernet Interconnection Cales



>he 6 interfaces of the

C-UB rear oardsconnect to the 6

interfaces of the UI<

oards in each shelf#

Internal ! connection is

used inside the BC>C#


User Plane Optical Cale Connection



>he optical interface on the

!UI< front panel in theB!S; connects to the

optical interface on the PLI

front panel#

Supports physical ackup#


<onitorin3 Cales



>he cales etween fans to P8/"

oards are usually %+( ohmtwisted0pair cales that are

connected to the 6.;BO'

interfaces to monitor fan runnin3

status#

>he environment monitorin3 sensoris connected to the S;SO/S

interface on the P8/" oard to

collect environment alarms#

>he door access sensor is

connected to the "OO/ interface

on the P8/" oard to monitordoor access status#

>he P8/" oard reports

monitorin3 information to the O<P

oard via /SG1J cales#


/eview



8hat eternal interfaces does iBSC provide ？8hat transmission

modes do those interfaces adopt ？

-ow many types of shelves does iBSC have ？8hat are the

maimum confi3uration and the minimum confi3uration

respectively ？

8hat is the hardware structure of iBSC@ Please make a drawin3 of

the hardware structure#

8hat are oard si3nal flows of iBSC CS control plane and PS user

plane@ Please make a drawin3 of the oard si3nal flows#

Documents

V3 Backup Document G_TM_iBSC System Structure and Principle_R1.0