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8/4/2019 V2 ColdFire Core - opening the door to 32-bit control
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V2 ColdFire Core
opening the door to 32-bit controller
8/4/2019 V2 ColdFire Core - opening the door to 32-bit control
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Contents
Introduction to ColdFire controller
Why V2 ColdFire?
Key Features
Architecture of V2 ColdFire
Ecosystem
Software ToolsApplications
Benefits and Advantages
Conclusion
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Introductiony In 1994, the innovative ColdFire family was added to Freescale 's
legacy 68K family tree.
y Freescale evaluated high-level source code from many 68K
embedded systems customers.
y The variable-length RISC ColdFire architecture gives customers
greater flexibility to lower memory and system costs.
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Intro
1. Core architecture (V2) is available as synthesizable
intellectual property for ASIC design. Runs up to 166
MHz.
2. The V2 ColdFire is available in choice of two different
design packages:
y V2 ColdFire Core: 32-bit address/data processor core with integrated
debug module
y V2 ColdFire Standard Product Platform (SPP): The V2 ColdFire Core
integrated with a set of tested and proven peripherals
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Why V2 ColdFire?
y RISC performance
y High Code density
y On-Chip memory
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Key Features
Features of the V2 ColdFire Core include:
y Variable-length RISC, clock-multiplied core
y 166-MHz in typical 130-nm process
y Independent, decoupled pipelines:
2-stage instruction fetch pipeline (IFP)
2-stage operand execution pipeline (OEP)
FIFO instruction buffer is the decoupling mechanism
y 16 user-accessible, 32-bit general purpose registers (GPRs)y Integrated cache controller
y Integrated SRAM controller
y 100% synthesizable and technology-independent design
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Architecture of V2 ColdFire Core
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Programming model
The ColdFire2/2M programming model consists of three registergroups:
INTEGER unit user programming model
i. 16 General-purpose 32-bit registers (D0 D7, A0 A7)
ii. 32-bit Program Counter (PC)
iii. 8-bit Condition Code Register (CCR)
MA
C unit user programming modeli. 32-bit accumulator (ACC)
ii. 16-bit mask register (MASK)
iii. 8-bit MAC status register (MACSR)
SUPERVISOR programming model
i. Status Register (SR)
ii. Cache Control Register (CACR)iii. Access Control Register 0 (ACR0, ACR1)
iv. Vector Base Register (VBR)
v. ROM Base Address Register (ROMBAR0)
vi. SRAM Base Address Register (RAMBAR0)
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Ecosystems
y World-class development tools suites offered through leading tools
developers.
y Also supported are a rich set of real time operating systems, stacks,
and drivers from Freescale partners, who include:
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Software Tools
y
CodeWarrior Development Studio
y ColdFire Flash/EEPROM Programmer
y ColdFire In-Circuit Debugger
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Applications
y Portable Internet Audio Products
y Local Medical Monitoring Gateway
y HVAC and Security Control Panel
y Music Media Player
y
Digital Set-Top Box
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Portable InternetAudio Products
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HVAC and Security Control Panel
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Local Medical Monitoring Gateway
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Benefits andAdvantages
y Memory costsVariable-length RISC Instruction set optimized for code density.
Requires substantially less memory then fixed length RISCs.
y Low CUP cost
Small gate count..MAC/EMAC often eliminates need for an additional DSP.
y High performance RISC-based Micro Architecture
Simple instruction set.
Single cycle execution of most instruction.
y Low Risk
The richest development tool ecosystem.
Compatible with and proven in a installed base.
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Conclusion
The ColdFire Architecture is ubiquitous in consumer and
industrial applications, which means a massive base of
existing application code. ColdFire controllers continue
to set the pace for the embedded marketfrom
industrial automation systems to inkjet printers andmedia players.
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References
Much of the material in this set of slides was borrowed from the
following sources:
y ColdFire User Manual.
y
ColdFire V2 Core Reference Manual.y MCF521x ColdFire Microcontroller Data Sheet.
y http://www.pemicro.com/support/forums_index.cfm
y http://www.ip-extreme.com/video/coldfire_family_video.html
y Prof. Yann-Hang Lee, Dept. of Computer Science & Engineering,
Arizona State University, CSE325 Course Slides.
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