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MC33204
MC33204
MC33204
MC33204
IC1A
IC1B
IC1C
IC1D
+
12 --
3 +
INPU
T
Virtual Ground
C1
0.1u
F
47k
1M
GND
C2 4.7uF
413 --
12 +
14
11
+12V
20k
20k
20k
8
7
1k
680
560k
V-GND
0.0022uF
0.0022uF
TREBLE (~3kHz)
9
10
--
+
V-GND
680
1k
0.01uF
0.01uF
560k
6
5 +
--
MID (~900Hz)
V-GND
1k
680
0.047uF
0.047uF
560k
BASS (~100Hz)
+
2.2uF
39k
1N4002
1uF
100k
2N3904
1k
1kYellow LEDs
+12V
+
2.2uF
39k
1N4002
4.7uF
100k
2N3904
470
470
+12V
RED LEDs
+
+
2.2uF 1N4002
39k
100k
2N3904+
+ 22uF
+12V
BLUE LEDs
18
3+
2--4
V-GND
+12VV+
100k
100k
0.1u
F
MC34072P
(important note) use this wiring diagram for ICS if you are using MC34072 (dual op amp)
2--
3+7
6
4
+12V
V-GND
V+
100k
100k
0.1u
F
TS921
(original wiring) Virtual Ground
160
160
1/10
RAIL TO RAIL INPUT AND OUTPUT LOW NOISE : 9nV/√(Hz) LOW DISTORTION HIGH OUTPUT CURRENT : 80mA
(able to drive 32Ω loads) HIGH SPEED : 4MHz, 1V/µs OPERATING FROM 2.7V to 12V ESD INTERNAL PROTECTION : 1.5KV LATCH-UP IMMUNITY MACROMODEL INCLUDED IN THIS SPECI-
FICATION
DESCRIPTION
The TS921 is a RAIL TO RAIL single BiCMOSoperational amplifier optimized and fully specifiedfor 3V and 5V operation.High output current allows low load impedances tobe driven.The TS921 exhibits a very low noise, low distor-tion, low offset and high ouput current capabilitymaking this device an excellent choice for highquality, low voltage or battery operated audio sys-tems.The device is stable for capacitive loads up to500pF.
APPLICATIONS
headphone amplifier piezoelectric speaker driver sound cards, multimedia systems line driver, actuator driver servo amplifier mobile phone and portable communication
sets instrumentation with low noise as key factor
ORDER CODE
N = Dual in Line Package (DIP)D = Small Outline Package (SO) - also available in Tape & Reel (DT)P = Thin Shrink Small Outline Package (TSSOP) - only available in Tape & Reel (PT)
PIN CONNECTIONS (top view)
Part Number
Temperature Range
Package
N D P
TS921I -40°C, +125°C • • •
NDIP8
(Plastic Package)
DSO8
(Plastic Micropackage)
PTSSOP8
(Thin Shrink Small Outline Package)
1
2
3
4 5
6
7
8
-
+
Inverting Input
N.C.
Non-inverting Input
VCC
VCC+
Output
N.C.
N.C.
TS921RAIL TO RAIL HIGH OUTPUT CURRENT
SINGLE OPERATIONAL AMPLIFIER
February 2001
TS921
2/10
ABSOLUTE MAXIMUM RATINGS
OPERATING CONDITIONS
Symbol Parameter Value Unit
VCC Supply voltage 1) 14 V
Vid Differential Input Voltage 2) ±1 V
Vi Input Voltage 3) -0.3 to 14 V
Toper Operating Free Air Temperature Range -40 to +125 °C
Istg Storage Temperature -65 to +150 °C
Tj Maximum Junction Temperature 150 °C
Output Short Circuit Duration see note 4) °C1. All voltages values, except differential voltage are with respect to network ground terminal.2. Differential voltagesare the non-inverting input terminal with respect to the inverting input terminal.3. The magnitude of input and output voltages must never exceed VCC
+ +0.3V.4. Short-circuits can cause excessive heating. Destructive dissipation can result from simultaneous short-circuit on all amplifiers
Symbol Parameter Value Unit
VCC Supply voltage 2.7 to 12 V
Vicm Common Mode Input Voltage Range VCC- -0.2 to VCC
+ +0.2 V
TS921
3/10
ELECTRICAL CHARACTERISTICSVCC
+ = 3V, Tamb = 25°C (unless otherwise specified)
Symbol Parameter Min. Typ. Max. Unit
VioInput Offset Voltage
Tmin. ≤ Tamb ≤ Tmax.35
mV
DVio Input Offset Voltage Drift 2 µV/°C
IioInput Offset Current
Vout = 1.5V 30nA
IibInput Bias Current
Vout = 1.5V 15 100nA
VOHHigh Level Output Voltage RL = 600Ω
RL = 32Ω2.87
2.63V
VOLLow Level Output Voltage RL = 600Ω
RL = 32Ω 180100
mV
AvdLarge Signal Voltage Gain (Vout = 2Vpk-pk) RL = 600Ω
RL = 32Ω3516
V/mV
ICCSupply Current no load, Vout = Vcc/2 1 1.5
mA
GBPGain Bandwith Product
RL = 600Ω 4MHz
CMR Common Mode Rejection Ratio 60 80 dB
SVRSupply Voltage Rejection RatioVcc = 2.7 to 3.3 V 60 80
dB
Io Output Short Circuit Current 50 80 mA
SR Slew Rate 0.7 1.3 V/µs
φmPhase Margin at Unit Gain
RL = 600Ω, CL =100pF 68Degrees
GmGain Margin
RL = 600Ω, CL =100pF 12dB
enEquivalent Input Noise Voltage
f = 1kHz 9
THDTotal Harmonic Distortion
Vout = 2Vpk-pk, F = 1kHz, Av = 1, RL =600Ω 0.005%
nV
Hz------------
TS921
4/10
ELECTRICAL CHARACTERISTICSVCC
+ = 5V, Tamb = 25°C (unless otherwise specified)
Symbol Parameter Min. Typ. Max. Unit
VioInput Offset Voltage
Tmin. ≤ Tamb ≤ Tmax.
35
mV
DVio Input Offset Voltage Drift 2 µV/°C
IioInput Offset Current
Vout = 1.5V 30nA
IibInput Bias Current
Vout = 1.5V 15 100nA
VOHHigh Level Output Voltage RL = 600Ω
RL = 32Ω4.85
4.4V
VOLLow Level Output Voltage RL = 600Ω
RL = 32Ω 300120
mV
AvdLarge Signal Voltage Gain (Vout = 2Vpk-Vpk) RL = 600Ω
RL = 32Ω3516
V/mV
IccSupply Current
no load, Vout = Vcc/2 1 1.5mA
GBPGain Bandwith Product
RL = 600Ω 4MHz
CMR Common Mode Rejection Ratio 60 80 dB
SVRSupply Voltage Rejection Ratio
Vcc = 4.5 to 5.5V 60 80dB
Io Output Short Circuit Current 50 80 mA
SR Slew Rate 0.7 1.3 V/µs
φmPhase Margin at Unit Gain
RL = 600Ω, CL =100pF 68Degrees
GmGain Margin
RL = 600Ω, CL =100pF 12dB
enEquivalent Input Noise Voltage
f = 1kHz9
THDTotal Harmonic Distortion
Vout = 2Vpk-pk, F = 1kHz, Av = 1, RL =600Ω 0.005%
nV
Hz------------
TS921
5/10
MACROMODELS
** Standard Linear Ics Macromodels, 1996.** CONNECTIONS :* 1 INVERTING INPUT* 2 NON-INVERTING INPUT* 3 OUTPUT* 4 POSITIVE POWER SUPPLY* 5 NEGATIVE POWER SUPPLY
.SUBCKT TS921 1 3 2 4 5 (analog) ********************************************************* .MODEL MDTH D IS=1E-8 KF=2.664234E-16 CJO=10F* INPUT STAGECIP 2 5 1.000000E-12CIN 1 5 1.000000E-12EIP 10 5 2 5 1EIN 16 5 1 5 1RIP 10 11 8.125000E+00RIN 15 16 8.125000E+00RIS 11 15 2.238465E+02DIP 11 12 MDTH 400E-12DIN 15 14 MDTH 400E-12VOFP 12 13 DC 153.5uVOFN 13 14 DC 0IPOL 13 5 3.200000E-05CPS 11 15 1e-9DINN 17 13 MDTH 400E-12VIN 17 5 -0.100000e+00DINR 15 18 MDTH 400E-12VIP 4 18 0.400000E+00FCP 4 5 VOFP 1.865000E+02FCN 5 4 VOFN 1.865000E+02FIBP 2 5 VOFP 6.250000E-03FIBN 5 1 VOFN 6.250000E-03* GM1 STAGE ***************FGM1P 119 5 VOFP 1.1FGM1N 119 5 VOFN 1.1RAP 119 4 2.6E+06RAN 119 5 2.6E+06* GM2 STAGE *************** G2P 19 5 119 5 1.92E-02
G2N 19 5 119 4 1.92E-02R2P 19 4 1E+07R2N 19 5 1E+07**************************VINT1 500 0 5GCONVP 500 501 119 4 19.38 !envoie ds VP, I(VP)=(V119-V4)/2/Ut VP 501 0 0GCONVN 500 502 119 5 19.38 !envoie ds VN, I(VN)=(V119-V5)/2/Ut VN 502 0 0********* orientation isink isource *******VINT2 503 0 5FCOPY 503 504 VOUT 1DCOPYP 504 505 MDTH 400E-9VCOPYP 505 0 0DCOPYN 506 504 MDTH 400E-9VCOPYN 0 506 0***************************F2PP 19 5 poly(2) VCOPYP VP 0 0 0 0 0.5 !multiplie I(vout)*I(VP)=Iout*(V119-V4)/2/UtF2PN 19 5 poly(2) VCOPYP VN 0 0 0 0 0.5 !multiplie I(vout)*I(VN)=Iout*(V119-V5)/2/UtF2NP 19 5 poly(2) VCOPYN VP 0 0 0 0 1.75 !multiplie I(vout)*I(VP)=Iout*(V119-V4)/2/UtF2NN 19 5 poly(2) VCOPYN VN 0 0 0 0 1.75 !multiplie I(vout)*I(VN)=Iout*(V119-V5)/2/Ut* COMPENSATION ************CC 19 119 25p* OUTPUT***********DOPM 19 22 MDTH 400E-12DONM 21 19 MDTH 400E-12HOPM 22 28 VOUT 6.250000E+02VIPM 28 4 5.000000E+01HONM 21 27 VOUT 6.250000E+02VINM 5 27 5.000000E+01VOUT 3 23 0ROUT 23 19 6COUT 3 5 1.300000E-10DOP 19 25 MDTH 400E-12VOP 4 25 1.052DON 24 19 MDTH 400E-12VON 24 5 1.052.ENDS
ELECTRICAL CHARACTERISTICSVCC
+ = 3V, VCC- = 0V, RL, CL connected to VCC/2, Tamb = 25°C (unless otherwise specified)
Symbol Conditions Value Unit
Vio 0 mV
Avd RL = 10kΩ 200 V/mV
ICC No load, per operator 1.2 mA
Vicm -0.2 to 3.2 V
VOH RL = 10kΩ 2.95 V
VOL RL = 10kΩ 25 mV
Isink VO = 3V 80 mA
Isource VO = 0V 80 mA
GBP RL = 600kΩ 4 MHz
SR RL = 10kΩ, CL = 100pF 1.3 V/µs
φm RL = 600kΩ 68 Degrees
TS921
6/10
OUTPUT SHORT CIRCUIT CURRENT vs OUTPUT VOLTAGE
OUTPUT SHORT CIRCUIT CURRENT vs OUTPUT VOLTAGE
OUTPUT SUPPLY CURRENT vs SUPPLY VOLTAGE
VOLTAGE GAIN AND PHASE vs FREQUENCY
EQUIVALENT INPUT NOISE VOLTAGE vs FREQUENCY
THD + NOISE vs FREQUENCY
0 1 2 3 4 5-120
-100
-80
-60
-40
-20
0
20
40
60
80
100
Output Voltage (V)
Out
putS
hort
-Cir
cuit
Cur
rent
(mA)
Source
Sink
Vcc=0/5V
0 0,5 1 1,5 2 2,5 3-100
-80
-60
-40
-20
0
20
40
60
80
100
Output Voltage (V)
Ou
tpu
tS
ho
rt-C
ircu
itC
urr
en
t(m
A)
Source
Sink
Vcc=0/3V
1E+02 1E+03 1E+04 1E+05 1E+06 1E+07 1E+08-20
0
20
40
60
-60
0
60
120
180
Frequency (Hz)
Gai
n(d
B)
Ph
ase
(De
g)
gain
phase
Rl=10kCl=100pF
0.01 0.1 1 10 100
Frequency (kHz)
0
5
10
15
20
25
30
Equ
ival
entI
nput
Noi
se(n
V/s
qrt(
Hz)
VCC=±1.5VRL=100Ω
0.01 0.1 1 10 100
Frequency (kHz)
0
0.005
0.01
0.015
0.02
TH
D+N
oise
(%)
RL=2k Vo=10VppVCC=±6V Av= 1
TS921
7/10
THD + NOISE vs FREQUENCY
THD + NOISE vs FREQUENCY
THD + NOISE vs OUTPUT VOLTAGE
THD + NOISE vs OUTPUT VOLTAGE
THD + NOISE vs OUTPUT VOLTAGE
OPEN LOOP GAIN AND PHASE vs FREQUENCY
0.01 0.1 1 10 100
Frequency (kHz)
0
0.008
0.016
0.024
0.032
0.04
TH
D+N
oise
(%) RL=32Ω Vo=4Vpp
VCC=±2.5V Av= 1
0.01 0.1 1 10 100
Frequency (kHz)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
TH
D+N
oise
(%)
RL=32Ω Vo=2VppVCC=±1.5V Av= 10
0 0,2 0,4 0,6 0,8 1 1,20,001
0,010
0,100
1,000
10,000
Vout (Vrms)
THD
+No
ise
(%)
RL=600Ω f=1kHzVCC=0/3V Av= -1
0 0.2 0.4 0.6 0.8 1
Vout (Vrms)
0.01
0.1
1
10
TH
D+N
ois
e(%
) RL=32Ω f=1kHzVCC=±1.5V Av= -1
0 0.2 0.4 0.6 0.8 1 1.2
Vout (Vrms)
0.001
0.01
0.1
1
10
TH
D+
Noi
se(%
) RL=2kΩ f=1kHzVCC=±1.5V Av= -1
1E+2 1E+3 1E+4 1E+5 1E+6 1E+7 1E+8
Frequency (Hz)
0
10
20
30
40
50
Gai
n(d
B)
0
60
120
180
Pha
se(D
eg)
CL=500pF
TS921
8/10
PACKAGE MECHANICAL DATA8 PINS - PLASTIC DIP
Dim.Millimeters Inches
Min. Typ. Max. Min. Typ. Max.
A 3.32 0.131
a1 0.51 0.020
B 1.15 1.65 0.045 0.065
b 0.356 0.55 0.014 0.022
b1 0.204 0.304 0.008 0.012
D 10.92 0.430
E 7.95 9.75 0.313 0.384
e 2.54 0.100
e3 7.62 0.300
e4 7.62 0.300
F 6.6 0260
i 5.08 0.200
L 3.18 3.81 0.125 0.150
Z 1.52 0.060
TS921
9/10
PACKAGE MECHANICAL DATA8 PINS - PLASTIC MICROPACKAGE (SO)
Dim.Millimeters Inches
Min. Typ. Max. Min. Typ. Max.
A 1.75 0.069
a1 0.1 0.25 0.004 0.010
a2 1.65 0.065
a3 0.65 0.85 0.026 0.033
b 0.35 0.48 0.014 0.019
b1 0.19 0.25 0.007 0.010
C 0.25 0.5 0.010 0.020
c1 45° (typ.)
D 4.8 5.0 0.189 0.197
E 5.8 6.2 0.228 0.244
e 1.27 0.050
e3 3.81 0.150
F 3.8 4.0 0.150 0.157
L 0.4 1.27 0.016 0.050
M 0.6 0.024
S 8° (max.)
TS921
10/10
PACKAGE MECHANICAL DATA8 PINS - THIN SHRINK SMALL OUTLINE PACKAGE
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result fromits use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specificationsmentioned in this publication are subject to change without notice. This publication supersedes and replaces all informationpreviously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices orsystems without express written approval of STMicroelectronics.
© The ST logo is a registered trademark of STMicroelectronics
© 2001 STMicroelectronics - Printed in Italy - All Rights ReservedSTMicroelectronics GROUP OF COMPANIES
Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom
© http://www.st.com
Dim.Millimeters Inches
Min. Typ. Max. Min. Typ. Max.
A 1.20 0.05
A1 0.05 0.15 0.01 0.006
A2 0.80 1.00 1.05 0.031 0.039 0.041
b 0.19 0.30 0.007 0.15
c 0.09 0.20 0.003 0.012
D 2.90 3.00 3.10 0.114 0.118 0.122
E 6.40 0.252
E1 4.30 4.40 4.50 0.169 0.173 0.177
e 0.65 0.025
k 0° 8° 0° 8°
l 0.50 0.60 0.75 0.09 0.0236 0.030
L 0.45 0.600 0.75 0.018 0.024 0.030
L1 1.000 0.039
C
L
14
85
L1
c0.25mm.010 inch
GAGE PLANE
E1
k
LL1
E
SE
ATIN
GP
LAN
E
A
A2
D
A1
b
5
8
4
1
PIN 1 IDENTIFICATION
e
Semiconductor Components Industries, LLC, 2004
January, 2004 − Rev. 61 Publication Order Number:
MC34071/D
MC34071,2,4,AMC33071,2,4,A
Single Supply 3.0 V to 44 VOperational Amplifiers
Quality bipolar fabrication with innovative design concepts areemployed for the MC33071/72/74, MC34071/72/74 series ofmonolithic operational amplifiers. This series of operationalamplifiers offer 4.5 MHz of gain bandwidth product, 13 V/s slew rateand fast settling time without the use of JFET device technology.Although this series can be operated from split supplies, it isparticularly suited for single supply operation, since the commonmode input voltage range includes ground potential (VEE). With aDarlington input stage, this series exhibits high input resistance, lowinput offset voltage and high gain. The all NPN output stage,characterized by no deadband crossover distortion and large outputvoltage swing, provides high capacitance drive capability, excellentphase and gain margins, low open loop high frequency outputimpedance and symmetrical source/sink AC frequency response.
The MC33071/72/74, MC34071/72/74 series of devices areavailable in standard or prime performance (A Suffix) grades and arespecified over the commercial, industrial/vehicular or militarytemperature ranges. The complete series of single, dual and quadoperational amplifiers are available in plastic DIP, SOIC and TSSOPsurface mount packages.• Wide Bandwidth: 4.5 MHz
• High Slew Rate: 13 V/s
• Fast Settling Time: 1.1 s to 0.1%
• Wide Single Supply Operation: 3.0 V to 44 V
• Wide Input Common Mode Voltage Range: Includes Ground (VEE)
• Low Input Offset Voltage: 3.0 mV Maximum (A Suffix)
• Large Output Voltage Swing: −14.7 V to +14 V (with ±15 VSupplies)
• Large Capacitance Drive Capability: 0 pF to 10,000 pF
• Low Total Harmonic Distortion: 0.02%
• Excellent Phase Margin: 60°• Excellent Gain Margin: 12 dB
• Output Short Circuit Protection
• ESD Diodes/Clamps Provide Input Protection for Dual and Quad
• Pb−Free Package May be Available. The G−Suffix Denotes aPb−Free Lead Finish
http://onsemi.com
See detailed ordering and shipping information in the packagedimensions section on page 17 of this data sheet.
ORDERING INFORMATION
PDIP−8P SUFFIXCASE 626
18
SO−8D SUFFIXCASE 751
1
8
PDIP−14P SUFFIXCASE 646
1
14
SO−14D SUFFIX
CASE 751A1
14
TSSOP−14DTB SUFFIXCASE 948G
114
See general marking information in the device markingsection on page 18 of this data sheet.
DEVICE MARKING INFORMATION
http://onsemi.com
MC34071,2,4,A MC33071,2,4,A
http://onsemi.com2
CASE 626/CASE 751
PIN CONNECTIONS
(Single, Top View)
(Dual, Top View)
Offset Null
VEE
NC
VCC
Output
Offset Null
Inputs
VEE
Inputs 1
Inputs 2
Output 2
Output 1 VCC
−
1
2
3
4
8
7
6
5
−
−
+
+
1
2
3
4
8
7
6
5
+ Inputs 1
Output 1
VCC
Inputs 2
Output 2
Output 4
Inputs 4
VEE
Inputs 3
Output 3
(Quad, Top View)
4
2 3
1
1
2
3
4
5
6
7 8
9
10
11
12
13
14
−+
−+
+−
+
−
CASE 646/CASE 751A/CASE 948G
Offset Null(MC33071, MC34071 only)
Q1
Q2
Q3 Q4 Q5 Q6 Q7
Q17
Q18D2
C2 D3
R6 R7
R8
R5
Q15 Q16Q14Q13
Q11Q10
R2C1R1
Q9Q8
Q12
D1
R3 R4
Inputs
VCC
Output
CurrentLimit
VEE/Gnd
BaseCurrent
Cancellation
−
+
Q19
Bias
Figure 1. Representative Schematic Diagram(Each Amplifier)
MAXIMUM RATINGS
Rating Symbol Value Unit
Supply Voltage (from VEE to VCC) VS +44 V
Input Differential Voltage Range VIDR Note 1 V
Input Voltage Range VIR Note 1 V
Output Short Circuit Duration (Note 2) tSC Indefinite sec
Operating Junction Temperature TJ +150 °C
Storage Temperature Range Tstg −60 to +150 °C
1. Either or both input voltages should not exceed the magnitude of VCC or VEE.2. Power dissipation must be considered to ensure maximum junction temperature (TJ) is not exceeded (see Figure 2).
MC34071,2,4,A MC33071,2,4,A
http://onsemi.com3
ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = −15 V, RL = connected to ground, unless otherwise noted. See Note 3 forTA = Tlow to Thigh)
A Suffix Non−Suffix
Characteristics Symbol Min Typ Max Min Typ Max Unit
Input Offset Voltage (RS = 100 , VCM = 0 V, VO = 0 V)VCC = +15 V, VEE = −15 V, TA = +25°CVCC = +5.0 V, VEE = 0 V, TA = +25°CVCC = +15 V, VEE = −15 V, TA = Tlow to Thigh
VIO
−−
− 0.50.5−
3.03.05.0
−−
−1.01.5−
5.05.07.0
mV
Average Temperature Coefficient of Input OffsetVoltageRS = 10 , VCM = 0 V, VO = 0 V, TA = Tlow to Thigh
VIO/T − 10 − − 10 − V/°C
Input Bias Current (VCM = 0 V, VO = 0 V)TA = +25°CTA = Tlow to Thigh
IIB−−
100−
500700
−−
100−
500700
nA
Input Offset Current (VCM = 0 V, VO = 0V)TA = +25°CTA = Tlow to Thigh
IIO−−
6.0−
50300
−−
6.0−
75300
nA
Input Common Mode Voltage RangeTA = +25°CTA = Tlow to Thigh
VICRVEE to (VCC −1.8)VEE to (VCC −2.2)
VEE to (VCC −1.8)VEE to (VCC −2.2)
V
Large Signal Voltage Gain (VO = ±10 V, RL = 2.0 k)TA = +25°CTA = Tlow to Thigh
AVOL5025
100−
−−
2520
100−
−−
V/mV
Output Voltage Swing (VID = ±1.0 V)VCC = +5.0 V, VEE = 0 V, RL = 2.0 k, TA = +25°CVCC = +15 V, VEE = −15 V, RL = 10 k, TA = +25°CVCC = +15 V, VEE = −15 V, RL = 2.0 k,
TA = Tlow to Thigh
VOH3.713.613.4
4.014−
−−−
3.713.613.4
4.014−
−−−
V
VCC = +5.0 V, VEE = 0 V, RL = 2.0 k, TA = +25°CVCC = +15 V, VEE = −15 V, RL = 10 k, TA = +25°CVCC = +15 V, VEE = −15 V, RL = 2.0 k,
TA = Tlow to Thigh
VOL −−−
0.1−14.7
−
0.3−14.3−13.5
−−−
0.1−14.7
−
0.3−14.3−13.5
V
Output Short Circuit Current (VID = 1.0 V, VO = 0 V,TA = 25°C)
SourceSink
ISC
1020
3030
−−
1020
3030
−−
mA
Common Mode RejectionRS ≤ 10 k, VCM = VICR, TA = 25°C
CMR 80 97 − 70 97 − dB
Power Supply Rejection (RS = 100 )VCC/VEE = +16.5 V/−16.5 V to +13.5 V/−13.5 V,
TA = 25°C
PSR 80 97 − 70 97 − dB
Power Supply Current (Per Amplifier, No Load)VCC = +5.0 V, VEE = 0 V, VO = +2.5 V, TA = +25°CVCC = +15 V, VEE = −15 V, VO = 0 V, TA = +25°CVCC = +15 V, VEE = −15 V, VO = 0 V,
TA = Tlow to Thigh
ID−−−
1.61.9−
2.02.52.8
−−−
1.61.9−
2.02.52.8
mA
3. Tlow = −40°C for MC33071, 2, 4, /A Thigh = +85°C for MC33071, 2, 4, /A= 0°C for MC34071, 2, 4, /A = +70°C for MC34071, 2, 4, /A= −40°C for MC34072, 4/V = +125°C for MC34072, 4/V
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AC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = −15 V, RL = connected to ground. TA = +25°C, unless otherwise noted.)
A Suffix Non−Suffix
Characteristics Symbol Min Typ Max Min Typ Max Unit
Slew Rate (Vin = −10 V to +10 V, RL = 2.0 k, CL = 500 pF)AV = +1.0AV = −1.0
SR8.0−
1013
−−
8.0−
1013
−−
V/s
Setting Time (10 V Step, AV = −1.0)To 0.1% (+1/2 LSB of 9−Bits)To 0.01% (+1/2 LSB of 12−Bits)
ts−−
1.12.2
−−
−−
1.12.2
−−
s
Gain Bandwidth Product (f = 100 kHz) GBW 3.5 4.5 − 3.5 4.5 − MHz
Power BandwidthAV = +1.0, RL = 2.0 k, VO = 20 Vpp, THD = 5.0%
BW − 160 − − 160 − kHz
Phase marginRL = 2.0 kRL = 2.0 k, CL = 300 pF
fm−−
6040
−−
−−
6040
−−
Deg
Gain MarginRL = 2.0 kRL = 2.0 k, CL = 300 pF
Am−−
124.0
−−
−−
124.0
−−
dB
Equivalent Input Noise VoltageRS = 100 , f = 1.0 kHz
en − 32 − − 32 − nV/ Hz√
Equivalent Input Noise Currentf = 1.0 kHz
in − 0.22 − − 0.22 − pA/ Hz√
Differential Input ResistanceVCM = 0 V
Rin − 150 − − 150 − M
Differential Input CapacitanceVCM = 0 V
Cin − 2.5 − − 2.5 − pF
Total Harmonic DistortionAV = +10, RL = 2.0 k, 2.0 Vpp ≤ VO ≤ 20 Vpp, f = 10 kHz
THD − 0.02 − − 0.02 − %
Channel Separation (f = 10 kHz) − − 120 − − 120 − dB
Open Loop Output Impedance (f = 1.0 MHz) |ZO| − 30 − − 30 − W
Figure 2. Power Supply Configurations Figure 3. Offset Null Circuit
Single Supply Split Supplies
1
2
3
4
VCC
VEE
VCC
VCC
VEE
VEE
1
2
3
4
3.0 V to 44 V VCC+|VEE|≤44 V
Offset nulling range is approximately ± 80 mV with a 10 kpotentiometer (MC33071, MC34071 only).
VCC
VEE
1
2
3
4
5
6
7
10 k
+
−
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RL Connectedto Ground TA = 25°C
RL = 10 k RL = 2.0 k
V O, O
UTP
UT
VO
LTA
GE
SW
ING
(Vpp
)
Figure 4. Maximum Power Dissipation versusTemperature for Package Types
Figure 5. Input Offset Voltage versusTemperature for Representative Units
Figure 6. Input Common Mode VoltageRange versus Temperature
Figure 7. Normalized Input Bias Currentversus Temperature
Figure 8. Normalized Input Bias Current versusInput Common Mode Voltage
Figure 9. Split Supply Output VoltageSwing versus Supply Voltage
TA, AMBIENT TEMPERATURE (°C)
DP
, M
AX
IMU
M P
OW
ER
DIS
SIP
ATIO
N (m
W)
−55 −40 −20 0 20 40 60 80 100 120 140 160
8 & 14 Pin Plastic PkgSO−14 Pkg
SO−8 Pkg
TA, AMBIENT TEMPERATURE (°C)
IOV
,
INP
UT
OFF
SE
T V
OLT
AG
E (m
V)
−55 −25 0 25 50 75 100 125
VCC = +15 VVEE = −15 VVCM = 0
TA, AMBIENT TEMPERATURE (°C)
ICR
V
, I
NP
UT
CO
MM
ON
MO
DE
VO
LTA
GE
RA
NG
E (V
)
−55 −25 0 25 50 75 100 125
VCC VCC/VEE = +1.5 V/ −1.5 V to +22 V/ −22 V
VEE
TA, AMBIENT TEMPERATURE (°C)
IBI, I
NP
UT
BIA
S C
UR
RE
NT
(NO
RM
ALI
ZED
)
−55 −25 0 25 50 75 100 125
VCC = +15 VVEE = −15 VVCM = 0
VIC, INPUT COMMON MODE VOLTAGE (V)
−12 −8.0 −4.0 0 4.0 8.0 12
VCC = +15 VVEE = −15 VTA = 25°C
VCC, |VEE|, SUPPLY VOLTAGE (V)
0 5.0 10 15 20 25
V
IBI, I
NP
UT
BIA
S C
UR
RE
NT
(NO
RM
ALI
ZED
)2400
2000
1600
1200
800
400
0
4.0
2.0
0
−2.0
−4.0
VCC
VCC −0.8
VCC −1.6
VCC −2.4
VEE +0.01
VEE
1.3
1.2
1.1
1.0
0.9
0.8
0.7
1.4
1.2
1.0
0.8
0.6
50
40
30
20
10
0
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VCC
VCC = +15 VRL to VCCTA = 25°C
Gnd
VCC
VCC = +15 VRL = GndTA = 25°C
Gnd
V O, O
UTP
UT
VO
LTA
GE
SW
ING
(Vpp
)
Figure 10. Single Supply Output Saturationversus Load Resistance to V CC
60
Figure 11. Split Supply Output Saturationversus Load Current
Figure 12. Single Supply Output Saturationversus Load Resistance to Ground
Figure 13. Output Short Circuit Currentversus Temperature
Figure 14. Output Impedance versus Frequency
Figure 15. Output Voltage Swingversus Frequency
0 5.0 10 15 20
IL, LOAD CURRENT (± mA)
VCC
VEE
Sink
VCC/VEE = +5.0 V/ −5.0 V to +22 V/ −22 VTA = 25°C
Source
RL, LOAD RESISTANCE TO GROUND ()
100 1.0 k 10 k 100 k
sat
V
, O
UTP
UT
SAT
UR
ATIO
N V
OLT
AG
E (V
)
RL, LOAD RESISTANCE TO VCC ()
100 1.0 k 10 k 100 k
TA, AMBIENT TEMPERATURE (°C)
SC
I
, O
UTP
UT
CU
RR
EN
T (m
A)
−55 −25 0 25 50 75 100 125
VCC = +15 VVEE = −15 VRL ≤ 0.1 Vin = 1.0 V
Sink
Source
f, FREQUENCY (Hz)
OZ
, O
UTP
UT
IMP
ED
AN
CE
()
Ω
1.0 k 10 k 100 1.0 M 10 M
AV = 1000 AV = 100 AV = 10 AV = 1.0
VCC = +15 VVEE = −15 VVCM = 0VO = 0IO = ±0.5 mATA = 25°C
f, FREQUENCY (Hz)
3.0 k 10 k 30 k 100 k 300 k 1.0 M 3.0 M
VCC = +15 VVEE = −15 VAV = +1.0RL = 2.0 kTHD ≤ 1.0%TA = 25°C
sat
V
, O
UTP
UT
SAT
UR
ATIO
N V
OLT
AG
E (V
)
sat
V
, O
UTP
UT
SAT
UR
ATIO
N V
OLT
AG
E (V
)VCC
VCC −1.0
VCC −2.0
VEE +2.0
VEE +1.0
VEE
VCC−2.0
VCC−4.0
VCC
0.2
0.1
0
0
−0.4
−0.8
2.0
1.0
50
40
30
20
10
0
50
40
30
20
10
0
28
24
20
16
12
8.0
4.0
0
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1. Phase RL = 2.0 k2. Phase RL = 2.0 k, CL = 300 pF3. Gain RL = 2.0 k4. Gain RL = 2.0 k, CL = 300 pFVCC = +15 VVEE = 15 VVO = 0 VTA = 25°C
PhaseMargin = 60°
GainMargin = 12 dB
3
4
1
2
Gain
VCC = +15 VVEE = −15 VVO = 0 VRL = 2.0 kTA = 25°C
Phase
PhaseMargin= 60°
Figure 16. Total Harmonic Distortionversus Frequency
Figure 17. Total Harmonic Distortionversus Output Voltage Swing
Figure 18. Open Loop Voltage Gainversus Temperature
Figure 19. Open Loop Voltage Gain andPhase versus Frequency
Figure 20. Open Loop Voltage Gain andPhase versus Frequency
Figure 21. Normalized Gain BandwidthProduct versus Temperature
f, FREQUENCY (Hz)
10 100 1.0 k 10 k 100 k
AV = 1000
AV = 100
AV = 10
AV = 1.0
VCC = +15 VVEE = −15 VVO = 2.0 VppRL = 2.0 kTA = 25°C
VO, OUTPUT VOLTAGE SWING (Vpp)
THD
, TO
TAL
HA
RM
ON
IC D
ISTO
RTI
ON
(%)
0 4.0 8.0 12 16 20
VCC = +15 VVEE = −15 VRL = 2.0 kTA = 25°C
AV = 1000
AV = 100
AV = 10
AV = 1.0
TA, AMBIENT TEMPERATURE (°C)
−55 −25 0 25 50 75 100 125
VCC = +15 VVEE = −15 VVO= −10 V to +10 VRL = 10 kf ≤ 10Hz
f, FREQUENCY (Hz)
1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M 100 M
, EX
CE
SS
PH
AS
E (D
EG
RE
ES
)φ
, EX
CE
SS
PH
AS
E (D
EG
RE
ES
)φ
f, FREQUENCY (MHz)
1.0 2.0 3.0 5.0 7.0 10 20 30
TA, AMBIENT TEMPERATURE (°C)
GB
W, G
AIN
BA
ND
WID
TH P
RO
DU
CT
(NO
RM
ALI
ED
)
−55 −25 0 25 50 75 100 125
VCC = +15 VVEE = −15 VRL = 2.0 k
VO
LA
, OP
EN
LO
OP
VO
LTA
GE
GA
IN (d
B)
0.4
0.3
0.2
0.1
0
4.0
3.0
2.0
1.0
0
116
112
108
104
100
96
100
80
60
40
20
0
20
10
0
−10
−20
−30
−40
1.15
1.1
1.05
1.0
0.95
0.9
0.85
0
45
90
135
180
100
120
140
160
180
THD
, TO
TAL
HA
RM
ON
IC D
ISTO
RTI
ON
(%)
VO
LA
, OP
EN
LO
OP
VO
LTA
GE
GA
IN (d
B)
VO
LA
, OP
EN
LO
OP
VO
LTA
GE
GA
IN (d
B)
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VCC = +15 VVEE = −15 VAV = +1.0RL = 2.0 k to VO = −10 V to +10 VTA = 25°C
Figure 22. Percent Overshoot versusLoad Capacitance
Figure 23. Phase Margin versusLoad Capacitance
Figure 24. Gain Margin versus Load Capacitance Figure 25. Phase Margin versus Temperature
Figure 26. Gain Margin versus Temperature Figure 27. Phase Margin and Gain Marginversus Differential Source Resistance
PE
RC
EN
T O
VE
RS
HO
OT
CL, LOAD CAPACITANCE (pF)
10 100 1.0 k 10 k
VCC = +15 VVEE = −15 VRL = 2.0 kVO = −10 V to +10 VTA = 25°C
CL, LOAD CAPACITANCE (pF)
, PH
AS
E M
AR
GIN
(DE
GR
EE
S)
φm
10 100 1.0 k 10 k
VCC = +15 VVEE = −15 VAV = +1.0RL = 2.0 k to ∞VO = −10 V to +10 VTA = 25°C
CL, LOAD CAPACITANCE (pF)
mA
, G
AIN
MA
RG
IN (d
B)
10 100 1.0 k 10 k
, PH
AS
E M
AR
GIN
(DE
GR
EE
S)
φm
TA, AMBIENT TEMPERATURE (°C)
−55 −25 0 25 50 75 100 125
VCC = +15 VVEE = −15 VAV = +1.0RL = 2.0 k to ∞VO = −10 V to +10 V
CL = 10 pF
CL = 100 pF
CL = 1,000 pF
CL = 10,000 pF
TA, AMBIENT TEMPERATURE (°C)
−55 −25 0 25 50 75 100 125
VCC = +15 V
VEE = −15 VAV = +1.0RL = 2.0 k to ∞VO = −10 V to +10 V
CL = 10 pF
CL = 1,000 pF
mA
, G
AIN
MA
RG
IN (d
B)
CL = 100 pF
CL = 10,000 pFPhase
mA
, G
AIN
MA
RG
IN (d
B)
RT, DIFFERENTIAL SOURCE RESISTANCE ()
1.0 100 1.0 k 10 k10 100 k
R1
R2
VO
+
−
VCC = +15 VVEE = −15 VRT = R1 + R2AV = +100VO = 0 VTA = 25°C
Gain, P
HA
SE
MA
RG
IN (D
EG
RE
ES
)φ
m
100
80
60
40
20
0
70
60
50
40
30
20
10
0
14
12
10
8.0
6.0
2.0
0
4.0
80
60
40
20
0
16
12
8.0
4.0
0
12
10
8.0
6.0
4.0
2.0
0
60
50
40
30
20
10
0
70
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Figure 28. Normalized Slew Rateversus Temperature
Figure 29. Output Settling Time
Figure 30. Small Signal Transient Response Figure 31. Large Signal Transient Response
Figure 32. Common Mode Rejectionversus Frequency
Figure 33. Power Supply Rejectionversus Frequency
TA, AMBIENT TEMPERATURE (°C)
SR
, SLE
W R
ATE
(NO
RM
ALI
ZED
)
−55 −25 0 25 50 75 100 125
VCC = +15 VVEE = −15 VAV = +1.0RL = 2.0 kCL = 500 pF
ts, SETTLING TIME (s)
OV
, O
UTP
UT
VO
LTA
GE
SW
ING
FR
OM
0 V
(V)
∆
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
VCC = +15 VVEE = −15 VAV = −1.0TA = 25°C
10 mV1.0 mV
1.0 mV
Compensated
Uncompensated
10 mV1.0 mV
1.0 mV
50 m
V/D
IV
2.0 s/DIV
VCC = +15 VVEE = −15 VAV = +1.0RL = 2.0 kCL = 300 pFTA = 25°C
5.0
V/D
IV
1.0 s/DIV
f, FREQUENCY (Hz)
CM
R, C
OM
MO
N M
OD
E R
EJE
CTI
ON
(dB
)
0.1 1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M
TA = 25°C
TA = 125°C
TA = −55°C
VCC = +15 VVEE = −15 VVCM = 0 VVCM = ±1.5 V
f, FREQUENCY (Hz)
PS
R, P
OW
ER
SU
PP
LY R
EJE
CTI
ON
(dB
)
0.1 1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M
VCC = +15 VVEE = −15 VTA = 25°C
(VCC = +1.5 V)
(VEE = +1.5 V)
+PSR
−PSR
VCC = +15 VVEE = −15 VAV = +1.0RL = 2.0 kCL = 300 pFTA = 25°C
1.15
1.1
1.05
1.0
0.95
0.9
0.85
10
5.0
0
−5.0
−10
0 0
100
80
60
40
20
0
100
80
60
40
20
0
VCM VOADM
CMR = 20 LogVCM
VOx ADM
+
−
VOADM+
−
VCC
VEE
VO/ADM
VCC
+PSR = 20 Log
VO/ADM
VEE
−PSR = 20 Log
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Figure 34. Supply Current versusSupply Voltage
Figure 35. Power Supply Rejectionversus Temperature
Figure 36. Channel Separation versus Frequency Figure 37. Input Noise versus Frequency
VCC, |VEE|, SUPPLY VOLTAGE (V)
CC
I ,
SU
PP
LY C
UR
RE
NT
(mA
)
0 5.0 10 15 20 25
TA = 25°C
TA = 125°C
TA = −55°C
TA, AMBIENT TEMPERATURE (°C)
PS
R, P
OW
ER
SU
PP
LY R
EJE
CTI
ON
(dB
)
−55 −25 0 25 50 75 100 125
VCC = +15 VVEE = −15 V
(VCC = +1.5 V)
(VEE = +1.5 V)
+PSR
−PSR
f, FREQUENCY (kHz)
CH
AN
NE
L S
EPA
RAT
ION
(dB
)
10 20 30 50 70 100 200 300
VCC = +15 VVEE = −15 VTA = 25°C
f, FREQUENCY (kHz)
ne,
INP
UT
NO
ICE
VO
LTA
GE
(
i, I
NP
UT
NO
ISE
CU
RR
EN
T (p
A
)
10 100 1.0 k 10 k 100 k
nVH
z)
√ Hz
√n
Voltage
Current
9.0
8.0
7.0
6.0
5.0
4.0
105
95
85
75
65
120
100
80
60
40
20
0
70
60
50
40
30
20
10
0
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0
VOADM+
−
VCC
VEE
VO/ADM
VCC+PSR = 20 Log
VO/ADM
VEE−PSR = 20 Log
VCC = +15 VVEE = −15 VVCM = 0TA = 25°C
APPLICATIONS INFORMATIONCIRCUIT DESCRIPTION/PERFORMANCE FEATURES
Although the bandwidth, slew rate, and settling time of theMC34071 amplifier series are similar to op amp productsutilizing JFET input devices, these amplifiers offer otheradditional distinct advantages as a result of the PNPtransistor differential input stage and an all NPN transistoroutput stage.
Since the input common mode voltage range of this inputstage includes the VEE potential, single supply operation isfeasible to as low as 3.0 V with the common mode inputvoltage at ground potential.
The input stage also allows differential input voltages upto ±44 V, provided the maximum input voltage range is notexceeded. Specifically, the input voltages must rangebetween VEE and VCC supply voltages as shown by themaximum rating table. In practice, although notrecommended, the input voltages can exceed the VCCvoltage by approximately 3.0 V and decrease below the VEEvoltage by 0.3 V without causing product damage, althoughoutput phase reversal may occur. It is also possible to source
up to approximately 5.0 mA of current from VEE througheither inputs clamping diode without damage or latching,although phase reversal may again occur.
If one or both inputs exceed the upper common modevoltage limit, the amplifier output is readily predictable andmay be in a low or high state depending on the existing inputbias conditions.
Since the input capacitance associated with the smallgeometry input device is substantially lower (2.5 pF) thanthe typical JFET input gate capacitance (5.0 pF), betterfrequency response for a given input source resistance canbe achieved using the MC34071 series of amplifiers. Thisperformance feature becomes evident, for example, in fastsettling D−to−A current to voltage conversion applicationswhere the feedback resistance can form an input pole withthe input capacitance of the op amp. This input pole createsa 2nd order system with the single pole op amp and istherefore detrimental to its settling time. In this context,lower input capacitance is desirable especially for higher
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values of feedback resistances (lower current DACs). Thisinput pole can be compensated for by creating a feedbackzero with a capacitance across the feedback resistance, ifnecessary, to reduce overshoot. For 2.0 k of feedbackresistance, the MC34071 series can settle to within 1/2 LSBof 8 bits in 1.0 s, and within 1/2 LSB of 12−bits in 2.2 sfor a 10 V step. In a inverting unity gain fast settlingconfiguration, the symmetrical slew rate is ±13 V/s. In theclassic noninverting unity gain configuration, the outputpositive slew rate is +10 V/s, and the correspondingnegative slew rate will exceed the positive slew rate as afunction of the fall time of the input waveform.
Since the bipolar input device matching characteristicsare superior to that of JFETs, a low untrimmed maximumoffset voltage of 3.0 mV prime and 5.0 mV downgrade canbe economically offered with high frequency performancecharacteristics. This combination is ideal for low costprecision, high speed quad op amp applications.
The all NPN output stage, shown in its basic form on theequivalent circuit schematic, offers unique advantages overthe more conventional NPN/PNP transistor Class AB outputstage. A 10 k load resistance can swing within 1.0 V of thepositive rail (VCC), and within 0.3 V of the negative rail(VEE), providing a 28.7 Vpp swing from ±15 V supplies.This large output swing becomes most noticeable at lowersupply voltages.
The positive swing is limited by the saturation voltage ofthe current source transistor Q7, and VBE of the NPN pull uptransistor Q17, and the voltage drop associated with the shortcircuit resistance, R7. The negative swing is limited by thesaturation voltage of the pull−down transistor Q16, thevoltage drop ILR6, and the voltage drop associated withresistance R7, where IL is the sink load current. For smallvalued sink currents, the above voltage drops are negligible,allowing the negative swing voltage to approach withinmillivolts of VEE. For large valued sink currents (>5.0 mA),diode D3 clamps the voltage across R6, thus limiting thenegative swing to the saturation voltage of Q16, plus theforward diode drop of D3 (≈VEE +1.0 V). Thus for a givensupply voltage, unprecedented peak−to−peak output voltageswing is possible as indicated by the output swingspecifications.
If the load resistance is referenced to VCC instead ofground for single supply applications, the maximumpossible output swing can be achieved for a given supplyvoltage. For light load currents, the load resistance will pullthe output to VCC during the positive swing and the outputwill pull the load resistance near ground during the negativeswing. The load resistance value should be much less thanthat of the feedback resistance to maximize pull upcapability.
Because the PNP output emitter−follower transistor hasbeen eliminated, the MC34071 series offers a 20 mA
minimum current sink capability, typically to an outputvoltage of (VEE +1.8 V). In single supply applications theoutput can directly source or sink base current from acommon emitter NPN transistor for fast high currentswitching applications.
In addition, the all NPN transistor output stage isinherently fast, contributing to the bipolar amplifier’s highgain bandwidth product and fast settling capability. Theassociated high frequency low output impedance (30 typ@ 1.0 MHz) allows capacitive drive capability from 0 pF to10,000 pF without oscillation in the unity closed loop gainconfiguration. The 60° phase margin and 12 dB gain marginas well as the general gain and phase characteristics arevirtually independent of the source/sink output swingconditions. This allows easier system phase compensation,since output swing will not be a phase consideration. Thehigh frequency characteristics of the MC34071 series alsoallow excellent high frequency active filter capability,especially for low voltage single supply applications.
Although the single supply specifications is defined at5.0 V, these amplifiers are functional to 3.0 V @ 25°Calthough slight changes in parametrics such as bandwidth,slew rate, and DC gain may occur.
If power to this integrated circuit is applied in reversepolarity or if the IC is installed backwards in a socket, largeunlimited current surges will occur through the device thatmay result in device destruction.
Special static precautions are not necessary for thesebipolar amplifiers since there are no MOS transistors on thedie.
As with most high frequency amplifiers, proper leaddress, component placement, and PC board layout should beexercised for optimum frequency performance. Forexample, long unshielded input or output leads may result inunwanted input−output coupling. In order to preserve therelatively low input capacitance associated with theseamplifiers, resistors connected to the inputs should beimmediately adjacent to the input pin to minimize additionalstray input capacitance. This not only minimizes the inputpole for optimum frequency response, but also minimizesextraneous “pick up” at this node. Supply decoupling withadequate capacitance immediately adjacent to the supply pinis also important, particularly over temperature, since manytypes of decoupling capacitors exhibit great impedancechanges over temperature.
The output of any one amplifier is current limited and thusprotected from a direct short to ground. However, undersuch conditions, it is important not to allow the device toexceed the maximum junction temperature rating. Typicallyfor ±15 V supplies, any one output can be shortedcontinuously to ground without exceeding the maximumtemperature rating.
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Figure 38. AC Coupled Noninverting Amplifier Figure 39. AC Coupled Inverting Amplifier
(Typical Single Supply Applications V CC = 5.0 V)
Figure 40. DC Coupled Inverting AmplifierMaximum Output Swing
Figure 41. Unity Gain Buffer TTL Driver
Figure 42. Active High−Q Notch Filter Figure 43. Active Bandpass Filter
−
+
VCC
5.1 M
20 k Cin
Vin
1.0 M
MC34071
VO
0 3.7 Vpp
RL
10 k
AV = 101
100 k
1.0 k
BW (−3.0 dB) = 45 kHz
CO VO
36.6 mVpp−
+
3.7 Vpp0VCC
VO
100 k
Cin 10 k
100 k
CO
RL
10 k
68 k
Vin 370 mVpp
AV = 10 BW (−3.0 dB) = 450 kHz
+
−
4.75 Vpp
VO
VO
VCC
RL
100 k
91 k
5.1 k
1.0 M
AV = 10Vin
2.63 V
5.1 k
BW (−3.0 dB) = 450 kHz
−
+Vin
2.5 V
0 0 to 10,000 pF
Cable TTL Gate
−
+Vin
VO
16 kC
0.01
32 k 2.0 R
2.0 C0.02
fo = 1.0 kHz
fo =
Vin ≥ 0.2 Vdc
1
4RC
2.0 C0.02
16 k
RR
−
+
VinVO
VCC
R32.2 k
C0.047
R25.6 k
0.4 VCC
R1
fo = 30 kHzHo = 10Ho = 1.0
1.1 k
Given fo = Center FrequencyAO = Gain at Center FrequencyChoose Value fo, Q, Ao, C
R3 = R1 = R2 =Q R3 R1 R3
2Ho 4Q2R1−R3foC
For less than 10% error from operational amplifierQofo
GBW< 0.1
where fo and GBW are expressed in Hz.
C0.047
MC34071
MC34071
MC34071
MC34071
MC34071
MC54/74XX
Then:
GBW = 4.5 MHz Typ.
MC34071,2,4,A MC33071,2,4,A
http://onsemi.com13
Figure 44. Low Voltage Fast D/A Converter Figure 45. High Speed Low Voltage Comparator
Figure 46. LED Driver Figure 47. Transistor Driver
Figure 48. AC/DC Ground Current Monitor Figure 49. Photovoltaic Cell Amplifier
5.0 k
10 k
BitSwitches
CF
RF
VO
VCC
(R−2R) Ladder Network
Settling Time1.0 s (8−Bits, 1/2 LSB)
−
+
5.0 k5.0 k
10 k 10 k
−
+
VO
VO
Vin
1.0 V
2.0 kRL
2.0 V
4.0 V
0.1
t
25 V/s
0.2 sDelay
Delay1.0 s
Vin
t
13 V/s
−
+
VCC
Vref
ON"
Vin < Vref
ON"
Vin > Vref
Vin
−
+
VCC
VCC
RL
RL
(A) PNP (B) NPN
−
+
−
+
VO
ILoad
R1
R2
RSGround CurrentSense Resistor
VO = ILoad RS
BW ( −3.0 dB) = GBW
For VO > 0.1V
R1
R2
R1+R2
R2
−
+
VO
MC34071
ICell
VCell = 0 VVO = ICell RFVO > 0.1 V
RF
1+
MC34071
MC34071
MC34071 MC34071
MC34071
MC34071
MC34071,2,4,A MC33071,2,4,A
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Figure 50. Low Input Voltage Comparatorwith Hysteresis
Figure 51. High Compliance Voltage toSink Current Converter
Figure 52. High Input ImpedanceDifferential Amplifier
Figure 53. Bridge Current Amplifier
Figure 54. Low Voltage Peak Detector Figure 55. High Frequency PulseWidth Modulation
Vref
R2
VO
VOH
VOL
VinL VinH
Vref
Hysteresis
VinVin
R1
MC34071
VinL = (VOL−Vref)+VrefR1
R1+R2
VinH = (VOH−Vref)+Vref
VH = (VOH −VOL)
+
−
R1
R1+R
R1
R1+R2
Vin
Iout
R
−
+
Iout =Vin±VIO
R
1/2MC34072 −
+
+
R1 R2
R3
R4
VO
+V1
+V2
R2 R4
R3R1(Critical to CMRR)
VO = 1 V2−V1
For (V2 ≥ V1), V > 0
=
−
+R4
R3
R4
R3
−
+
+Vref
RF
VO
R R
RR = R
R < < R
RF > > R (VO ≥ 0.1 V)
RF
VO = Vref
R RF
2R2
−
+Vin
Vin
RL VP 10,000 pF
VO = Vin (pk)
+
VP
t
−+
+
VP
t
t
Iout
VP
+
−
0
+ISC
Base ChargeRemoval
±IB
V+
47 k100 k
C
R
Pulse WidthControl Group
OSC Comparator High CurrentOutput
fOSC V
0.85
RC
−
100 k
IB
MC34071
MC34071
MC34071
1/2MC34072
1/2MC34072
1/2MC34072
MC34071,2,4,A MC33071,2,4,A
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Figure 56. Second Order Low−Pass Active Filter Figure 57. Second Order High−Pass Active Filter
GENERAL ADDITIONAL APPLICATIONS INFORMATION V S = ±15.0 V
Figure 58. Fast Settling Inverter Figure 59. Basic Inverting Amplifier
Figure 60. Basic Noninverting Amplifier Figure 61. Unity Gain Buffer (A V = +1.0)
−
+
R1 R3560 510
C2
C10.44
0.02
R25.6 k
MC34071
fo = 1.0 kHzHo = 10
Choose: fo, Ho, C2
Then: C1 = 2C2 (Ho+1)
R2 = R3 = R1 =R2
HoHo+14foC2
R2
+
−
C20.05 C1
1.0
R146.1 k
R21.1 k
fo = 100 HzHo = 20
Choose: fo, Ho, C1 Then: R1 =
R2 =
C2 =
Ho+0.5
foC1
2foC1 (1/Ho+2)
C
Ho
C11.0
+
−
CF*
VO = 10 VStepRF
2.0 k
I
High SpeedDAC
*Optional Compensation
Uncompensated
Compensated
ts = 1.0 s
to 1/2 LSB (8−Bits)
ts = 2.2 s
to 1/2 LSB (12−Bits)
SR = 13 V/s
VO
+
−R1
R2
VO
Vin
RL
BW (−3.0 dB) = GBW=
SR = 13 V/s
VO
Vin
R2
R1 R1 +R2
R1
BW (−3.0 dB) = GBWR1 +R2
R1
+
−Vin
VO
R2
RL
R1
=VO
Vin
R2
R11 +
+
−
Vin
VO
BWp = 200 kHzVO = 20 VppSR = 10 V/s
MC34071
MC34071MC34071
MC34071
MC34071
2
2
2
MC34071,2,4,A MC33071,2,4,A
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Figure 62. High Impedance Differential Amplifier
Figure 63. Dual Voltage Doubler
−
R
RE
Example:Let: R = RE = 12 kThen: AV = 3.0BW = 1.5 MHz
AV = 1 +2R
RE
−
−
+
+
+
VO
R
R
R R
R
MC34074
−
+
+
100 k 10
+10
−10
220 pF
−VO
+VO
RL +VO −VO
18.93 −18.78
10 k 18 −18
5.0 k 15.4 −15.4
∞
RL
100 k
100 k
RL
+
+
−
+
+
+
10
10
10
−
MC34074
MC34074
MC34074
MC34074
MC34074
MC34071,2,4,A MC33071,2,4,A
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ORDERING INFORMATIONOp AmpFunction Device
OperatingTemperature Range Package Shipping †
Single MC34071P, MC34071APMC34071D, MC34071ADMC34071DR2, MC34071ADR2
TA = 0° to +70°CDIP−8SO−8
SO−8 / Tape & Reel
50 Units / Rail98 Units / Rail
2500 Units / Tape & Reel
MC33071P, MC33071APMC33071D, MC33071ADMC33071DR2, MC33071ADR2
TA = −40° to +85°CDIP−8SO−8
SO−8 / Tape & Reel
50 Units / Rail98 Units / Rail
2500 Units / Tape & Reel
Dual MC34072P, MC34072APMC34072D, MC34072ADMC34072DR2, MC34072ADR2
TA = 0° to +70°CDIP−8SO−8
SO−8 / Tape & Reel
50 Units / Rail98 Units / Rail
2500 Units / Tape & Reel
MC33072P, MC33072APMC33072D, MC33072ADMC33072DR2, MC33072DR2G,MC33072ADR2
TA = −40° to +85°C
DIP−8SO−8
SO−8 / Tape & Reel
50 Units / Rail98 Units / Rail
2500 Units / Tape & Reel
MC34072VDMC34072VDR2MC34072VP
TA = −40° to +125°CSO−8
SO−8 / Tape & ReelDIP−8
98 Units / Rail2500 Units / Tape & Reel
50 Units / Rail
Quad MC34074P, MC34074APMC34074D, MC34074ADMC34074DR2, MC34074ADR2
TA = 0° to +70°CDIP−14SO−14
SO−14 / Tape & Reel
25 Units / Rail55 Units / Rail
2500 Units / Tape & Reel
MC33074P, MC33074APMC33074D, MC33074ADMC33074DR2, MC33074ADR2MC33074DTB, MC33074ADTBMC33074DTBR2, MC33074ADTBR2
TA = −40° to +85°C
DIP−14SO−14
SO−14 / Tape & ReelTSSOP−14
TSSOP−14 / Tape & Reel
25 Units / Rail55 Units / Rail
2500 Units / Tape & Reel96 Units / Rail
2500 Units / Tape & Reel
MC34074VDMC34074VDR2MC34074VP
TA = −40° to +125°CSO−14
SO−14 / Tape & ReelDIP−14
55 Units / Rail2500 Units / Tape & Reel
25 Units / Rail
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel PackagingSpecifications Brochure, BRD8011/D.
MC34071,2,4,A MC33071,2,4,A
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MARKING DIAGRAMS
AWLMC3x071P
1
8
YYWWAWL
MC3x071AP
1
8
YYWW
ALYW3x071
1
8
ALYWA3x071
1
8
x = 3 or 4A = Assembly LocationWL, L = Wafer LotYY, Y = YearWW, W = Work Week
AWLMC3x072P
1
8
YYWW
PDIP−8P SUFFIXCASE 626
AWLMC3x072AP
1
8
YYWW
ALYW3x072
1
8
ALYWA3x072
1
8
SO−8D SUFFIXCASE 751
ALYWV3x072
1
8
1
14
MC3x074PAWLYYWW
PDIP−14P SUFFIXCASE 646
1
14
MC3x074APAWLYYWW
1
14
MC3x074DAWLYWW
1
14
MC3x074ADAWLYWW
MC33074
ALYW
1
14
TSSOP−14DTB SUFFIXCASE 948G
MC33074AALYW
1
14
SO−14D SUFFIX
CASE 751A
1
14
MC34074VDAWLYWW
AWLMC34072VP
1
8
YYWW
1
14
MC34074VPAWLYYWW
MC34071,2,4,A MC33071,2,4,A
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PACKAGE DIMENSIONS
PDIP−8P SUFFIX
CASE 626−05ISSUE L
NOTES:1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
1 4
58
F
NOTE 2 −A−
−B−
−T−SEATINGPLANE
H
J
G
D K
N
C
L
M
MAM0.13 (0.005) B MT
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 9.40 10.16 0.370 0.400B 6.10 6.60 0.240 0.260C 3.94 4.45 0.155 0.175D 0.38 0.51 0.015 0.020F 1.02 1.78 0.040 0.070G 2.54 BSC 0.100 BSCH 0.76 1.27 0.030 0.050J 0.20 0.30 0.008 0.012K 2.92 3.43 0.115 0.135L 7.62 BSC 0.300 BSCM −−− 10 −−− 10 N 0.76 1.01 0.030 0.040
MC34071,2,4,A MC33071,2,4,A
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PACKAGE DIMENSIONS
SO−8D SUFFIX
CASE 751−07ISSUE AA
SEATINGPLANE
1
4
58
N
J
X 45
K
NOTES:1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.127 (0.005) TOTAL INEXCESS OF THE D DIMENSION AT MAXIMUMMATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEWSTANDARD IS 751−07.
A
B S
DH
C
0.10 (0.004)
DIM
A
MIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B 3.80 4.00 0.150 0.157C 1.35 1.75 0.053 0.069D 0.33 0.51 0.013 0.020G 1.27 BSC 0.050 BSCH 0.10 0.25 0.004 0.010J 0.19 0.25 0.007 0.010K 0.40 1.27 0.016 0.050M 0 8 0 8 N 0.25 0.50 0.010 0.020S 5.80 6.20 0.228 0.244
−X−
−Y−
G
MYM0.25 (0.010)
−Z−
YM0.25 (0.010) Z S X S
M
SO−8
1.520.060
7.00.275
0.60.024
1.2700.050
4.00.155
mminches
SCALE 6:1
*For additional information on our Pb−Free strategy and solderingdetails, please download the ON Semiconductor Soldering andMounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
MC34071,2,4,A MC33071,2,4,A
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PACKAGE DIMENSIONS
PDIP−14P SUFFIX
CASE 646−06ISSUE M
1 7
14 8
B
A DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.715 0.770 18.16 18.80B 0.240 0.260 6.10 6.60C 0.145 0.185 3.69 4.69D 0.015 0.021 0.38 0.53F 0.040 0.070 1.02 1.78G 0.100 BSC 2.54 BSCH 0.052 0.095 1.32 2.41J 0.008 0.015 0.20 0.38K 0.115 0.135 2.92 3.43L
M −−− 10 −−− 10 N 0.015 0.039 0.38 1.01
NOTES:1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.2. CONTROLLING DIMENSION: INCH.3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.5. ROUNDED CORNERS OPTIONAL.
F
H G DK
C
SEATINGPLANE
N
−T−
14 PL
M0.13 (0.005)
L
MJ
0.290 0.310 7.37 7.87
SO−14D SUFFIX
CASE 751A−03ISSUE F
NOTES:1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.127 (0.005) TOTALIN EXCESS OF THE D DIMENSION ATMAXIMUM MATERIAL CONDITION.
−A−
−B−
G
P 7 PL
14 8
71M0.25 (0.010) B M
SBM0.25 (0.010) A ST
−T−
FR X 45
SEATINGPLANE
D 14 PL K
C
JM
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 8.55 8.75 0.337 0.344B 3.80 4.00 0.150 0.157C 1.35 1.75 0.054 0.068D 0.35 0.49 0.014 0.019F 0.40 1.25 0.016 0.049G 1.27 BSC 0.050 BSCJ 0.19 0.25 0.008 0.009K 0.10 0.25 0.004 0.009M 0 7 0 7 P 5.80 6.20 0.228 0.244R 0.25 0.50 0.010 0.019
MC34071,2,4,A MC33071,2,4,A
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PACKAGE DIMENSIONS
SU0.15 (0.006) T
2X L/2
SUM0.10 (0.004) V ST
L−U−
SEATING
PLANE
0.10 (0.004)
−T−
ÇÇÇÇ
SECTION N−N
DETAIL E
J J1
K
K1
ÉÉÉÉ
DETAIL E
F
M
−W−
0.25 (0.010)814
71
PIN 1IDENT.
HG
A
D
C
B
SU0.15 (0.006) T
−V−
14X REFK
N
N
TSSOP−14DTB SUFFIX
CASE 948G−01ISSUE O
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 4.90 5.10 0.193 0.200B 4.30 4.50 0.169 0.177C −−− 1.20 −−− 0.047D 0.05 0.15 0.002 0.006F 0.50 0.75 0.020 0.030G 0.65 BSC 0.026 BSCH 0.50 0.60 0.020 0.024J 0.09 0.20 0.004 0.008J1 0.09 0.16 0.004 0.006K 0.19 0.30 0.007 0.012K1 0.19 0.25 0.007 0.010L 6.40 BSC 0.252 BSCM 0 8 0 8
NOTES:1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASHOR GATE BURRS SHALL NOT EXCEED 0.15(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEADFLASH OR PROTRUSION. INTERLEAD FLASH ORPROTRUSION SHALL NOT EXCEED0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBARPROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.08 (0.003) TOTAL INEXCESS OF THE K DIMENSION AT MAXIMUMMATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FORREFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINEDAT DATUM PLANE −W−.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further noticeto any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liabilityarising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. Alloperating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rightsnor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicationsintended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. ShouldBuyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or deathassociated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an EqualOpportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATIONN. American Technical Support : 800−282−9855 Toll FreeUSA/Canada
Japan : ON Semiconductor, Japan Customer Focus Center2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051Phone : 81−3−5773−3850
MC34071/D
LITERATURE FULFILLMENT :Literature Distribution Center for ON SemiconductorP.O. Box 5163, Denver, Colorado 80217 USAPhone : 303−675−2175 or 800−344−3860 Toll Free USA/CanadaFax: 303−675−2176 or 800−344−3867 Toll Free USA/CanadaEmail : [email protected]
ON Semiconductor Website : http://onsemi.com
Order Literature : http://www.onsemi.com/litorder
For additional information, please contact yourlocal Sales Representative.
Semiconductor Components Industries, LLC, 2003
July, 2003 - Rev. 91 Publication Order Number:
MC33201/D
MC33201, MC33202,MC33204, NCV33202,NCV33204
Low Voltage, Rail−to−RailOperational Amplifiers
The MC33201/2/4 family of operational amplifiers providerail-to-rail operation on both the input and output. The inputs can bedriven as high as 200 mV beyond the supply rails without phasereversal on the outputs, and the output can swing within 50 mV of eachrail. This rail-to-rail operation enables the user to make full use of thesupply voltage range available. It is designed to work at very lowsupply voltages (± 0.9 V) yet can operate with a supply of up to +12 Vand ground. Output current boosting techniques provide a high outputcurrent capability while keeping the drain current of the amplifier to aminimum. Also, the combination of low noise and distortion with ahigh slew rate and drive capability make this an ideal amplifier foraudio applications.
• Low Voltage, Single Supply Operation(+1.8 V and Ground to +12 V and Ground)
• Input Voltage Range Includes both Supply Rails
• Output Voltage Swings within 50 mV of both Rails
• No Phase Reversal on the Output for Over-driven Input Signals
• High Output Current (ISC = 80 mA, Typ)
• Low Supply Current (ID = 0.9 mA, Typ)
• 600 Output Drive Capability
• Extended Operating Temperature Ranges(-40° to +105°C and -55° to +125°C)
• Typical Gain Bandwidth Product = 2.2 MHz
See detailed ordering and shipping information in the packagedimensions section on page 11 of this data sheet.
ORDERING INFORMATION
PDIP-8P, VP SUFFIX
CASE 6268
1
SO-8D, VD SUFFIX
CASE 7518
1
PDIP-14P, VP SUFFIX
CASE 64614
1
SO-14D, VD SUFFIXCASE 751A14
1
TSSOP-14DTB SUFFIXCASE 948G
14
1
Micro-8DM SUFFIXCASE 846A
81
See general marking information in the device markingsection on page 12 of this data sheet.
DEVICE MARKING INFORMATION
http://onsemi.com
MC33201, MC33202, MC33204, NCV33202, NCV33204
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PIN CONNECTIONS
6
7
8
5
3
2
1
4
NC
Inputs
VEE
NC
VCC
NC
Output
(Top View)
MC33201All Case Styles
MC33202All Case Styles
Output 1
Inputs 1
VEE
VCC
Output 2
Inputs 2
1
2
6
7
8
5
3
2
1
4
(Top View)
MC33204All Case Styles
(Top View)
Output 1
Inputs 1
VCC
Output 4
Inputs 41
12
13
14
11
3
2
1
4
105
96
Output 2 87
Inputs 2 2
4
3
VEE
Inputs 3
Output 3
Vin−Vout
Figure 1. Circuit Schematic(Each Amplifier)
VEE
VCC
VCC
VCC
VCC
Vin+
VEEThis device contains 70 active transistors (each amplifier).
MC33201, MC33202, MC33204, NCV33202, NCV33204
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MAXIMUM RATINGS
Rating Symbol Value Unit
Supply Voltage (VCC to VEE) VS +13 V
Input Differential Voltage Range VIDR Note 1 V
Common Mode Input Voltage Range (Note 2) VCM VCC + 0.5 V toVEE - 0.5 V
V
Output Short Circuit Duration ts Note 3 sec
Maximum Junction Temperature TJ +150 °C
Storage Temperature Tstg - 65 to +150 °C
Maximum Power Dissipation PD Note 3 mW
DC ELECTRICAL CHARACTERISTICS (TA = 25°C)
Characteristic VCC = 2.0 V VCC = 3.3 V VCC = 5.0 V Unit
Input Offset VoltageVIO (max)MC33201MC33202, NCV33202MC33204
± 8.0±10±12
± 8.0±10±12
± 6.0± 8.0±10
mV
Output Voltage SwingVOH (RL = 10 k)VOL (RL = 10 k)
1.90.10
3.150.15
4.850.15
VminVmax
Power Supply Currentper Amplifier (ID) 1.125 1.125 1.125
mA
Specifications at VCC = 3.3 V are guaranteed by the 2.0 V and 5.0 V tests. VEE = GND.
DC ELECTRICAL CHARACTERISTICS (VCC = + 5.0 V, VEE = Ground, TA = 25°C, unless otherwise noted.)
Characteristic Figure Symbol Min Typ Max Unit
Input Offset Voltage (VCM 0 V to 0.5 V, VCM 1.0 V to 5.0 V)MC33201: TA = + 25°CMC33201: TA = - 40° to +105°CMC33201V: TA = - 55° to +125°CMC33202: TA = + 25°CMC33202: TA = - 40° to +105°CMC33202V: TA = - 55° to +125°CNCV33202V: TA = - 55° to +125°C (Note 4)MC33204: TA = + 25°CMC33204: TA = - 40° to +105°CMC33204V: TA = - 55° to +125°C
3 VIO----------
---------
6.09.0138.0111414101317
mV
Input Offset Voltage Temperature Coefficient (RS = 50 )TA = - 40° to +105°CTA = - 55° to +125°C
4 VIO/T--
2.02.0
--
V/°C
Input Bias Current (VCM = 0 V to 0.5 V, VCM = 1.0 V to 5.0 V)TA = + 25°CTA = - 40° to +105°CTA = - 55° to +125°C
5, 6 IIB---
80100
-
200250500
nA
Input Offset Current (VCM = 0 V to 0.5 V, VCM = 1.0 V to 5.0 V)TA = + 25°CTA = - 40° to +105°CTA = - 55° to +125°C
- IIO---
5.010-
50100200
nA
Common Mode Input Voltage Range - VICR VEE - VCC V
1. The differential input voltage of each amplifier is limited by two internal parallel back- to-back diodes. For additional differential input voltagerange, use current limiting resistors in series with the input pins.
2. The input common mode voltage range is limited by internal diodes connected from the inputs to both supply rails. Therefore, the voltageon either input must not exceed either supply rail by more than 500 mV.
3. Power dissipation must be considered to ensure maximum junction temperature (TJ) is not exceeded. (See Figure 2)4. NCV33202 and NCV33204 are qualified for automotive use.
MC33201, MC33202, MC33204, NCV33202, NCV33204
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DC ELECTRICAL CHARACTERISTICS (cont.) (VCC = + 5.0 V, VEE = Ground, TA = 25°C, unless otherwise noted.)
Characteristic Figure Symbol Min Typ Max Unit
Large Signal Voltage Gain (VCC = + 5.0 V, VEE = - 5.0 V)RL = 10 kRL = 600
7 AVOL5025
300250
--
kV/V
Output Voltage Swing (VID = ± 0.2 V)RL = 10 kRL = 10 kRL = 600 RL = 600
8, 9, 10VOHVOLVOHVOL
4.85-
4.75-
4.950.054.850.15
-0.15
-0.25
V
Common Mode Rejection (Vin = 0 V to 5.0 V) 11 CMR 60 90 - dB
Power Supply Rejection RatioVCC/VEE = 5.0 V/GND to 3.0 V/GND
12 PSRR500 25 -
V/V
Output Short Circuit Current (Source and Sink) 13, 14 ISC 50 80 - mA
Power Supply Current per Amplifier (VO = 0 V)TA = - 40° to +105°CTA = - 55° to +125°C
15 ID--
0.90.9
1.1251.125
mA
AC ELECTRICAL CHARACTERISTICS (VCC = + 5.0 V, VEE = Ground, TA = 25°C, unless otherwise noted.)
Characteristic Figure Symbol Min Typ Max Unit
Slew Rate(VS = ± 2.5 V, VO = - 2.0 V to + 2.0 V, RL = 2.0 k, AV = +1.0)
16, 26 SR0.5 1.0 -
V/s
Gain Bandwidth Product (f = 100 kHz) 17 GBW - 2.2 - MHz
Gain Margin (RL = 600 , CL = 0 pF) 20, 21, 22 AM - 12 - dB
Phase Margin (RL = 600 , CL = 0 pF) 20, 21, 22 M - 65 - Deg
Channel Separation (f = 1.0 Hz to 20 kHz, AV = 100) 23 CS - 90 - dB
Power Bandwidth (VO = 4.0 Vpp, RL = 600 , THD ≤ 1 %) BWP - 28 - kHz
Total Harmonic Distortion (RL = 600 , VO = 1.0 Vpp, AV = 1.0)f = 1.0 kHzf = 10 kHz
24 THD--
0.0020.008
--
%
Open Loop Output Impedance(VO = 0 V, f = 2.0 MHz, AV = 10)
ZO- 100 -
Differential Input Resistance (VCM = 0 V) Rin - 200 - k
Differential Input Capacitance (VCM = 0 V) Cin - 8.0 - pF
Equivalent Input Noise Voltage (RS = 100 )f = 10 Hzf = 1.0 kHz
25 en--
2520
-- Hz
nV/
Equivalent Input Noise Currentf = 10 Hzf = 1.0 kHz
25 in--
0.80.2
--
pA/Hz
MC33201, MC33202, MC33204, NCV33202, NCV33204
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300
260
220
180
TA, AMBIENT TEMPERATURE (°C)
100
140
PE
RC
EN
TAG
E O
F A
MP
LIFI
ER
S (%
)
TCVIO, INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT (V/°C)
50
30
0
40
10
20
AV
OL
, OP
EN
LO
OP
VO
LTA
GE
GA
IN (k
V/V
)
Figure 2. Maximum Power Dissipation versus Temperature
Figure 3. Input Offset Voltage Distribution
PE
RC
EN
TAG
E O
F A
MP
LIFI
ER
S (%
)
40
35
VIO, INPUT OFFSET VOLTAGE (mV)
30
25
15
0
20
Figure 4. Input Offset Voltage Temperature Coefficient Distribution
2500
2000
1000
500
0
TA, AMBIENT TEMPERATURE (°C)
Figure 5. Input Bias Current versus Temperature
Figure 6. Input Bias Current versus Common Mode Voltage
Figure 7. Open Loop Voltage Gain versusTemperature
150
50
0
−50
VCM, INPUT COMMON MODE VOLTAGE (V)
1500
PD
(max
), MA
XIM
UM
PO
WE
R D
ISS
IPAT
ION
(mW
200
160
120
80
TA, AMBIENT TEMPERATURE (°C)
0
I IB, I
NP
UT
BIA
S C
UR
RE
NT
(nA
)
40
5.0
10
VCC = +5.0 VVEE = Gnd
VCM > 1.0 V
VCM = 0 V to 0.5 V
I IB, I
NP
UT
BIA
S C
UR
RE
NT
(nA
) 100
−100
−150
−200
−250−55 −40 −25 0 25 70 85 125
−50 0 20 40 50−10 10 30−30−40 −20
−10 0 4.0 8.0 10−55 −40 −25 0 25 50 85 125
2.0 4.0
−2.0 2.0 6.0−6.0−8.0 −4.0
−55 −40 −25 0 25 70 85 125
0 6.0 8.0 10 12 105
8 and 14 Pin DIP Pkg
SO−14 Pkg
SO−8 Pkg
360 amplifiers tested from3 (MC33204) wafer lotsVCC = +5.0 VVEE = GndTA = 25°CDIP Package
360 amplifiers tested from3 (MC33204) wafer lotsVCC = +5.0 VVEE = GndTA = 25°CDIP Package
VCC = +5.0 VVEE = GndRL = 600 VO = 0.5 V to 4.5 V
VCC = 12 VVEE = GndTA = 25°C
TSSOP−14 Pkg
MC33201, MC33202, MC33204, NCV33202, NCV33204
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VO
,OU
TPU
T V
OLT
AG
E (V
)pp
VO
,OU
TPU
T V
OLT
AG
E (V
)pp
40
20
100
80
60
Vout , OUTPUT VOLTAGE (V)
0
f, FREQUENCY (Hz)
12
0
9.0
3.0
6.0
VCC = +6.0 VVEE = −6.0 VRL = 600 AV = +1.0TA = 25°C
Figure 8. Output Voltage Swingversus Supply Voltage
Figure 9. Output Saturation Voltageversus Load Current
V
IL, LOAD CURRENT (mA)
VEE
Figure 10. Output Voltageversus Frequency
12
10
6.0
2.0
0
VCC, VEE SUPPLY VOLTAGE (V)
Figure 11. Common Mode Rejectionversus Frequency
Figure 12. Power Supply Rejectionversus Frequency
Figure 13. Output Short Circuit Currentversus Output Voltage
120
80
60
f, FREQUENCY (Hz)
8.0
100
80
60
40
f, FREQUENCY (Hz)
0
CM
R, C
OM
MO
N M
OD
E R
EJE
CTI
ON
(dB
)
20
VCC = +6.0 VVEE = −6.0 VTA = −55° to +125°C
PS
R, P
OW
ER
SU
PP
LY R
EJE
CTI
ON
(dB
)
100
40
20
0
VCC = +6.0 VVEE = −6.0 VTA = −55° to +125°C
VCC = +6.0 VVEE = −6.0 VTA = 25°C
4.0
SAT
, OU
TPU
T S
ATU
RAT
ION
VO
LTA
GE
(V)
TA = 25°C
TA = −55°C
PSR+
PSR−
I SC
, OU
TPU
T S
HO
RT
CIR
CU
IT C
UR
RE
NT
(mA
)
Source
Sink
VCC = +5.0 VVEE = −5.0 V
TA = 125°C
TA = 125°C
TA = −55°C
TA = 25°C
10 100 1.0 k 10 k 100 k 1.0 M 0 1.0 2.0 3.0 4.0 5.0 6.0
1.0 k 100 k 1.0 M10 k
0 15 20±1.0 ±2.0 105.0
10 100 1.0 k 10 k 100 k 1.0 M
±3.0 ±4.0 ±5.0 ±6.0
RL = 600 TA = 25°C
VCC
VCC − 0.2 V
VCC − 0.4 V
VEE + 0.4 V
VEE + 0.2 V
MC33201, MC33202, MC33204, NCV33202, NCV33204
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, EX
CE
SS
PH
AS
E (D
EG
RE
ES
)
VCC, VEE , SUPPLY VOLTAGE (V)
I SC
, OU
TPU
T S
HO
RT
CIR
CU
IT C
UR
RE
NT
(mA
)S
R, S
LEW
RAT
E (V
/ s
)µ
TA, AMBIENT TEMPERATURE (°C)
VCC = +2.5 VVEE = −2.5 VVO = ±2.0 V
Figure 14. Output Short Circuit Currentversus Temperature
Figure 15. Supply Current per Amplifierversus Supply Voltage with No Load
I
Figure 16. Slew Rateversus Temperature
TA, AMBIENT TEMPERATURE (°C)
Figure 17. Gain Bandwidth Productversus Temperature
Figure 18. Voltage Gain and Phaseversus Frequency
Figure 19. Voltage Gain and Phaseversus Frequency
f, FREQUENCY (Hz)
GB
W, G
AIN
BA
ND
WID
TH P
RO
DU
CT
(MH
z)
A
, O
PE
N L
OO
P V
OLT
AG
E G
AIN
(dB
)
VCC = +5.0 VVEE = Gnd
CC
, SU
PP
LY C
UR
RE
NT
PE
R A
MP
LIFI
ER
(mA
)
TA = 125°C
TA = −55°C
Source
SinkTA = 25°C
+Slew Rate
−Slew Rate
TA, AMBIENT TEMPERATURE (°C)
VCC = +2.5 VVEE = −2.5 Vf = 100 kHz
VO
L , EX
CE
SS
PH
AS
E (D
EG
RE
ES
)
f, FREQUENCY (Hz)
70
50
30
10
−10
−30
2.0
0
1.5
0.5
1.0
2.0
1.6
0
150
125
75
25
0
70
50
30
100
4.0
3.0
2.0
0
1.0
10
−10
−30
50
1.2
0.8
0.4
±1.0 ±2.0 ±3.0 ±4.0 ±5.0 ±6.0
10 k 100 k 1.0 M 10 M
−55 −40 −25 25 70 1250 85 105 ±0
−55 −40 −25 25 70 1250 85 105 −55 −40 −25 25 70 1250 85 105
10 k 100 k 1.0 M 10 M240
40
80
120
160
200
40
80
120
160
200
240
A
, O
PE
N L
OO
P V
OLT
AG
E G
AIN
(dB
)V
OL
1A − Phase, CL = 0 pF1B − Gain, CL = 0 pF2A − Phase, CL = 300 pF2B − Gain, CL = 300 pF
1A − Phase, VS = ±6.0 V1B − Gain, VS = ±6.0 V2A − Phase, VS = ±1.0 V2B − Gain, VS = ±1.0 V
VS = ±6.0 VTA = 25°CRL = 600
CL = 0 pFTA = 25°CRL = 600
1A2A
2B
1B
1A
2A
2B
1B
MC33201, MC33202, MC33204, NCV33202, NCV33204
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M, P
HA
SE
MA
RG
IN (D
EG
RE
ES
)
i ,
INP
UT
RE
FER
RE
D N
OIS
E C
UR
RE
NT
(pA
/ H
z)n
50
40
30
e ,
EQ
UIV
ALE
NT
INP
UT
NO
ISE
VO
LTA
GE
(nV
/ H
z)
20
10
0
n
RT, DIFFERENTIAL SOURCE RESISTANCE ()
CL, CAPACITIVE LOAD (pF)
80
0
70
40
Figure 20. Gain and Phase Marginversus Temperature
Figure 21. Gain and Phase Marginversus Differential Source Resistance
75
60
0
Figure 22. Gain and Phase Marginversus Capacitive Load
70
60
40
10
0
TA, AMBIENT TEMPERATURE (°C)
Figure 23. Channel Separationversus Frequency
Figure 24. Total Harmonic Distortionversus Frequency
Figure 25. Equivalent Input Noise Voltageand Current versus Frequency
10
1.0
0.1
f, FREQUENCY (Hz)
50
150
90
60
0
CS
, CH
AN
NE
L S
EPA
RAT
ION
(dB
)
30
THD
, TO
TAL
HA
RM
ON
IC D
ISTO
RTI
ON
(%)
0.01
0.001
20
45
30
15
Phase Margin
Gain Margin
f, FREQUENCY (Hz)
f, FREQUENCY (Hz)
M, P
HA
SE
MA
RG
IN (D
EG
RE
ES
)
30
AM
, GA
IN M
AR
GIN
(dB
)
AM
, GA
IN M
AR
GIN
(dB
)
60
10
20
30
50
AM
, GA
IN M
AR
GIN
(dB
)
AV = 10
120
AV = 100
AV = 10
AV = 1.0
AV = 100
M, P
HA
SE
MA
RG
IN (D
EG
RE
ES
)
100 1.0 k 10 k 100 k
10 100 1.0 k 100 k
−55 −40 −25 25 70 1250 85 105 10
10 100 1.0 k 100 1.0 k 10 k
10 100 10 k 100 k10 k 1.0 k
5.0
4.0
3.0
2.0
1.0
0
70
60
40
10
0
50
20
30
75
60
0
45
30
15
16
0
14
8.0
12
2.0
4.0
6.0
10
VCC = +6.0 VVEE = −6.0 VRL = 600 CL = 100 pF
VCC = +6.0 VVEE = −6.0 VTA = 25°C
Phase Margin
Phase Margin
Gain Margin
VCC = +6.0 VVEE = −6.0 VRL = 600 AV = 100TA = 25°C
Gain Margin
VCC = +6.0 VVEE = −6.0 VVO = 8.0 VppTA = 25°C
VCC = +5.0 VTA = 25°CVO = 2.0 Vpp
VEE = −5.0 VRL = 600
VCC = +6.0 VVEE = −6.0 VTA = 25°C
Noise Voltage
Noise Current
AV = 1000
MC33201, MC33202, MC33204, NCV33202, NCV33204
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DETAILED OPERATING DESCRIPTION
General Information
The MC33201/2/4 family of operational amplifiers areunique in their ability to swing rail-to-rail on both the inputand the output with a completely bipolar design. This offerslow noise, high output current capability and a widecommon mode input voltage range even with low supplyvoltages. Operation is guaranteed over an extendedtemperature range and at supply voltages of 2.0 V, 3.3 V and5.0 V and ground.
Since the common mode input voltage range extends fromVCC to VEE, it can be operated with either single or splitvoltage supplies. The MC33201/2/4 are guaranteed not tolatch or phase reverse over the entire common mode range,however, the inputs should not be allowed to exceedmaximum ratings.
Circuit Information
Rail-to-rail performance is achieved at the input of theamplifiers by using parallel NPN-PNP differential inputstages. When the inputs are within 800 mV of the negativerail, the PNP stage is on. When the inputs are more than 800mV greater than VEE, the NPN stage is on. This switching ofinput pairs will cause a reversal of input bias currents (seeFigure 6). Also, slight differences in offset voltage may benoted between the NPN and PNP pairs. Cross-couplingtechniques have been used to keep this change to a minimum.
In addition to its rail-to-rail performance, the output stageis current boosted to provide 80 mA of output current,enabling the op amp to drive 600 loads. Because of thishigh output current capability, care should be taken not toexceed the 150°C maximum junction temperature.
O, O
UTP
UT
VO
LTA
GE
(50
mV
/DIV
)V
t, TIME (10 s/DIV)
Figure 26. Noninverting Amplifier Slew Rate Figure 27. Small Signal Transient Response
t, TIME (5.0 s/DIV)
Figure 28. Large Signal Transient Response
VCC = +6.0 VVEE = −6.0 VRL = 600 CL = 100 pFTA = 25°C
O, O
UTP
UT
VO
LTA
GE
(2.0
mV
/DIV
)
VCC = +6.0 VVEE = −6.0 VRL = 600 CL = 100 pFAV = 1.0TA = 25°C
V
VCC = +6.0 VVEE = −6.0 VRL = 600 CL = 100 pFTA = 25°C
t, TIME (10 s/DIV)
O, O
UTP
UT
VO
LTA
GE
(2.0
V/D
IV)
V
MC33201, MC33202, MC33204, NCV33202, NCV33204
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MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the totaldesign. The footprint for the semiconductor packages must bethe correct size to ensure proper solder connection interface
between the board and the package. With the correct padgeometry, the packages will self-align when subjected to asolder reflow process.
mm
inches
0.0411.04
0.2085.28
0.0150.38
0.02560.65
0.1263.20
Micro-8
MC33201, MC33202, MC33204, NCV33202, NCV33204
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ORDERING INFORMATION
OperationalAmplifier Function Device
OperatingTemperature Range Package Shipping
MC33201D SO-8 98 Units / Rail
SingleMC33201DR2 TA= -40° to +105°C SO-8 2500 Units / Tape & Reel
SingleMC33201P
A
Plastic DIP 50 Units / Rail
MC33201VD TA = -55° to 125°C SO-8 98 Units / Rail
MC33202D SO-8 98 Units / Rail
MC33202DR2TA= 40 ° to +105°C
SO-8 2500 Units / Tape & Reel
MC33202DMR2TA= -40 ° to +105°C
Micro-8 4000 Units / Tape & Reel
DualMC33202P Plastic DIP 50 Units / Rail
DualMC33202VD SO-8 98 Units / Rail
MC33202VDR2TA 55° to 125°C
SO-8 2500 Units / Tape & Reel
NCV33202VDR2*TA = -55° to 125°C
SO-8 2500 Units / Tape & Reel
MC33202VP Plastic DIP 50 Units / Rail
MC33204D SO-14 55 Units / Rail
MC33204DR2 SO-14 2500 Units / Tape & Reel
MC33204DTB TA= -40 ° to +105°C TSSOP-14 96 Units / Rail
MC33204DTBR2
A
TSSOP-14 2500 Units / Tape & Reel
QuadMC33204P Plastic DIP 25 Units / Rail
QuadMC33204VD SO-14 55 Units / Rail
MC33204VDR2 SO-14 2500 Units / Tape & Reel
NCV33204DR2* TA = -55° to 125°C SO-14 2500 Units / Tape & Reel
NCV33204DTBR2*
A
TSSOP-14 2500 Units / Tape & Reel
MC33204VP Plastic DIP 25 Units / Rail
*NCV33202 and NCV33204 are qualified for automotive use.
MC33201, MC33202, MC33204, NCV33202, NCV33204
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SO-8D SUFFIXCASE 751
PDIP-8P SUFFIXCASE 626
SO-8VD SUFFIXCASE 751
x = 1 or 2A = Assembly LocationWL, L = Wafer LotYY, Y = YearWW, W = Work Week
PDIP-8VP SUFFIXCASE 626
SO-14D SUFFIX
CASE 751A
TSSOP-14DTB SUFFIXCASE 948G
PDIP-14P SUFFIXCASE 646
SO-14VD SUFFIXCASE 751A
PDIP-14VP SUFFIXCASE 646
MARKING DIAGRAMS
Micro-8DM SUFFIXCASE 846A
3202AYW
1
8
ALYW3320x
1
8
ALYW320xV
1
8
1
8
MC3320xP AWL YYWW
1
8
MC33202VP AWL YYWW
1
14
MC33204DAWLYWW
1
14
MC33204VDAWLYWW
1
14
MC33204PAWLYYWW
1
14
MC33204VPAWLYYWW
1
14
MC33204
ALYW
*
*This marking diagram applies to NCV3320x
*
*
1
14
MC33204VALYW
MC33201, MC33202, MC33204, NCV33202, NCV33204
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PACKAGE DIMENSIONS
PDIP-8P, VP SUFFIXCASE 626-05
ISSUE L
NOTES:1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
1 4
58
F
NOTE 2 -A-
-B-
-T-SEATINGPLANE
H
J
G
D K
N
C
L
M
MAM0.13 (0.005) B MT
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 9.40 10.16 0.370 0.400B 6.10 6.60 0.240 0.260C 3.94 4.45 0.155 0.175D 0.38 0.51 0.015 0.020F 1.02 1.78 0.040 0.070G 2.54 BSC 0.100 BSCH 0.76 1.27 0.030 0.050J 0.20 0.30 0.008 0.012K 2.92 3.43 0.115 0.135L 7.62 BSC 0.300 BSCM −−− 10 −−− 10 N 0.76 1.01 0.030 0.040
SO-8D, VD SUFFIXCASE 751-07
ISSUE AA
SEATINGPLANE
1
4
58
N
J
X 45
K
NOTES:1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.127 (0.005) TOTAL INEXCESS OF THE D DIMENSION AT MAXIMUMMATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEWSTANDAARD IS 751−07
A
B S
DH
C
0.10 (0.004)
DIM
A
MIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B 3.80 4.00 0.150 0.157C 1.35 1.75 0.053 0.069D 0.33 0.51 0.013 0.020G 1.27 BSC 0.050 BSCH 0.10 0.25 0.004 0.010J 0.19 0.25 0.007 0.010K 0.40 1.27 0.016 0.050M 0 8 0 8 N 0.25 0.50 0.010 0.020S 5.80 6.20 0.228 0.244
-X-
-Y-
G
MYM0.25 (0.010)
-Z-
YM0.25 (0.010) Z S X S
M
MC33201, MC33202, MC33204, NCV33202, NCV33204
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PACKAGE DIMENSIONS
PDIP-14P, VP SUFFIXCASE 646-06
ISSUE M
1 7
14 8
B
A DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.715 0.770 18.16 18.80B 0.240 0.260 6.10 6.60C 0.145 0.185 3.69 4.69D 0.015 0.021 0.38 0.53F 0.040 0.070 1.02 1.78G 0.100 BSC 2.54 BSCH 0.052 0.095 1.32 2.41J 0.008 0.015 0.20 0.38K 0.115 0.135 2.92 3.43L
M −−− 10 −−− 10 N 0.015 0.039 0.38 1.01
NOTES:1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.2. CONTROLLING DIMENSION: INCH.3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.5. ROUNDED CORNERS OPTIONAL.
F
H G DK
C
SEATINGPLANE
N
-T-
14 PL
M0.13 (0.005)
L
MJ
0.290 0.310 7.37 7.87
SO-14D, VD SUFFIXCASE 751A-03
ISSUE F
NOTES:1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.127 (0.005) TOTALIN EXCESS OF THE D DIMENSION ATMAXIMUM MATERIAL CONDITION.
-A-
-B-
G
P 7 PL
14 8
71M0.25 (0.010) B M
SBM0.25 (0.010) A ST
-T-
FR X 45
SEATINGPLANE
D 14 PL K
C
JM
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 8.55 8.75 0.337 0.344B 3.80 4.00 0.150 0.157C 1.35 1.75 0.054 0.068D 0.35 0.49 0.014 0.019F 0.40 1.25 0.016 0.049G 1.27 BSC 0.050 BSCJ 0.19 0.25 0.008 0.009K 0.10 0.25 0.004 0.009M 0 7 0 7 P 5.80 6.20 0.228 0.244R 0.25 0.50 0.010 0.019
MC33201, MC33202, MC33204, NCV33202, NCV33204
http://onsemi.com15
PACKAGE DIMENSIONS
TSSOP-14DTB SUFFIX
CASE 948G-01ISSUE O
SU0.15 (0.006) T
2X L/2
SUM0.10 (0.004) V ST
L-U-
SEATING
PLANE
0.10 (0.004)
-T-
ÇÇÇÇ
SECTION N-N
DETAIL E
J J1
K
K1
ÉÉÉÉ
DETAIL E
F
M
-W-
0.25 (0.010)814
71
PIN 1IDENT.
HG
A
D
C
B
SU0.15 (0.006) T
-V-
14X REFK
N
N
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 4.90 5.10 0.193 0.200B 4.30 4.50 0.169 0.177C −−− 1.20 −−− 0.047D 0.05 0.15 0.002 0.006F 0.50 0.75 0.020 0.030G 0.65 BSC 0.026 BSCH 0.50 0.60 0.020 0.024J 0.09 0.20 0.004 0.008J1 0.09 0.16 0.004 0.006K 0.19 0.30 0.007 0.012K1 0.19 0.25 0.007 0.010L 6.40 BSC 0.252 BSCM 0 8 0 8
NOTES:1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASHOR GATE BURRS SHALL NOT EXCEED 0.15(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEADFLASH OR PROTRUSION. INTERLEAD FLASH ORPROTRUSION SHALL NOT EXCEED0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBARPROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.08 (0.003) TOTAL INEXCESS OF THE K DIMENSION AT MAXIMUMMATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FORREFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINEDAT DATUM PLANE −W−.
MC33201, MC33202, MC33204, NCV33202, NCV33204
http://onsemi.com16
PACKAGE DIMENSIONS
SBM0.08 (0.003) A STDIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 2.90 3.10 0.114 0.122B 2.90 3.10 0.114 0.122C −−− 1.10 −−− 0.043D 0.25 0.40 0.010 0.016G 0.65 BSC 0.026 BSCH 0.05 0.15 0.002 0.006J 0.13 0.23 0.005 0.009K 4.75 5.05 0.187 0.199L 0.40 0.70 0.016 0.028
NOTES:1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH,PROTRUSIONS OR GATE BURRS SHALL NOTEXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEADFLASH OR PROTRUSION. INTERLEAD FLASH ORPROTRUSION SHALL NOT EXCEED 0.25 (0.010)PER SIDE.
5. 846A−01 OBSOLETE, NEW STANDARD 846A−02.
-B-
-A-
D
K
GPIN 1 ID
8 PL
0.038 (0.0015)
-T-SEATINGPLANE
C
H J L
STYLE 1:PIN 1. SOURCE
2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN
STYLE 2:PIN 1. SOURCE 1
2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. DRAIN 2 7. DRAIN 1 8. DRAIN 1
STYLE 3:PIN 1. N−SOURCE
2. N−GATE 3. P−SOURCE 4. P−GATE 5. P−DRAIN 6. P−DRAIN 7. N−DRAIN 8. N−DRAIN
Micro-8DM SUFFIX
CASE 846A-02ISSUE F
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to makechanges without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for anyparticular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and allliability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/orspecifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must bevalidated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicationsintended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or deathmay occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLCand its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney feesarising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges thatSCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATIONJAPAN : ON Semiconductor, Japan Customer Focus Center4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan 141-0031Phone : 81-3-5740-2700Email : [email protected]
ON Semiconductor Website : http://onsemi.com
For additional information, please contact your localSales Representative.
MC33201/D
Literature Fulfillment :Literature Distribution Center for ON SemiconductorP.O. Box 5163, Denver, Colorado 80217 USAPhone : 303-675-2175 or 800-344-3860 Toll Free USA/CanadaFax: 303-675-2176 or 800-344-3867 Toll Free USA/CanadaEmail : [email protected]
N. American Technical Support : 800-282-9855 Toll Free USA/Canada
1N4001-1N
4007
1N4001-1N4007, Rev. C1 2003 Fairchild Semiconductor Corporation
1N4001 - 1N4007
General Purpose Rectifiers
Absolute Maximum Ratings* TA = 25°C unless otherwise noted
*These ratings are limiting values above which the serviceability of any semiconductor device may be impaired.
Electrical Characteristics TA = 25°C unless otherwise noted
Features• Low forward voltage drop.
• High surge current capability.
Symbol
Parameter
Device
Units 4001 4002 4003 4004 4005 4006 4007
VF Forward Voltage @ 1.0 A 1.1 V Irr Maximum Full Load Reverse Current, Full
Cycle TA = 75°C 30 µA
IR Reverse Current @ rated VR TA = 25°C TA = 100°C
5.0 500
µA µA
CT Total Capacitance VR = 4.0 V, f = 1.0 MHz
15 pF
DO-41COLOR BAND DENOTES CATHODE
Symbol
Parameter
Value
Units 4001 4002 4003 4004 4005 4006 4007
VRRM Peak Repetitive Reverse Voltage 50 100 200 400 600 800 1000 V IF(AV) Average Rectified Forward Current,
.375 " lead length @ TA = 75°C 1.0 A
IFSM Non-repetitive Peak Forward Surge Current
8.3 ms Single Half-Sine-Wave 30 A
Tstg Storage Temperature Range -55 to +175 °C TJ Operating Junction Temperature -55 to +175 °C
Symbol
Parameter
Value
Units PD Power Dissipation 3.0 W RθJA Thermal Resistance, Junction to Ambient 50 °C/W
Thermal Characteristics
1N4001-1N
4007
1N4001-1N4007, Rev. C1 2003 Fairchild Semiconductor Corporation
General Purpose Rectifiers (continued)
Typical Characteristics
Forward Characteristics
0.6 0.8 1 1.2 1.40.010.020.04
0.10.20.4
124
1020
FORWARD VOLTAGE (V)
FORW
ARD
CUR
REN
T (A
)
T = 25 C Pulse Width = 300µµµµS2% Duty Cycle
ºJ
Non-Repetitive Surge Current
1 2 4 6 8 10 20 40 60 1000
6
12
18
24
30
NUMBER OF CYCLES AT 60Hz
FORW
AR
D SU
RGE
CUR
RENT
(A) p
k
Forward Current Derating Curve
0 20 40 60 80 100 120 140 160 1800
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
AMBIENT TEMPERATURE ( C)
FOR
WA
RD C
URR
ENT
(A)
º
SINGLE PHASE HALF WAVE
60HZRESISTIVE OR
INDUCTIVE LOAD.375" 9.0 mm LEAD
LENGTHS
Reverse Characteristics
0 20 40 60 80 100 120 1400.01
0.1
1
10
100
1000
RATED PEAK REVERSE VOLTAGE (%)
REVE
RSE
CUR
RENT
( A
)
T = 25 CºJ
T = 150 CºJ
T = 100 CºJ
µ µµµ
!"#$%"&'(%& %)'"%&'!%*$%('((!'&$$%"'+'%,'*- %& ''.$'-'($$%+!% !"'*%("&%%$%%( /0!11 2 2345 123 4511 3 45 1 1 1 2 1 3 21 6 2
7 12111 2 1 21 11 23 2
$ 2
((
%
1 1 1122
1 2311 21 2 1
1 2 1
11 2 1 2
"
$
$
($
!"# !
$ %
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+
,-./,0
"""! "# !1+# !%
!
0#23#24#25((+
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7! 0!$8!#! 0!,80!,!0+$! '!
CB E
TO-92
C
B
E
BC
C
SOT-223
E
NPN General Purpose AmplifierThis device is designed as a general purpose amplifier and switch.The useful dynamic range extends to 100 mA as a switch and to100 MHz as an amplifier.
Absolute Maximum Ratings* TA = 25°C unless otherwise noted
*These ratings are limiting values above which the serviceability of any semiconductor device may be impaired.
NOTES:1) These ratings are based on a maximum junction temperature of 150 degrees C.2) These are steady state limits. The factory should be consulted on applications involving pulsed or low duty cycle operations.
Symbol Parameter Value UnitsVCEO Collector-Emitter Voltage 40 VVCBO Collector-Base Voltage 60 VVEBO Emitter-Base Voltage 6.0 VIC Collector Current - Continuous 200 mATJ, Tstg Operating and Storage Junction Temperature Range -55 to +150 °C
2001 Fairchild Semiconductor Corporation
Thermal Characteristics TA = 25°C unless otherwise noted
Symbol Characteristic Max Units2N3904 *MMBT3904 **PZT3904
PD Total Device DissipationDerate above 25°C
6255.0
3502.8
1,0008.0
mWmW/°C
RθJC Thermal Resistance, Junction to Case 83.3 °C/WRθJA Thermal Resistance, Junction to Ambient 200 357 125 °C/W
*Device mounted on FR-4 PCB 1.6" X 1.6" X 0.06."
**Device mounted on FR-4 PCB 36 mm X 18 mm X 1.5 mm; mounting pad for the collector lead min. 6 cm2.
2N3904 MMBT3904
SOT-23Mark: 1A
PZT3904
2N3904 / M
MB
T3904 / PZT3904
2N3904/MMBT3904/PZT3904, Rev A
Electrical Characteristics TA = 25°C unless otherwise noted
Symbol Parameter Test Conditions Min Max Units
V(BR)CEO Collector-Emitter BreakdownVoltage
IC = 1.0 mA, IB = 0 40 V
V(BR)CBO Collector-Base Breakdown Voltage IC = 10 µA, IE = 0 60 VV(BR)EBO Emitter-Base Breakdown Voltage IE = 10 µA, IC = 0 6.0 VIBL Base Cutoff Current VCE = 30 V, VEB = 3V 50 nAICEX Collector Cutoff Current VCE = 30 V, VEB = 3V 50 nA
OFF CHARACTERISTICS
ON CHARACTERISTICS*
SMALL SIGNAL CHARACTERISTICS
SWITCHING CHARACTERISTICS
*Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0%
NPN (Is=6.734f Xti=3 Eg=1.11 Vaf=74.03 Bf=416.4 Ne=1.259 Ise=6.734 Ikf=66.78m Xtb=1.5 Br=.7371 Nc=2Isc=0 Ikr=0 Rc=1 Cjc=3.638p Mjc=.3085 Vjc=.75 Fc=.5 Cje=4.493p Mje=.2593 Vje=.75 Tr=239.5n Tf=301.2pItf=.4 Vtf=4 Xtf=2 Rb=10)
Spice Model
fT Current Gain - Bandwidth Product IC = 10 mA, VCE = 20 V,f = 100 MHz
300 MHz
Cobo Output Capacitance VCB = 5.0 V, IE = 0,f = 1.0 MHz
4.0 pF
Cibo Input Capacitance VEB = 0.5 V, IC = 0,f = 1.0 MHz
8.0 pF
NF Noise Figure IC = 100 µA, VCE = 5.0 V,RS =1.0kΩ,f=10 Hz to 15.7kHz
5.0 dB
td Delay Time VCC = 3.0 V, VBE = 0.5 V, 35 nstr Rise Time IC = 10 mA, IB1 = 1.0 mA 35 ns
ts Storage Time VCC = 3.0 V, IC = 10mA 200 nstf Fall Time IB1 = IB2 = 1.0 mA 50 ns
hFE DC Current Gain IC = 0.1 mA, VCE = 1.0 VIC = 1.0 mA, VCE = 1.0 VIC = 10 mA, VCE = 1.0 VIC = 50 mA, VCE = 1.0 VIC = 100 mA, VCE = 1.0 V
40701006030
300
VCE(sat) Collector-Emitter Saturation Voltage IC = 10 mA, IB = 1.0 mAIC = 50 mA, IB = 5.0 mA
0.20.3
VV
VBE(sat) Base-Emitter Saturation Voltage IC = 10 mA, IB = 1.0 mAIC = 50 mA, IB = 5.0 mA
0.65 0.850.95
VV
2N3904 / M
MB
T3904 / PZT3904NPN General Purpose Amplifier
(continued)
2N3904 / M
MB
T3904 / P
ZT
3904
Typical Characteristics
Base-Emitter ON Voltage vsCollector Current
0.1 1 10 1000.2
0.4
0.6
0.8
1
I - COLLECTOR CURRENT (mA)V
-
BA
SE
-EM
ITT
ER
ON
VO
LTA
GE
(V
)B
E(O
N)
C
V = 5VCE
25 °C
125 °C
- 40 °C
NPN General Purpose Amplifier(continued)
Base-Emitter SaturationVoltage vs Collector Current
0.1 1 10 100
0.4
0.6
0.8
1
I - COLLECTOR CURRENT (mA)
V
-
BA
SE
-EM
ITT
ER
VO
LTA
GE
(V)
BE
SA
T
C
β = 10
25 °C
125 °C
- 40 °C
Collector-Emitter SaturationVoltage vs Collector Current
0.1 1 10 100
0.05
0.1
0.15
I - COLLECTOR CURRENT (mA)V
-
CO
LL
EC
TOR
-EM
ITT
ER
VO
LTA
GE
(V
)C
ES
AT
25 °C
C
β = 10
125 °C
- 40 °C
Collector-Cutoff Currentvs Ambient Temperature
25 50 75 100 125 150
0.1
1
10
100
500
T - AMBIENT TEMPERATURE ( C)
I
- C
OL
LE
CTO
R C
UR
RE
NT
(n
A)
A
V = 30VCB
CB
O
°
Capacitance vs Reverse Bias Voltage
0.1 1 10 1001
2
3
4
5
10
REVERSE BIAS VOLTAGE (V)
CA
PAC
ITA
NC
E (
pF)
C obo
C ibo
f = 1.0 MHz
Typical Pulsed Current Gainvs Collector Current
0.1 1 10 1000
100
200
300
400
500
I - COLLECTOR CURRENT (mA)h
- T
YP
ICA
L P
UL
SE
D C
UR
RE
NT
GA
INF
E
- 40 °C
25 °C
C
V = 5VCE
125 °C
Power Dissipation vsAmbient Temperature
0 25 50 75 100 125 1500
0.25
0.5
0.75
1
TEMPERATURE ( C)
P
- PO
WE
R D
ISS
IPAT
ION
(W)
D
o
SOT-223
SOT-23
TO-92
Typical Characteristics (continued)
Noise Figure vs Frequency
0.1 1 10 1000
2
4
6
8
10
12
f - FREQUENCY (kHz)
NF
- N
OIS
E F
IGU
RE
(d
B)
V = 5.0VCE
I = 100 µA, R = 500 ΩC S
I = 1.0 mA R = 200ΩC
S
I = 50 µA
R = 1.0 kΩCS
I = 0.5 mA R = 200ΩC
S
kΩ
Noise Figure vs Source Resistance
0.1 1 10 1000
2
4
6
8
10
12
R - SOURCE RESISTANCE ( )
NF
- N
OIS
E F
IGU
RE
(d
B)
I = 100 µAC
I = 1.0 mAC
S
I = 50 µAC
I = 5.0 mAC
θ - DE
GR
EE
S
0
406080100120
140160
20
180
Current Gain and Phase Anglevs Frequency
1 10 100 10000
5
10
15
20
25
30
35
40
45
50
f - FREQUENCY (MHz)
h
-
CU
RR
EN
T G
AIN
(d
B)
θ
V = 40VCE
I = 10 mAC
h fe
fe
Turn-On Time vs Collector Current
1 10 1005
10
100
500
I - COLLECTOR CURRENT (mA)
TIM
E (
nS
)
I = I = B1
C
B2I c
1040V
15V
2.0V
t @ V = 0VCBd
t @ V = 3.0VCCr
Rise Time vs Collector Current
1 10 1005
10
100
500
I - COLLECTOR CURRENT (mA)
t
- R
ISE
TIM
E (
ns)
I = I = B1
C
B2I c
10
T = 125°C
T = 25°CJ
V = 40VCC
r
J
2N3904 / M
MB
T3904 / P
ZT
3904NPN General Purpose Amplifier
(continued)
2N3904 / M
MB
T3904 / P
ZT
3904NPN General Purpose Amplifier
(continued)
Typical Characteristics (continued)
Storage Time vs Collector Current
1 10 1005
10
100
500
I - COLLECTOR CURRENT (mA)
t
- S
TOR
AG
E T
IME
(n
s)
I = I = B1
C
B2I c
10
S
T = 125°C
T = 25°CJ
J
Fall Time vs Collector Current
1 10 1005
10
100
500
I - COLLECTOR CURRENT (mA)
t
- FA
LL
TIM
E (
ns)
I = I = B1
C
B2I c
10V = 40VCC
f
T = 125°C
T = 25°CJ
J
Current Gain
0.1 1 1010
100
500
I - COLLECTOR CURRENT (mA)
h
- C
UR
RE
NT
GA
IN
V = 10 VCE
C
fe
f = 1.0 kHzT = 25 CA
o
Output Admittance
0.1 1 101
10
100
I - COLLECTOR CURRENT (mA)
h
- O
UT
PU
T A
DM
ITTA
NC
E (
mho
s) V = 10 VCE
C
oe
f = 1.0 kHzT = 25 CA
oµ
Input Impedance
0.1 1 100.1
1
10
100
I - COLLECTOR CURRENT (mA)
h
- IN
PU
T IM
PE
DA
NC
E (
k )
V = 10 VCE
C
ie
f = 1.0 kHzT = 25 CA
oΩ
Voltage Feedback Ratio
0.1 1 101
2
3
4
5
7
10
I - COLLECTOR CURRENT (mA)
h
- V
OLT
AG
E F
EE
DB
AC
K R
AT
IO (
x10
)
V = 10 VCE
C
re
f = 1.0 kHzT = 25 CA
o
_4
Test Circuits
10 KΩΩΩΩΩ
3.0 V
275 ΩΩΩΩΩ
t1
C1 <<<<< 4.0 pF
Duty Cycle ===== 2%
Duty Cycle ===== 2%
<<<<< 1.0 ns
- 0.5 V
300 ns
10.6 V
10 < < < < < t1 <<<<< 500 µµµµµs
10.9 V
- 9.1 V
<<<<< 1.0 ns
0
0
10 KΩΩΩΩΩ
3.0 V
275 ΩΩΩΩΩ
C1 <<<<< 4.0 pF
1N916
FIGURE 2: Storage and Fall Time Equivalent Test Circuit
FIGURE 1: Delay and Rise Time Equivalent Test Circuit
2N3904 / M
MB
T3904 / P
ZT
3904NPN General Purpose Amplifier
(continued)
TO-92 (FS PKG Code 92, 94, 96)
TO-92 Package Dimensions
January 2000, Rev. B
1:1Scale 1:1 on letter size paper
Dimensions shown below are in:inches [millimeters]
Part Weight per unit (gram): 0.1977
©2000 Fairchild Semiconductor International
SOT-23 (FS PKG Code 49)
SOT-23 Package Dimensions
September 1998, Rev. A1
1:1Scale 1:1 on letter size paper
Dimensions shown below are in:inches [millimeters]
Part Weight per unit (gram): 0.0082
©2000 Fairchild Semiconductor International
SOT-223 (FS PKG Code 47)
SOT-223 Package Dimensions
1 : 1
Scale 1:1 on letter size paper
Part Weight per unit (gram): 0.1246
September 1999, Rev. C©2000 Fairchild Semiconductor International
TRADEMARKSThe following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and isnot intended to be an exhaustive list of all such trademarks.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORTDEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.As used herein:1. Life support devices or systems are devices orsystems which, (a) are intended for surgical implant intothe body, or (b) support or sustain life, or (c) whosefailure to perform when properly used in accordancewith instructions for use provided in the labeling, can bereasonably expected to result in significant injury to theuser.
2. A critical component is any component of a lifesupport device or system whose failure to perform canbe reasonably expected to cause the failure of the lifesupport device or system, or to affect its safety oreffectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
This datasheet contains the design specifications forproduct development. Specifications may change inany manner without notice.
This datasheet contains preliminary data, andsupplementary data will be published at a later date.Fairchild Semiconductor reserves the right to makechanges at any time without notice in order to improvedesign.
This datasheet contains final specifications. FairchildSemiconductor reserves the right to make changes atany time without notice in order to improve design.
This datasheet contains specifications on a productthat has been discontinued by Fairchild semiconductor.The datasheet is printed for reference information only.
Formative orIn Design
First Production
Full Production
Not In Production
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHERNOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILDDOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCTOR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENTRIGHTS, NOR THE RIGHTS OF OTHERS.
PowerTrenchQFET™QS™QT Optoelectronics™Quiet Series™SILENT SWITCHERSMART START™SuperSOT™-3SuperSOT™-6SuperSOT™-8
FASTr™GlobalOptoisolator™GTO™HiSeC™ISOPLANAR™MICROWIRE™OPTOLOGIC™OPTOPLANAR™PACMAN™POP™
Rev. G
ACEx™Bottomless™CoolFET™CROSSVOLT™DOME™E2CMOSTM
EnSignaTM
FACT™FACT Quiet Series™FAST
SyncFET™TinyLogic™UHC™VCX™
LEDTECH ELECTRONICS CORP.
SPECIFICATION
PART NO. : UT1813-83-UJE1-P22-TAA 5.0mm ROUND LED LAMP
OBSERVE PRECAUTION FOR HANDLING ELECTRO STATIC SENSITIVE DEVICES
ATTENTION
Approved by Checked by Prepared by
Sam Yang Min Bao
UT1813-83-UJE1-P22-TAA 5.0 mm ROUND LED LAMP
REV.: 01 Date: 2006/08/05 Page: 1/6
Description
This hyper red lamp is made with AlGaInP/GaAs chip and water clear
epoxy resin.
5.9
8.7
24.0
MIN
.
1.5
TYP.
0.5
MA
X.
A K Notes:
1. ALL DIMENSIONS ARE IN mm.
2. TOLERANCE IS ±0.25mm UNLESS OTHERWISE NOTED.
Description
LED Chip Part No.
Material Emitting Color Lens Color
UT1813-83-UJE1-P22-TAA AlGaInP/GaAs Hyper red Water clear
UT1813-83-UJE1-P22-TAA 5.0 mm ROUND LED LAMP
REV.: 01 Date: 2006/08/05 Page: 2/6
Absolute Maximum Ratings at Ta=25
Parameter Symbol Rating Unit
Power Dissipation PD 75 mW
Reverse Voltage VR 5 V
D.C. Forward Current If 30 mA
Reverse (Leakage) Current Ir 100 μA
Peak Current(1/10Duty Cycle,0.1ms Pulse Width.) If(Peak) 100 mA
Operating Temperature Range Topr. -25 to +85
Storage Temperature Range Tstg. -40 to +100
Lead Soldering Temp.(1.6mm from body) for 5 seconds Tsol. 260
Electrostatic discharge ESD. 300 V
Electrical and Optical Characteristics:
Parameter Symbol Condition Min. Typ. Max. Unit
Luminous Intensity IV If=20mA 3000 5500 mcd
Forward Voltage Vf If=20mA 2.1 2.5 V
Peak Wavelength λP If=20mA 632 nm
Dominant Wavelength λD If=20mA 625 nm
Reverse (Leakage) Current Ir Vr=5V 100 µA
Viewing Angle 2θ1/2 If=20mA 25 deg
Spectrum Line Halfwidth ∆λ If=20mA 20 nm
1. NOTE: THE DATAS TESTED BY IS TESTER 2. Customer’s special requirements are also welcome.
UT1813-83-UJE1-P22-TAA 5.0 mm ROUND LED LAMP
REV.: 01 Date: 2006/08/05 Page: 3/6
Typical Electrical / Optical Characteristics Curves :
Applied Voltage (V)FORWARD CURRENT VS.APPLIED VOLTAGE
Forw
ard
Cur
rent
IF(m
A)
10
20
40
30
50
1.2 1.6 2.0 2.4 2.8 3.0
20.0
Forward Current (mA) FORWARD CURRENT VS. LUMINOUS INTENSITY
Rel
ativ
e Lu
min
ous I
nten
sity
10.00
2000
4000
6000
30.00.0
10000
8000
FORWARD CURRENT VS. AMBIENT TEMPERATURE
0 20 40 60 10080
Forw
ard
Cur
rent
IF(m
A)
10
20
40
30
50
Temperature ( )
0.1 0.4 0.60.30.5 0.2
90°
70°
80°
60°
50°
40°
0° 10° 20°
30°
0.7
0.8
1.00.9
RADIATION DIAGRAM
UT1813-83-UJE1-P22-TAA 5.0 mm ROUND LED LAMP
REV.: 01 Date: 2006/08/05 Page: 4/6
Precautions: TAKE NOTE OF THE FOLLOWING IN USE OF LED
1. Temperature in use
Since the light generated inside the LED needs to be emitted to outside efficiently, a resin with
high light transparency is used; therefore, additives to improve the heat resistance or moisture
resistance (silica gel , etc) which are used for semiconductor products such as transistors
cannot be added to the resin.
Consequently, the heat resistant ability of the resin used for LED is usually low; therefore,
please be careful on the following during use.
Avoid applying external force, stress, and excessive vibration to the resins and terminals at
high temperature. The glass transition temperature of epoxy resin used for the LED is
approximately 120-130.
At a temperature exceeding this limit, the coefficient of liner expansion of the resin doubles or
more compared to that at normal temperature and the resin is softened.
If external force or stress is applied at that time, it may cause a wire rupture.
2. Soldering
Please be careful on the following at soldering.
After soldering, avoided applying external force, stress, and excessive vibration until the
products go to cooling process (normal temperature), <Same for products with terminal leads>
(1) Soldering measurements:
Distance between melted solder side to bottom of resin shall be 1.6mm or longer.
(2) Solder dip: Preheat: 90 max. (Backside of PCB), Within 60 seconds
Solder bath: 260±5 (Solder temperature), Within 5 seconds
(3) Soldering iron : 350 max. (Temperature of soldering iron tip), Within 3 seconds
3. Insertion
Pitch of the LED leads and pitch of mounting holes need to be same
4. Others
Since the heat resistant ability of the LED resin is low, SMD components are used on the same
PCB, please mount the LED after adhesive baking process for SMD components. In case
adhesive baking is done after LED lamp insertion due to a production process reason, make
sure not to apply external force, stress, and excessive vibration to the LED and follow the
conditions below.
Baking temperature: 120 max. Baking time: Within 60 seconds
If soldering is done sequentially after the adhesive baking, please perform the soldering after cooling down
the LED to normal temperature.
8.7(.34)
5.0(.197)
24.0(0.92) Min.
1.0(.04)
1.0(.04)Min.
5.9(.227)
Flat Denotes Cathode
2.54(.100) Nom
MCDL-513SBC4 (5MM 470nm Blue 25°°°°)
Lens Color: Water ClearLens Dimension: 5 mm
Absolute Maximum Ratings At Ta = 25°°°° C
Parameter Max UnitDC Forward Current (mA) 20 mAReverse Voltage 5 VPower Dissipation (mW) 200 mWContinuous forward Current (mW) 100 mWPeak Forward Current, tw ,=1 msec. Duty ,= 1/20 500 mAOperation Temperature (°C) -40°°°° - +85°°°°Storage Temperature (°C) -40°°°° +100°°°°Solder DIP (5 seconds, 1.6 mm from body) Temperature 260 ±±±± 5°°°°C
Electrical Characteristics At Ta= 25°°°°C
Symbol Parameter Test Cond. Min. Typ. Max. UnitVF Forward Voltage IF = 20mA 3.20 3.60 4.30 VIR Reverse Current VR=5V ** ** 10 µµµµA
Part Number Emitted Color Peak Wavelengthλλλλ PEAK
Viewing Angle2θθθθ Degrees
IV (IF = 20mA)MCD
Min Typ MaxMCDL-513SBC4 InGaN Blue 470 25 2,000 3,000 3,500
Notes:1. All Dimensions are in millimeters (inches).2. Tolerance is ± 0.25mm (0.010") unless otherwise specified.3. Protruded resin under flange is 1.5mm (0.059") max.4. Lead spacing is measured where the leads emerge from the package.
LEDTECH ELECTRONICS CORP.
SPECIFICATION
PART NO. : UT1813-83-UJE1-P22-TAA 5.0mm ROUND LED LAMP
OBSERVE PRECAUTION FOR HANDLING ELECTRO STATIC SENSITIVE DEVICES
ATTENTION
Approved by Checked by Prepared by
Sam Yang Min Bao
UT1813-83-UJE1-P22-TAA 5.0 mm ROUND LED LAMP
REV.: 01 Date: 2006/08/05 Page: 1/6
Description
This hyper red lamp is made with AlGaInP/GaAs chip and water clear
epoxy resin.
5.9
8.7
24.0
MIN
.
1.5
TYP.
0.5
MA
X.
A K Notes:
1. ALL DIMENSIONS ARE IN mm.
2. TOLERANCE IS ±0.25mm UNLESS OTHERWISE NOTED.
Description
LED Chip Part No.
Material Emitting Color Lens Color
UT1813-83-UJE1-P22-TAA AlGaInP/GaAs Hyper red Water clear
UT1813-83-UJE1-P22-TAA 5.0 mm ROUND LED LAMP
REV.: 01 Date: 2006/08/05 Page: 2/6
Absolute Maximum Ratings at Ta=25
Parameter Symbol Rating Unit
Power Dissipation PD 75 mW
Reverse Voltage VR 5 V
D.C. Forward Current If 30 mA
Reverse (Leakage) Current Ir 100 μA
Peak Current(1/10Duty Cycle,0.1ms Pulse Width.) If(Peak) 100 mA
Operating Temperature Range Topr. -25 to +85
Storage Temperature Range Tstg. -40 to +100
Lead Soldering Temp.(1.6mm from body) for 5 seconds Tsol. 260
Electrostatic discharge ESD. 300 V
Electrical and Optical Characteristics:
Parameter Symbol Condition Min. Typ. Max. Unit
Luminous Intensity IV If=20mA 3000 5500 mcd
Forward Voltage Vf If=20mA 2.1 2.5 V
Peak Wavelength λP If=20mA 632 nm
Dominant Wavelength λD If=20mA 625 nm
Reverse (Leakage) Current Ir Vr=5V 100 µA
Viewing Angle 2θ1/2 If=20mA 25 deg
Spectrum Line Halfwidth ∆λ If=20mA 20 nm
1. NOTE: THE DATAS TESTED BY IS TESTER 2. Customer’s special requirements are also welcome.
UT1813-83-UJE1-P22-TAA 5.0 mm ROUND LED LAMP
REV.: 01 Date: 2006/08/05 Page: 3/6
Typical Electrical / Optical Characteristics Curves :
Applied Voltage (V)FORWARD CURRENT VS.APPLIED VOLTAGE
Forw
ard
Cur
rent
IF(m
A)
10
20
40
30
50
1.2 1.6 2.0 2.4 2.8 3.0
20.0
Forward Current (mA) FORWARD CURRENT VS. LUMINOUS INTENSITY
Rel
ativ
e Lu
min
ous I
nten
sity
10.00
2000
4000
6000
30.00.0
10000
8000
FORWARD CURRENT VS. AMBIENT TEMPERATURE
0 20 40 60 10080
Forw
ard
Cur
rent
IF(m
A)
10
20
40
30
50
Temperature ( )
0.1 0.4 0.60.30.5 0.2
90°
70°
80°
60°
50°
40°
0° 10° 20°
30°
0.7
0.8
1.00.9
RADIATION DIAGRAM
UT1813-83-UJE1-P22-TAA 5.0 mm ROUND LED LAMP
REV.: 01 Date: 2006/08/05 Page: 4/6
Precautions: TAKE NOTE OF THE FOLLOWING IN USE OF LED
1. Temperature in use
Since the light generated inside the LED needs to be emitted to outside efficiently, a resin with
high light transparency is used; therefore, additives to improve the heat resistance or moisture
resistance (silica gel , etc) which are used for semiconductor products such as transistors
cannot be added to the resin.
Consequently, the heat resistant ability of the resin used for LED is usually low; therefore,
please be careful on the following during use.
Avoid applying external force, stress, and excessive vibration to the resins and terminals at
high temperature. The glass transition temperature of epoxy resin used for the LED is
approximately 120-130.
At a temperature exceeding this limit, the coefficient of liner expansion of the resin doubles or
more compared to that at normal temperature and the resin is softened.
If external force or stress is applied at that time, it may cause a wire rupture.
2. Soldering
Please be careful on the following at soldering.
After soldering, avoided applying external force, stress, and excessive vibration until the
products go to cooling process (normal temperature), <Same for products with terminal leads>
(1) Soldering measurements:
Distance between melted solder side to bottom of resin shall be 1.6mm or longer.
(2) Solder dip: Preheat: 90 max. (Backside of PCB), Within 60 seconds
Solder bath: 260±5 (Solder temperature), Within 5 seconds
(3) Soldering iron : 350 max. (Temperature of soldering iron tip), Within 3 seconds
3. Insertion
Pitch of the LED leads and pitch of mounting holes need to be same
4. Others
Since the heat resistant ability of the LED resin is low, SMD components are used on the same
PCB, please mount the LED after adhesive baking process for SMD components. In case
adhesive baking is done after LED lamp insertion due to a production process reason, make
sure not to apply external force, stress, and excessive vibration to the LED and follow the
conditions below.
Baking temperature: 120 max. Baking time: Within 60 seconds
If soldering is done sequentially after the adhesive baking, please perform the soldering after cooling down
the LED to normal temperature.
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