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Tom Fitzpatrick
UVM CookbookRecipe of the Month:Introduction to UVM Registers
Verification EvangelistDVT
www.mentor.com© 2011 Mentor Graphics Corp. Company Confidential
The Idea Behind The Methodology
OVM & UVM underpin best practices— It's all about people...— Team Development
Peopleware is most important— Develop Skill Set— Common language— Strategy and cohesion— Clarity and transparency
A Guiding Methodology— Provides Freedom From Choice— Avoids Chaos and Repetition— Ease of Use APIs
— Not just for Super-heroes!
TF - UVM Recipe of the Month 10/112
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ObjectiveSeparation of stimulus generation from deliveryRaise the abstraction level of stimulus and checkingTest bench configurationInteroperability— Standard class library & API
Reuse— VIP— Testbench components— Stimulus
JustificationSeveral people can develop stimulusIncrease productivity
Avoid expensive recompilationImportant for intra and intercompany developmentKey to productivity
UVM Foundations
TF - UVM Recipe of the Month 10/113
www.mentor.com© 2011 Mentor Graphics Corp. Company Confidential
For the Design:
UVM Testbench - Architectural Design
DUT
SPII/F
APB
IRQ
For Each Interface:
TF - UVM Recipe of the Month 10/114
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UVC Structural Building Block
DUT
UVC(agent)
SequencerDriver
MonitorConfiguration
Object
seq_item
TF - UVM Recipe of the Month 10/115
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UVM Registers are Layered
DUT
UVC(agent)
SequencerDriver
MonitorConfiguration
ObjectUVC(agent)
SequencerDriver
MonitorConfiguration
Object
TF - UVM Recipe of the Month 10/116
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UVM Registers are Layered
UVM Register Layer providesprotocol-independent register-based layering
TF - UVM Recipe of the Month 10/117
DUT
UVC(agent)
SequencerDriver
MonitorConfiguration
Object
UVM Reg Layer
Predict
RegSeq
www.mentor.com© 2011 Mentor Graphics Corp. Company Confidential
Registers, Blocks & Maps
TF - UVM Recipe of the Month 10/118
R/WChar_Len
RRsrv
R/WGoBsy
R/WRxNeg
R/WTxNeg
R/WLSB
R/WIE
R/WASS
RReserved
31:14 13 12 11 10 9 8 7 6:0R/W
Char_LenR
RsrvR/W
GoBsyR/W
RxNegR/WTxNeg
R/WLSB
R/WIE
R/WASS
RReserved
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The Register Map – uvm_reg_map
Contains offsets for:— Registers and Memories— (Hierachical blocks)— (Sub-maps)
Also provides means to access registers— Handle for target sequencer— Handle for register layer adapter
A block can have > 1 map— AXI Master1, AXI Master2 (Fabric)
TF - UVM Recipe of the Month 10/119
DUT
UVC(agent)
SequencerDriver
Monitor
SQR
SQR
www.mentor.com© 2011 Mentor Graphics Corp. Company Confidential
UVM Register Use Models
Stimulus Generation— Abstraction of stimulus:
– i.e. Set this bit in this register rather than write x to address y— Stimulus reuse
– If the bus agent changes, the stimulus still works— Front and Back Door access:
– Front door is via an agent– Back door is directly to the hardware via the simulator database
Configuration— Register model reflects hardware programmable registers— Set up desired configuration in register model then dump to DUT
– Randomization with configuration constraints
Analysis ‘Mirror’— Current state of the register model matches the DUT hardware— Useful for scoreboards and functional coverage monitors
TF - UVM Recipe of the Month 10/1110
www.mentor.com© 2011 Mentor Graphics Corp. Company Confidential
class spi_reg_block extends uvm_reg_block;`uvm_object_utils(spi_reg_block)
rand divider divider_reg;
uvm_reg_map APB_map; // Block map
function new(string name = "spi_reg_block");super.new(name, build_coverage(UVM_CVR_ADDR_MAP));
endfunction
virtual function void build();
divider_reg = divider::type_id::create("divider");divider_reg.build();divider_reg.configure(this, null, "");divider_reg.add_hdl_path_slice("divider", 0, 16);
APB_map = create_map("APB_map", 'h800, 4, UVM_LITTLE_ENDIAN);APB_map.add_reg(divider_reg, 32'h00000014, "RW");
add_hdl_path("DUT", "RTL");lock_model();
endfunction: build
endclass: spi_reg_block
Block containing Register
Register Model Code Example (Only 1 Reg)
11 TF - UVM Recipe of the Month 10/11
class divider extends uvm_reg;`uvm_object_utils(divider)
uvm_reg_field reserved;rand uvm_reg_field ratio;
function new(string name = "divider");super.new(name, 16, UVM_NO_COVERAGE);
endfunction
virtual function void build();ratio = uvm_reg_field::type_id::create("ratio");ratio.configure(this, 16, 0, "RW", 0, 16'hffff, 1, 1, 1);
endfunctionendclass
Register class with one field
Build is not the component build
A map is a component of a block
www.mentor.com© 2011 Mentor Graphics Corp. Company Confidential
Register Assistant* OverviewRegister/Memory Definition & Management for the Entire Design Process
Central, Scalable & Extensible Register/Memory Datamodel — Enables easy specification of registers— Manages register changes— Eliminates hand coding & resultant mistakes— Completely customizable
Automatically Generates Register Outputs— OVM/UVM Register Package— Synthesizable RTL— Documentation— Extensive roadmap
12
* Included with Certe Testbench Studio Supports the entire design team
www.mentor.com© 2011 Mentor Graphics Corp. Company Confidential
Common Register Path
Generate the UVM/OVM register modelGenerate the DUT registersUse Certe templates to generate UVM sequences, adaptor class& the bus agent
13
Template-Generated
DUT
UVC(agent)
SequencerDriver
MonitorRegSeq
SQR
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14
UVM Register Package Generation
Register Definitions
Optional Blocks & Block Maps
Customer ExampleEarly in project:335 Registers 11,500 lines
Final project: 1,000 Registers 35,000+ lines of Register Package code
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Register Documentation Generation
Communicate the register layer to all team membersFinal documents auto-generatedCustomizable content & style
15
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16
The Architecture – Open & Extensible
DatamodelAPI
API
Block Map
Reg. Definitions
Blocks
Documentation
OVM/UVM Pkg.
Readers Writers
Checks
Control File
RTL
Spreadsheet (CSV)IP-XACTAPI calls
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UVM Coverage
You can specify the coverage model you wish to generate for instances in a blockSimply add a column to your spreadsheet
17
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UVM Register Class Access API
Direct access methodsreg.read() and reg.write()— Access the hardware register and update the register database— Can specify front or back door access
– Front door access takes time and may create side effects– Uses bus agent and consumes clock cycles
– Back door access is instant and does not cause side effects– Uses simulation database and access API (VPI)
— Not used for individual fields
reg.peek() and reg.poke()— For back door accesses, register model updated with result— Can be used for individual fields
The register model has two register variables:— Desired value
– For when a field has been updated, but not the hardware— Mirrored value
– Containing the latest known value
TF - UVM Recipe of the Month 10/1118
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Register Access Method Fields
Type Name Purpose
uvm_status_e status Indicates Access completed OK
uvm_reg_data_t value Data value transfered
uvm_path_e path Front or back door access
uvm_reg_map map Map to use for access
uvm_sequence_base parent Parent sequence
int prior Sequence priority on sequencer
uvm_object extension Transfer extension object
string fname Filename (For reporting)
int lineno Line number (For reporting)
Good news – most of these fields have defaults!
A typical register access only needs a few of these:spi_rm.ctrl.write(status, wdata, .parent(this));
TF - UVM Recipe of the Month 10/1119
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Register Stimulus Examples – Base Classclass spi_bus_base_seq extends uvm_sequence #(uvm_sequence_item);
`uvm_object_utils(spi_bus_base_seq)
// SPI Register model:spi_reg_block spi_rm;// SPI env config object (contains register model handle)spi_env_config m_cfg;
// Properties used by the various register access methods:rand uvm_reg_data_t data; // For passing datauvm_status_e status; // Returning access status
// Common functionality:// Getting a handle to the register modeltask body;
m_cfg = spi_env_config::get_config(m_sequencer);spi_rm = m_cfg.spi_rm;
endtask: body
endclass: spi_bus_base_seq
Sequence base class contains variablescommon to all register sequences:• data, status• register model handle
TF - UVM Recipe of the Month 10/1120
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Register Stimulus Example: Set Divider Valueclass div_load_seq extends spi_bus_base_seq;
`uvm_object_utils(div_load_seq)
// Interesting divisor values:constraint div_values {data[15:0] inside {16'h0, 16'h1, 16'h2,
16'h4, 16'h8, 16'h10,16'h20, 16'h40, 16'h80};}
task body;super.body;// Randomize the local data valueassert(this.randomize());// Write to the divider registerspi_rm.divider_reg.write(status, data, .parent(this));
endtask: body
endclass: div_load_seq
Extends base sequenceRandomizes data value with specific constraintWrites data to divider register
TF - UVM Recipe of the Month 10/1121
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Register Sequence Example – TX Data Loadclass data_load_seq extends spi_bus_base_seq;
`uvm_object_utils(data_load_seq)
uvm_reg data_regs[]; // Array of registers
task body;super.body;// Set up the data register handle arraydata_regs = '{spi_rm.rxtx0_reg, spi_rm.rxtx1_reg,
spi_rm.rxtx2_reg, spi_rm.rxtx3_reg};// Randomize orderdata_regs.shuffle();foreach(data_regs[i]) begin// Randomize register content and then updateassert(data_regs[i].randomize());data_regs[i].update(status, .path(UVM_FRONTDOOR), .parent(this));
end
endtask: body
endclass: data_load_seq
Extends the base classGets an array of register handlesRandomizes the array index orderForeach reg in the array:
Randomize the contentUpdates the register
TF - UVM Recipe of the Month 10/1122
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How Do Front Door Register Accesses Work?
When an explicit register access method is called— The register access method forms a generic register
command:– Address, Data, Read or Write
— This is then sent through a layering to the target bus agent
The layering has to convert:— Generic register requests to
target bus sequence items
This conversion takes place in the adapter — Extended from uvm_reg_adapter
TF - UVM Recipe of the Month 10/1123
DUT
UVC(agent)
SequencerDriver
MonitorRegSeq
SQR
B
Reg
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Register Adapter Class Exampleclass reg2ahb_adapter extends uvm_reg_adapter;
`uvm_object_utils(reg2ahb_adapter)
function new(string name = "reg2ahb_adapter");super.new(name);
endfunction
virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw);ahb_seq_item ahb = ahb_seq_item::type_id::create("ahb");ahb.HWRITE = (rw.kind == UVM_READ) ? AHB_READ : AHB_WRITE;ahb.HADDR = rw.addr;ahb.DATA = rw.data;return ahb;
endfunction
virtual function void bus2reg(uvm_sequence_item bus_item,ref uvm_reg_bus_op rw);
ahb_seq_item ahb;if (!$cast(ahb, bus_item)) begin
`uvm_fatal("NOT_AHB_TYPE","Provided bus_item is not of the correct type")return;
endrw.kind = (ahb.HWRITE == AHB_READ) ? UVM_READ : UVM_WRITE;rw.addr = ahb.HADDR;rw.data = ahb.DATA;rw.status = UVM_IS_OK;
endfunction
endclass: reg2ahb_adapter
reg2bus() converts register itemto bus item – note single access only
bus2reg() converts bus itemto reg item
TF - UVM Recipe of the Month 10/1124
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Keeping The Register Model Up To Date
Need to update register model with results of hardware access— This is referred to as prediction
Two ways:— Auto prediction
– Register model updates based on value written or read back– OK in simple situations where only one way to access the DUT
registers– Requires no additional components
— Explicit prediction (UVM Default)– A predictor component:
– Observes bus analysis transactions– Updates the register model on what it observes
– Works for normal to complex scenarios– Supports hierarchical reuse
TF - UVM Recipe of the Month 10/1125
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UVC(agent)
SequencerDriver
Monitor
reg
Auto Prediction
For ‘simple’ scenarios:— Only sequences accessing the bus agent are register sequences— Register can only be accessed via one bus
The register model updates itself— Based on value read or written to the register
Has to be enabled – reg_model.set_auto_predict(1);
TF - UVM Recipe of the Month 10/1126
RegSeq
SQR
Breq
Reg
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Predictor
Explicit Prediction - Recommended
Supports arbitrary complexity
Predictor component updates register model— Based on any detected bus transaction— Regardless of origin
Supports vertical reuse
TF - UVM Recipe of the Month 10/1127
UVC(agent)
SequencerDriver
Monitor
RegSeq
SQR
reg
Breq
RegBreq
Reg
Breq Breq
Reg
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Explicit Prediction - Recommended
TF - UVM Recipe of the Month 10/1128
PredictorUVC(agent)
SequencerDriver
Monitor
RegSeq
SQR
reg
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Explicit Prediction - Recommended
TF - UVM Recipe of the Month 10/1129
PredictorUVC(agent)
SequencerDriver
Monitor
RegSeq
SQR
reg
reg
PredictorUVC(agent)
SequencerDriver
Monitor
RegSeq
www.mentor.com© 2011 Mentor Graphics Corp. Company Confidential
Register Model Testbench Integrationclass spi_env extends uvm_env;
apb_agent m_apb_agent;spi_env_config m_cfg;// Register layering adapter:reg2apb_adapter reg2apb;// Register predictor:uvm_reg_predictor #(apb_seq_item) apb2reg_predictor;
function void spi_env::connect_phase(uvm_phase phase);if(m_cfg.m_apb_agent_cfg.active == UVM_ACTIVE) beginreg2apb = reg2apb_adapter::type_id::create("reg2apb");// Register sequencer layering part:m_cfg.ss_rm.TOP_map.set_sequencer(m_apb_agent.m_sequencer, reg2apb);// Set the predictor map:apb2reg_predictor.map = m_cfg.ss_rm.TOP_map;// Set the predictor adapter:apb2reg_predictor.adapter = reg2apb;// Connect the predictor to the bus agent monitor analysis portm_apb_agent.ap.connect(apb2reg_predictor.bus_in);
endendfunction: connect
Predictor is a parameteriseduvm base class
Predictor is integrated duringthe connect phase
Register adapter specific tobus agent
TF - UVM Recipe of the Month 10/1130
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Register Read And The Register Mirror
Read cycle results in the register model being updated
mirroredvalue
desiredvalue
hardwarevalue
mirroredvalue
desiredvalue
hardwarevalue
Mirrored and desiredvalue out of step withhardware value
Mirrored and desiredvalue updated at theend of the bus read cycle
Before After
TF - UVM Recipe of the Month 10/1131
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Register Write And The Register Mirror
mirroredvalue
desiredvalue
hardwarevalue
mirroredvalue
desiredvalue
hardwarevalue
Hardware valuechanged by bus write cycle
Mirrored and desiredvalue updated at theend of the write cycle
During After
mirroredvalue
desiredvalue
hardwarevalue
Initial state, hardwareand reg model in sync
Before
TF - UVM Recipe of the Month 10/1132
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Register Model Internal Access And Update()
Indirect methods:— Only access the register database
reg.get(), reg.set(), — Can be used on registers and fields
reg.reset(), reg.get_reset()— set/get the register or field reset value
reg.update()— Cause the hardware to be updated if register model content has
changed via reg.set(), reg.reset() or reg.randomize()— Can specify front or back door access
These methods set the desired value
TF - UVM Recipe of the Month 10/1133
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Register Write And The Register Mirror
mirroredvalue
desiredvalue
hardwarevalue
mirroredvalue
desiredvalue
hardwarevalue
Update() transfersdesired value to HWvia a write bus cycle
Mirrored value updated at the end of the write cycle
update() After
mirroredvalue
desiredvalue
hardwarevalue
Desired value changedby indirect access method (e.g. set())
set()
mirroredvalue
desiredvalue
hardwarevalue
Initial state, hardwareand reg model in sync
Before
TF - UVM Recipe of the Month 10/1134
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Built-In Sequences
Sequences are automatic— Low overhead to use— Useful for initial sanity checks on bus connectivity
Access modes are respected— e.g. Read only registers are not bit bashed— Read only memories are not tested
Memories, Registers or Fields can be opted out of a test— e.g. Clock enable bit— Mechanism is to use the uvm_resource_db to set an attribute for
the register
TF - UVM Recipe of the Month 10/1135
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Register Built-In Sequences
Sequence Name Description
uvm_reg_hw_reset_seq Checks register reset values
uvm_reg_single_bit_bash_seq Checks R/W path to each register bit in a register
uvm_reg_bit_bash_seq Runs single_bit_bash_seq on a register block
uvm_reg_single_access_seq Checks that both front and back door accesses work correctly for a register
uvm_reg_access_seq Runs single_access_seq on a register block
uvm_reg_shared_access_seq If a register is in multiple maps, checks that accesses can be made from each map
TF - UVM Recipe of the Month 10/1136
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Stimulus Reuse (Bridge Example)
SPI master is integrated inside an AHB peripheral block
Host bus sequences can reused as is
Testbench structure changes
SPI Master
APB SPI
AHB to APBBridge
Another DUT
APB ANIAnother DUT
APB ANIAnother DUT
APB ANI
AHBBus Agent
SPI Host BusSequence
TF - UVM Recipe of the Month 10/1137
APBBus Agent
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Stimulus Reuse Code Exampleclass spi_env extends uvm_env;
apb_agent m_apb_agent;spi_env_config m_cfg;// Register layering adapter:reg2apb_adapter reg2apb;// Register predictor:uvm_reg_predictor #(apb_seq_item) apb2reg_predictor;
function void spi_env::connect_phase(uvm_phase phase);if(m_cfg.m_apb_agent_cfg.active == UVM_ACTIVE) beginreg2apb = reg2apb_adapter::type_id::create("reg2apb");// Register sequencer layering part:m_cfg.ss_rm.TOP_map.set_sequencer(m_apb_agent.m_sequencer, reg2apb);// Set the predictor map:apb2reg_predictor.map = m_cfg.ss_rm.TOP_map;// Set the predictor adapter:apb2reg_predictor.adapter = reg2apb;// Connect the predictor to the bus agent monitor analysis portm_apb_agent.ap.connect(apb2reg_predictor.bus_in);
endendfunction: connect
class io_ss_env extends uvm_env;
ahb_agent m_ahb_agent;io_ss_env_config m_cfg;// Register layering adapter:reg2ahb_adapter reg2ahb;// Register predictor:uvm_reg_predictor #(ahb_seq_item) ahb2reg_predictor;
function void spi_env::connect_phase(uvm_phase phase);if(m_cfg.m_ahb_agent_cfg.active == UVM_ACTIVE) beginreg2ahb = reg2ahb_adapter::type_id::create("reg2ahb");// Register sequencer layering part:m_cfg.io_ss_rm.TOP_map.set_sequencer(m_ahb_agent.m_sequencer, reg2ahb);// Set the predictor map:ahb2reg_predictor.map = m_cfg.io_ss_rm.TOP_map;// Set the predictor adapter:ahb2reg_predictor.adapter = reg2ahb;// Connect the predictor to the bus agent monitor analysis portm_ahb_agent.ap.connect(ahb2reg_predictor.bus_in);
endendfunction: connect
TF - UVM Recipe of the Month 10/1138
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Register Stimulus Reuse: Set Divider Value
class div_load_seq extends spi_bus_base_seq;
`uvm_object_utils(div_load_seq)
// Interesting divisor values:constraint div_values {data[15:0] inside {16'h0, 16'h1, 16'h2,
16'h4, 16'h8, 16'h10,16'h20, 16'h40, 16'h80};}
task body;super.body;// Randomize the local data valueassert(this.randomize());// Write to the divider registerspi_rm.divider_reg.write(status, data, .parent(this));
endtask: body
endclass: div_load_seq
Extends base sequence which gets register model handle from config object.Sequence works as before but via the AHB agent
TF - UVM Recipe of the Month 10/1139
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Stimulus Reuse Layer II – Across Fabric
SPI Master
APB SPI
AHB to APBBridge
AXIBus Agent
SPI Host BusSequence
AXIBus
FabricAXI2
AHBBridge
TF - UVM Recipe of the Month 10/1140
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Relevant Parts Of Top Level Environment
class sys_env extends uvm_env;
axi_agent m_axi_agent;sys_env_config m_cfg;// Register layering adapter:reg2ahb_adapter reg2axi;// Register predictor:uvm_reg_predictor #(axi_seq_item) axi2reg_predictor;
function void spi_env::connect_phase(uvm_phase phase);if(m_cfg.m_axi_agent_cfg.active == UVM_ACTIVE) begin
reg2axi = reg2axi_adapter::type_id::create("reg2axi");// Register sequencer layering part:m_cfg.sys_rm.TOP_map.set_sequencer(m_axi_agent.m_sequencer, reg2axi);// Set the predictor map:axi2reg_predictor.map = m_cfg.sys_rm.TOP_map;// Set the predictor adapter:axi2reg_predictor.adapter = reg2axi;// Connect the predictor to the bus agent monitor analysis portm_axi_agent.ap.connect(axi2reg_predictor.bus_in);
endendfunction: connect
TF - UVM Recipe of the Month 10/1141
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UVM Register Package Works with OVM
42 TF - UVM Recipe of the Month 10/11
`include “ovm_macros.svh”`include “uvm_reg_macros.svh”import ovm_pkg::*;import uvm_reg_pkg::*;
class sys_env extends ovm_env;
axi_agent m_axi_agent;sys_env_config m_cfg;// Register layering adapter:reg2ahb_adapter reg2axi;// Register predictor:uvm_reg_predictor #(axi_seq_item) axi2reg_predictor;
function void spi_env::connect();if(m_cfg.m_axi_agent_cfg.active == UVM_ACTIVE) begin
reg2axi = reg2axi_adapter::type_id::create("reg2axi");// Register sequencer layering part:m_cfg.sys_rm.TOP_map.set_sequencer(m_axi_agent.m_sequencer, reg2axi);// Set the predictor map:axi2reg_predictor.map = m_cfg.sys_rm.TOP_map;// Set the predictor adapter:axi2reg_predictor.adapter = reg2axi;// Connect the predictor to the bus agent monitor analysis portm_axi_agent.ap.connect(axi2reg_predictor.bus_in);
endendfunction: connect
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UVM Register Summary
Register model follows hardware structure— Fields, Registers, Blocks, Maps
Register model generator available:— Certe Register Assistant
Register access API:— Internal access – get(), set() etc
– Sets up desired value— External access – Front and Backdoor
Access layered via model— Generic sequences adapted to target bus sequences— Sequence reuse straight-forward
Use explicit predictionBuilt in sequences available for initial testingWorks with OVM
TF - UVM Recipe of the Month 10/1143
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Verification Academy
•ABV •CDC •FPGA Verification•Basic and Advanced UVM/OVM
•Verification Planning
•SystemVerilog Testbench Acceleration•Intelligent Testbench Automation
Wide Variety of Topics
Verification Academy—Provide the necessary skills that enable you to take advantage of today’s latest, advanced functional verification techniques.
New UVM/OVM Online Methodology Cookbook Available too!
TF - UVM Recipe of the Month 10/1144
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Online Documentation - UVM/OVM Cookbook
UVM/OVM docs
Comment-able
PDF printed books
Real code examples
TF - UVM Recipe of the Month 10/1145
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Three Industry Leading Platforms
Vista— Architectural Design, Analysis,
Verification, and Virtual Prototyping
Questa— Highest Performance with
Support for TLM through Transistor
— Unique Technologies Combined for 100X in Verification Per Cycle
— Unified Coverage Tracking and Verification Process Management
Veloce— Hardware Assisted Verification
Platform for Both Acceleration and Emulation
Vista Veloce
Transactions Transistors
Questa
ESL Emulation
UVM/OVM
TF - UVM Recipe of the Month 10/1146
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Future Recipe of the Month Webinars
More UVM Registers: November, 2011— How to write scoreboards and functional coverage at the register
level— Implementing “Quirky” Registers— Register-layer coverage model— Implementing “back-door” register accesses— Scoreboarding at the register layer
Configuring your UVM Testbench: December, 2011— UVM Configuration Database Overview— Desiginging Configuration Objects— Configuration Reuse
Register at http://www.mentor.com/products/fv/series/uvm-ovm-series
TF - UVM Recipe of the Month 10/1147
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Thank you