Using Hierarchy in Design Automation: The Fault Collapsing Problem

Using Hierarchy in Design Automation:

The Fault Collapsing Problem

Raja K. K. R. Sandireddy

Intel CorporationHillsboro, OR 97124,

USAr

[email protected]

Vishwani D. Agrawal

Auburn UniversityAuburn, AL 36849,

[email protected]

11th VLSI Design and Test SymposiumKolkata, August 8-11, 2007

mailto:[email protected]




Aug. 8, 2007 VDAT: Sandireddy & Agrawal 2

Outline• Introduction

– Main idea

– Background on fault collapsing

• Hierarchical fault collapsing– Method

– Advantages:• Smaller collapse ratio

• Reduced CPU time

• Results• Conclusion


The General Idea of Hierarchy

Circuit(top levelIn hierarchy)

Subnetwork analyzed once, placed in library.

interconnects

Lowest-level block (gates and interconnects),analyzed in detail, saved in library.

Analysis at nth level: 1. Copy preprocessed internal detail of n-1 level from library.2. Process nth level interconnects.


Background on Fault Collapsing

DUT

Generate fault list

Collapse fault list

Generate test vectors

Fault model

Required fault coverage

Test Vector Generation Flow


Structural Fault Collapsing

• Equivalence Collapsing: It is the process of selecting one fault from each equivalence fault set.– Equivalence collapsed set = {a0, b0, c0, c1}– Collapse ratio = 4/6 = 0.67

• Dominance Collapsing: From the equivalence collapsed set, all dominating faults are left out retaining their respective dominated faults.– Dominance collapsed set = {a0, b0, c1}– Collapse ratio = 3/6 = 0.5

a0 a1

b0 b1

c0 c1 Total faults = 6


Functional Collapsing: XOR Cell

a

b

c

d

e

g

h

i

j

k

m

c0 c1

d0

d1

Functional dominance examples: d0 → j0, k1 → g0

f

All faults = 24Str. Equ. Faults = 16Str. Dom. Faults = 13Func. Dom. Faults = 4


Hierarchical Fault Collapsing• Create a library

– For smaller (gate-level) circuits, exhaustive (functional) collapsing may be done.

– For larger circuits, use structural collapsing.• For hierarchical circuits, at any level of hierarchy, say

nth level:– Read-in preprocessed (library) collapse data of (n-1) level

sub-circuits.– Structurally collapse the interconnects and gate faults of nth

level.

- R. K. K. R. Sandireddy and V. D. Agrawal, “Diagnostic and Detection Fault Collapsing for Multiple Output Circuits,” Proc. Design, Automation and Test in Europe Conf., March 2005, pp. 1014–1019.

- R. Hahn, R. Krieger, and B. Becker, “A Hierarchical Approach to Fault Collapsing,” Proc. European Design & Test Conf., 1994, pp. 171–176.


A Fault Collapsing Library

Cellname

Cell characteristics Collapsed fault set size

Func.coll.CPU(s)*

No. ofinputs

No. ofoutputs

No. ofgates

Totalfaults

Structural Functional

Equ Dom Equ Dom

Logicgates

n 1 1 2n+2 n+2 n+1 n+2 n+1 -

XOR 2 1 4 24 16 13 10 4 7.9

HA 2 2 5 30 20 16 15 6 9.1

FA 3 2 11 60 38 30 26 12 15.7

* Sun Ultrasparc 5_10 (360MHz, 128MB)


Collapse Ratios for Ripple-Carry Adders

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

4-bitAdder

32-bitAdder

256-bitAdder

2048-bitAdder

8192-bitAdder

Structural Equiv.

Hierarchical Equiv.

Structural Dom.

Hierarchical Dom.

Co

llap

se

rati

o

Total faults 234 1,858 14,850 118,786 475,138

In hierarchical collapsing, faults in lowest level cells (XOR, full-adder, half-adder) are functionally collapsed.Programs used: 1. Hitec (obtained from Univ. of Illinois at Urbana-Champaign)

2. Fastest (obtained from Univ. of Wisconsin at Madison)3. Our program (Auburn Univ.)


CPU Time (sec) Improvement by Hierarchy for Ripple-Carry Adder


Rent’s rule• Rent’s Rule: Number of inputs and outputs

terminals (T) for a typical block containing G logic gates is given by:

T = K × Gα

α ~ 0.5 to 0.65

• CPU time for collapsing a large hierarchical circuit is dominated by the time taken to build the structure of the circuit which is proportional to the T 2 (ref: our previous work).

G isproportional

to area


Hierarchical Ripple-Carry Adder

Here α ~ 1.0, hence the total collapse time is quadratic in circuit size as observed in our experiment.

FA

FA

FA

FA

Hierarchical Implementation of Adder Circuits

Inp

uts

Ou

tpu

ts

2-bit Adder

2-bit Adder

4-bit Adderprop. to G prop. to G


Hierarchical Array Multiplier

n/2×n/2

Additional Circuitry

n × n multiplier

prop. to √G

n/2×n/2

n/2×n/2 n/2×n/2

Here α ~ 0.5, hence we expect the total collapse time to grow linearly with circuit size.

Inp

uts

prop. to √G

Ou

tpu

ts


Collapse Ratios for Array Multipliers

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

2*2 mult.

4*4 mult.

8*8 mult.

16*16mult.

32*32mult.

64*64mult.

128mult.

Structural Equiv.

Hierarchical Equiv.

Structural Dom.

Hierarchical Dom.

Co

llap

se

rati

o

Total faults 84 726 3762 16,842 71,034 291,546 1,181,082

In hierarchical collapsing, faults in lowest level cells (XOR, full-adder, half-adder) are functionally collapsed.Programs used: 1. Hitec (obtained from Univ. of Illinois at Urbana-Champaign)

2. Fastest (obtained from Univ. of Wisconsin at Madison)3. Our program (Auburn Univ.)


CPU Time Improvement by Hierarchy for Array Multipliers


Conclusion• Benefits of hierarchical fault collapsing:

– Better (lower) collapse ratios due to functional collapsing of library cells.

– Order of magnitude reduction in collapse time.

• Possible benefits of smaller fault sets:– Fewer test vectors

– Efficient fault simulation

– Easier fault diagnosis

• Further investigations:– Structural problems (testability measures, static timing

analysis, physical design, etc.) may be solved using hierarchy.

– Functional problems (ATPG, simulation, etc.) may require new hierarchical algorithms.

Dom. Collapsed Set Size (Collapse Ratio)

CPU s

Flat Hierarchical Flat Hier

53,4284 (0.45) 26,5824 (0.23) 27645 40

128-bit multiplier

Documents

Using Hierarchy in Design Automation: The Fault Collapsing Problem