Using HARDSIL® to minimize the impact of extreme temperature on CMOS integrated circuits

VORAGOTECHNOLOGIESAustin,Texas

IntroductionThereisagrowingtrendtoincreasethesophisticationofelectronicsinhightemperaturesystemswithmoreadvancedCMOSdevicesthatcanbeoperatedathightemperatures.This isbeingdrivenbythedesiretoenhance electronic controller systems for extreme environment applications such as avionics, downholedrilling,alternativeenergyandnowexpandingtotheInternetofthings.

AmajorchallengefacingdesignersofsuchsystemsisthatmanyofthecommercialICcomponentsusedtobuildsuchsystemsarenotratedforoperationathightemperatureandtheirreliabilityisatriskwhenusedattemperatures>125˚C.

Commercially available digital and analog CMOS devices mainly operate in moderate temperatureenvironmentsbutdesignerswantelectronicsystemsintendedforuseinextremetemperatureenvironmentsto deliver the same high level of functionality, integration and reliability as commercial devices whileoperatingattemperaturesofupto200˚C.

Unfortunately, due to the limited number of high temperature rated CMOSproducts that are available,systemdevelopersareoftenforcedtochooseacommercialoff-theshelf(COTS)devicewasnotdesignedforoperationattemperaturesgreaterthan125˚C.

ACMOSdeviceoperatingatatemperaturegreaterthan125˚Cislikelytoexperiencesignificantlyhigherratesoffailuresthanitwouldwhenoperatingattemperatures<125˚C.Systemdevelopersmustthereforetakeprecautions at the architectural level toprotect the system fromhigh temperature effects. This is oftenaccomplishedbybuildinginheatdissipationmethodologieswhichaddcost,size,weightandpower(SWAP).Ideally,adesignercouldsimplyselectanappropriateCMOSdevicethatcouldwithstandhightemperaturesupto200˚C.

CMOSLatch-up

AllbulkCMOSdevicesaresubjecttolatch-up.Latch-upeffectsrangefromtransientfailuresthatupsetthelogicstateofthecircuit,functionallydisablingregionsofthecircuitordestroyingthedevice(hardfailure).

Latch-upoccursduetoparasiticdevicesthatarecreatedacrossabulkCMOSwaferthatbecomeproblematicwhen there is a transient event that has the effect of switchingon theparasitic structure. TheparasitictransistorsareconfiguredinsuchawaythatanycurrentflowingthroughonedeviceisamplifiedbytheotherBJT and this positive feedback loop results in a short circuit from VDD to VSS. The parasitic structureresemblesasiliconcontrolledrectifier(SCR)andisshowninFigure1.

Increasingtemperaturereducestheforwardbiasvoltageofthep-ndiode,makingiteasierforatransientevent(neutron,singleover-voltage,currentnoise,orsingleparticle)totriggertheparasiticbi-polartransistorstructureintoan“on”state.Thereductionofthediodeforwardbiascausedbytheincreasingtemperaturereduces latch-up trigger current as the diode ismore easily forward biased and this leads to increasedpossibilityoffailure.

Astemperatureisincreased,thedevicebecomesmoresusceptibletolatch-upbecausetheeffectivenessofap-ndiodetoblockcurrentisdegradedwithtemperature.Increasingtemperatureresultsinincreasedp-njunctiondiodeleakagecurrentaselectron-holepairsaregeneratedinthesiliconlatticeofthesemiconductor

device and collected at the cathode/anode terminals. The p-n junction diode forward-biasing shifts todepletion,makingthediodeeasiertoturnon.Thisleadstoincreasedtransientfailuresrangingfrommicro-latch triggering, destructive latch-up or simple forward diode conduction (high leakage). Micro-latchtriggeringisasubsetofthelatch-upphenomenonwherethedevicecurrentremainsbelowthemaximumspecifiedforthedeviceandisdifficulttoobservedirectlywithintheCMOScircuitcoreregions.Itisinsteadobservedashighleakagecurrent.

Figure1-CMOStwinwellcrosssectionwiththeelectricalschematicoftheparasiticnetworkofdiodesandBJTs.

Micro latch-upmaynot result in thedestructionof a chipbut itwill certainly result in increasedpowerconsumptionandself-heating. Ifparasiticchargespreadingoccurs,chipdestructionbecomesmorelikely.Parasiticchargespreadingofalatch-upeventacrossCMOSdiffusionswillextendthelatch-uptransientfromtheinitialparasiticdiffusiontocouple(viaparasiticbipolarinteractions)withotherregionsofthecircuitthatwere initially unaffected. As CMOS processes scale to smaller geometries, transistor and isolation welldiffusions are in closer proximity to each other. This proximity makes it easier for parasitic transientinteractionstooccur.Theseeventscantriggeractiveconductionbyatransienteventsuchasover-voltage,ESD spike, ionizingparticle strikeorhigh temperature leakage. Figure2 illustratesanover-voltageeventinitiatinglatch-upandtheeffectofparasiticinteractionsbetweendifferentcircuitlocalities.

CMOSLatchupparasiticnetwork

Figure2 - (Left) IVplotofa latch-upover-voltage transientshowing theriseof thesignalover-voltageinitiating latch-up triggering, negative resistance region and latch-up saturation (SCR short). (Right)Voldman(IRPS2005)illustratestheCMOSparasiticinteractions.

IntroductiontoHARDSIL©andBuriedGuardRing(BGR)Technology

HARDSIL©isVORAGOTechnologiespatentedprocesstohardenCMOSdevicesagainsttheeffectsofextremetemperatureandradiation.AnycommercialCMOSmanufacturingprocessthathasbeenenhancedwithHARDSIL©willbelatch-upimmunetoallformsofnaturalradiationandextremetemperaturesupto200˚C.

A Buried Guard Ring (BGR) is created in the CMOS structure as part of the HARDSIL© process. Whenimplementedintotheprocess,theBGRenablesanyCMOScircuittooperatelatch-upfreeattemperatures>200˚C.TheBGRreducesdiodecurrentleakageathightemperaturebyreducingminoritycarrierlifetimesandsignificantlyimprovingthegroundingplaneacrosstheCMOSdevicestructurewithalowresistanceshuntwithintheP-typesilicon.ThisshuntpinsthePwellpotentialto0VandhardenstheparasiticN+/P-emitter,preventing forward bias. To demonstrate the effect of HARDSIL© on diode leakage, two identical teststructuresweredevelopedandobservedover temperature.The results indicated that thediode leakagecurrentwassignificantlylesstemperaturedependentthanthecommercialCMOSdevice.AgraphshowingtheseresultsisgiveninFigure3(thecurrentleakageontheY-axishasalogscale).TheHARDSIL©treatedstructureexhibitsmorethantwentytimeslessleakagethanthecommercialCMOSstructure.

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Figure3-HARDSIL©processdiodeleakageisconsiderablylessatelevatedtemperaturesthancommercialCMOS

TheBGRimplementedonaVORAGOTechnologiesVA10800microcontrollerisshowninFigure4.Theareaabove the light horizontal line is a highly conductive layer beneath the CMOS structures that reducessubstrateresistanceandpreventstheparasiticBJTsfromswitchingon.Thisisthemechanismthatpreventslatch-upfromoccurring.Thereisalsoaverticalimplantthatprovidesahighlyconductiveconnectiontothewellcontacts.

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DiodeLeakageofCommercialCMOSandHARDSILprocesses

CommercialCMOS HARDSIL©

Temperature 25°C 85°C 125°C 150°C 175°C 200°CCommercialCMOS 6.30E-12 9.10E-11 5.30E-10 2.60E-09 1.70E-08 8.60E-08HARDSIL© 3.80E-12 4.60E-11 1.80E-10 3.80E-10 9.40E-10 4.10E-09

Figure4–HARDSIL©BGRonVORAGOTechnologiesVA10800microcontroller

A CMOS circuit with BGR implemented cannot be triggered into latch-up by any on-chip parasitic SCRstructure.TheBGRstructureeliminateslatch-upbyestablishingalowresistanceshuntthroughoutthechipwhichpreventsdiodeforwardbiasingwhichactstolimittheactivationoftheparasiticn-emitters.

Latch-upTestingComparisonBetweenHARDSIL©andCommercialDevices

Usingacommercial(130nm)CMOSprocessandtheHARDSIL©process,twosetsoflatchupteststructuresweremanufacturedandlatch-upcharacterizationtestingconductedacrossatemperaturerangefrom25˚Cto200˚C.Thelatch-updatatakenshowstheeffectofincreasingtemperatureonlatch-uptriggercurrentforthetwosamples.AsignalovervoltageconditionisestablishedbyapplyinganincreasingforwardbiastotheP+/NWL diffusion to conduct P+ emitter current to Vss (parasitic PNP collector). The latch-up testing isconductedusingthesamelatch-upteststructure(layoutat450nmN+/P+)withtwodifferentchipvoltages,coreVDDtestat1.5VandIOVDDtestat3.3V.

CoreVDDLatch-uptestingat1.5V:

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Thetestresultsindicatedthatastemperatureincreases,thetriggercurrentisreducedforthecommercialsample.IncontrasttheHARDSIL©latch-upteststructuredoesnottriggerintolatch-upforalltemperaturesacross the testing rangeup to200˚C. Figure5plots the trigger currentdata for the commercial processsample(dashedline)andtheHARDSIL©processsample.

Figure5-Latch-upcharacterizationfora130nmcommercialCMOSprocessvsHARDSILprocessandlatch-upcharacterizationvs.temperatures(25˚Cto200˚C)atcorevoltage1.5VandN+/P+spacingof450nm.

For thecommercial coreVDD latch-up testdevice the latch-up triggercurrent is reduced from288uA to178uA when temperature is increased to 85˚C. This is further reduced to 109uA when temperature isincreasedto125˚C.Theholdingvoltageforcoredeviceat85˚Cis1.73V(higherthancorevoltageupto145˚C),buttheholdingvoltageisalmostat1.5Vat150˚C,whichimpliesthatacommercialcoredeviceoperatingat150˚Cwillbeatriskfordestructivelatch-upeventifalatch-uptriggeringstimulusoccursinthecorecircuitryasthecoretemperatureapproaches150˚Corhigher.Ambienttemperaturepluselectricalconductionwithinthechipwillincreasethejunctiontemperatureevenhigherthantheoperatingambienttemperature.

TheLatch-uptestdataalsoshowsforCOREvoltageaHARDSIL©testdevicedoesnottriggerintoeitherlatch-up or micro latch-up at up to 200˚C. HARDSIL© devices are observed to be latch-up immune for thetemperaturerange(25˚Cto200˚C)withN+/P+spacingof450nm.

IOVDDLatch-uptestingat3.3V:

CommercialIOlayoutruleshavewiderspacingthancorelayoutrulesduetohigheroperatingvoltageoftheIOat3.3V.ItisunrealistictoexpectthecommercialIOdevicetopasslatch-uptestingatcorelayoutspacingwiththehigheroperatingvoltage.However,latch-upcharacterizationwasperformedontheHARDSIL©test

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devicewiththecorelayoutspacingrulesandtheIOvoltage(3.3V).ThetestresultdatainFigure6showsthatforthecommercialdevice,latch-upistriggeredforalltemperatures(25˚Cto200˚C).Therefore,itwouldbeimpossibletousethetightercorespacinginacommercialIOdeviceoroperateattemperaturesexceeding25˚C.

Incontrast,thelatch-uptestdatafortheHARDSIL©device(usingthesame450nmlatch-upteststructures)willnottriggerintolatch-upormicrolatch-upevenat200˚CwithanappliedIOvoltageof3.3V.HARDSIL©devicesconsistentlydemonstratelatch-upimmunebehaviorevenwhileoperatinginthetemperaturerangeupto250˚C.

Figure6-Latch-upcharacterizationfora130nmcommercialCMOSprocessvsHARDSILprocessandlatch-upcharacterizationvs.temperatures(25˚Cto200˚C)atIOvoltage(3.3V)andN+/P+spacingof450nm.

LifeTestingat250˚ConHARDSIL©18MbSRAMDevice

Adynamiclifetimetestofan18MbCMOSSRAMmanufacturedwithHARDSIL©wasperformedat250˚Cfor2600hours.DuringthelifetesttheSRAMwascycled(daily)from25˚Cto250˚Candclockedat30MHzwhileperformingreadoperations.Testingwasstoppedafter2600hoursastheboardhadbecomeunusableduetotheeffectsofprolongedhightemperatureexposure.TheHARDSIL©SRAMDUTwasstillfunctioningnormallywhentestingwasstoppedandtherewasnoreasontosuspectthatitwouldnothavecontinuedtooperatenormally.

The SRAM was controlled by an HARDSIL© based ARM© Cortex©-M0 microcontroller (available fromVORAGO,partnumberPA32KAS)performingbiterrorchecking(ECC)ontheSRAM.Figure7illustratesthe

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testsetupforthe18MbSRAM.ThetemperatureisreadbytwothermocouplesattachedtothepackageatthetopandbottomoftheSRAMceramicpackage.Heatersareseparatelycontrolled(topandbottom)byanexternalcontroller.Temperatureiscontrolledto+/-0.5˚C.

Figure7-VORAGOlabboardfor18MbSRAMHTlifetest.The18MbSRAM(DUT)isheatedbystripheaterfromexternalcontroller.

AportionoftheheatcontrolplotoftemperaturevpowerthatwasmaintainedduringthelifetestisshowninFigure8fromzeroto1180hours.Temperatureisshowninredwiththescaleontherighthandsideofthechart.Currentconsumption(fortheentirelabboard)isshowninbluewiththescaleonthelefthandside.TheoperatingcurrentoftheSRAM(@250˚C)wasmeasuredat550mA,anddidnotvarythroughoutthetest.Zeroerrorsweredetectedduringthe125trillionreadoperationsat250˚Cduringthecourseofthe2600hoursoftesting.

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Thermocouple placed on top of 18M SRAM device

Temperature controlled by Omega controller

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Hardsil318M SRAM@ 250C

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VORAGO18MbHARDSIL©SRAMheated to250°C

VORAGOHARDSIL©PA32KASARM©Cortex©-M0MCUrunning continuousreadswithECCchecking18Mb SRAMat30MHz

Figure8-TemperatureandCurrentConsumptionof18MbSRAM

The18MbSRAMwasreadbythemicrocontrollerat30MHzcontinuouslythroughoutthetest.SRAMbiterrorcheckingwasperformedbythemicrocontrollerwithECClocatedinthemicrocontroller.TheSRAMisreadinnativemode(ECCisoffandNOTused)duringbitreadsandNOerrorcorrectionorwritebacksareperformedbythecontroller.Adifferentmemorypatternwas loadedeachdaybeforeheatingtheSRAM.Duringthe250˚ClifetestallSRAMaddresses(0to512Kx36)arereadandcheckedforerrorsbytheparitycheckingincontrollerevery5seconds.Nobiterrors,latch-upeventsorcurrentdriftwasdetectedatanytimeduringthe2600hourlifetest.

TheVA10800microcontroller is the latest newproduct tobe releasedusingHARDSIL© technology.HightemperaturetestingisongoingandisapproachingthesamenumberofhoursthatwasaccomplishedwiththeSRAMdevice.ItisexpectedthatthenumberofhoursaccumulatedathightemperaturefortheVA10800willsignificantlyexceedthe2600hourspreviouslyachieved,astheVA10800boardsweredesignedtobebakedinanovenandtheboardwillnotbedestroyedbyhightemperatureexposure.

Stablecurrentconsumptionathightemperatureisareliableindicatorofrobusttechnology.TestsamplesoftheVA10800havebeenexercisedwithmaximumCPUandperipheralthroughputat increasingoperatingfrequenciesfrom20MHzto80MHzupto200˚C.Thecurvesfor20MHz,50MHzand80MHzareshowninFigure9 tobeextremely flatuntil temperatureexceeds125˚C.Whenoperatingat80MHz, theoperatingcurrentincreaseislessthan5%between175˚Cand200˚C.NotethatthemaximumoperatingspeedoftheVA10800isspecifiedat50MHzinordertotoprovideasubstantialguard-band.

Figure9–VA10800CoreIDDacrosstemperature

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TotalSapphireboardIddcorecurrent(A)with18MbSBRAM(DUT)operatingat250Cvs.elapsedtimeattemperaturewithcontinuous30MHzdynamicreadoperationswithbiterrorchecking.Zeroerrorsdetectedafter>1180hoursand16.1Trillionreadoperationswith18MSRAMoperatingat250C.Lifetestcontinuesto2000hoursormore.

TotalVORAGOlabboardIdd corecurrent (A)with18MbSRAM(DUT)operatingat250°CversuselapsedtimeatTemperature withcontinuous 30MHzdynamicreadoperations withbiterror checking.Zeroerrors detected after2600hoursand125trillion readoperations with18MbSRAMoperatingat250°C.Graphshowsresults at1180hrs.

Summary

Latch-upisaphenomenoninallbulkCMOSdevicesthatincreasesinlikelihoodsignificantlyastemperatureincreases.TheHARDSIL©BuriedGuardRingstructurethatiscreatedbeneaththeCMOSdevicehasproventobeeffectiveinimmunizingagainstlatch-up.

ComparisontestinghasbeenperformedusingidenticalCMOSdeviceswithandwithoutHARDSIL©processingimplemented. The HARDSIL© based devices were shown to be latch-up under elevated temperatureconditionswhilethecommercialCMOSdeviceslatched-up.

Extendedtemperaturetestingat250˚ConaHARDSIL©treatedSRAMdevicefor2600hoursdemonstratednoinstancesofmemorybiterrorsorlatch-up.Inthistime,125trillionmemoryreadswereexecutedandstablecurrentconsumptionwasobserved.

HARDSIL®technologycanbeintegratedintoanycommercialCMOSprocess,atanyCMOSgeneration,atanyCMOSwaferfab.ThereisnoyieldimpactonwafersthathavehadHARDSIL©implementedandthereisnoperformanceimpactonthedevicesotherthanhardeningagainsttemperatureeffects,betterESDandnoiseimmunitycharacteristics.

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