Using DSP

to Improve the Performance

of a Doherty Amplifier

Yu Zhao, Masaya Iwamoto, Larry Larson and Peter Asbeck

High Speed Device&Circuit Group

04/21/23

High Speed Device&Circuit Group

Introduction

To reduce DC power consumption in wireless communication» Increase overall efficiency of RF PA

Use Doherty structure

To maintain performance of transmitter» Achieve adequate linearity ( for CDMA and

OFDM)

Use DSP to control Doherty Amplifier

04/21/23

High Speed Device&Circuit Group

Extended Doherty amplifier

» architecture» measured results without DSP

Simulated application of DSP to Doherty amplifier

» control strategy» behavioral model» simulation result

Conclusions

Agenda

04/21/23

High Speed Device&Circuit Group

Low power range» only Main-PA operates» Reff = RL

High power range» Main-PA goes into saturation,

Aux-PA turns on

» Reff = RL

Extended Doherty uses » Achieves wider high efficiency

range

Reff

Zc=RL

/4

Main PA

Auxiliary PA RL

Zo

/4

Pin Pout

Advantages of Doherty Architecture

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0 0.2 0.4 0.6 0.8 1

Pout (normalized)

Eff

icie

ncy

10dB output back-off

Extended Doherty (=4)

Classical Doherty (=2)

Class B

Class A

04/21/23

High Speed Device&Circuit Group

3

4

5

6

7

8

9

10

11

12

13

0 5 10 15 20 25 30

Pout (dBm)G

ain

(d

B)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

AC

PR

1, A

CP

R2

(dB

c)

Doherty

Main Only

Gain

ACPR1

ACPR2

Circuit shows good efficiency over wide power range

Experimental Results --- Gain,Efficiency&ACPR

GCS InGaP/GaAs HBT

0

10

20

30

40

50

60

-10 -5 0 5 10 15 20 25 30

Pout (dBm)

PAE

Gain

Drain efficiency

ACPR is still a concern

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High Speed Device&Circuit Group

ACPR1=-46 to -48 dBc (3:1 VSWR)PAE=10 to 15% (3:1 VSWR)

center=50.00+0.00j

10.0

12.5

46

UCSD_P16_V4.0_F950.bin

PAE=+14.2% ACP1=+47.2dB ACP2=+62.6dB Load:69.00+15.00j PAE=+13.2% Gain=+7.0dB ACP1=+47.8dB ACP2=+63.4dB

Pout=16dBm

ACPR1=-38 to -58 dBc (3:1 VSWR)PAE=12 to 35% (3:1 VSWR)

ACPR1PAE

Pout=25dBm

center=50.00+0.00j

12.515.017.520.025.0

30.0

35.0

3840

4244

4648

5052

54

5658

UCSD_P25_V4.0_F950.bin

PAE=+33.0% ACP1=+46.9dB ACP2=+55.6dB Load:69.00+15.00j PAE=+35.1% Gain=+8.1dB ACP1=+51.4dB ACP2=+55.1dB

Experimental Results --- Load-Pull

Measurements taken at Conexant Systems Inc.

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Relative input of Main & Aux amplifier- A2/A1, Φ2-Φ1 » Maintain magnitude&phase balance

Bias point of Auxiliary amplifier – Vgg2» Maintain magnitude&phase balance and good efficiency

Eliminate additional phase shifter

Design Issues where DSP Can Help

Vgg2

DSP

I

I

Q

Q

Pre_amp

Main

/4

Auxiliary

Input

match

Input

matchA2, Φ2

A1, Φ1 Zc=RL

/4Φ2-Φ1

04/21/23

High Speed Device&Circuit Group

-2

-1.5

-1

-0.5

0

0.5

1

0 5 10 15 20 25 30

-20

-15

-10

-5

0

5

10

0 5 10 15 20 25 30Pout (dBm)

Sweep Φ2 - Φ1

A2/A1 = 1.5 constant

Bias = - 4.0 V constant

Normalized Phase

Normalized Gain

Simulation Results --- Phase Difference Φ1, Φ2

/4Main PA

Auxiliary PA

RF_signal1

RF_signal2

A1, Φ1

A2, Φ2

Ph

as

e D

isto

rtio

n(d

eg

ree

)

Ga

in D

isto

rtio

n(d

B)

Pout (dBm)

04/21/23

High Speed Device&Circuit Group

Design Issues where DSP Can Help

Relative input of Main & Aux amplifier- A2/A1, Φ2-Φ1 » Maintain magnitude&phase balance

Bias point of Auxiliary amplifier – Vgg2» Maintain magnitude&phase balance and good efficiency

Eliminate additional phase shifter

Vgg2

DSP

I

I

Q

Q

Pre_amp

Main

/4

Auxiliary

Input

match

Input

matchA2, Φ2

A1, Φ1 Zc=RL

/4A2/A1

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High Speed Device&Circuit Group

-2

-1.5

-1

-0.5

0

0.5

1

0 5 10 15 20 25 30

Pout (dBm)

Ga

in D

isto

rtio

n(d

B)

Set A1=1,Sweep A2 Φ2 - Φ1 = 90° constant

Bias = - 4.0 V constant

/4Main PA

Auxiliary PA

RF_signal1

RF_signal2

A1, Φ1

-8

-6

-4

-2

0

2

4

6

8

10

0 5 10 15 20 25 30Pout (dBm)

Ph

as

e D

isto

rtio

n(d

eg

ree

)

Normalized Phase

Normalized Gain

Simulation Results --- Power Split Ratio A1, A2

A2, Φ2

04/21/23

High Speed Device&Circuit Group

Design Issues where DSP Can Help

Relative input of Main & Aux amplifier- A2/A1, Φ2 - Φ1 » Maintain magnitude&phase balance

Bias point of Auxiliary amplifier – Vgg2» Maintain magnitude&phase balance and good efficiency

Eliminate additional phase shifter

Vgg2

DSP

I

I

Q

Q

Pre_amp

Main

/4

Auxiliary

Input

match

Input

matchA2, Φ2

A1, Φ1 Zc=RL

/4

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High Speed Device&Circuit Group

Simulation Results --- Different Bias

change bias of Aux-PA

A2/A1 = 1.5 constant

Φ2 - Φ1 = 90° constant 0

10

20

30

40

50

60

0 5 10 15 20 25 30

Dra

in E

ffic

ien

cy

(%

)

Pout (dBm)

-6

-4

-2

0

2

4

6

8

10

0 5 10 15 20 25 30Pout (dBm)

Normalized Phase

Ph

as

e D

isto

rtio

n(d

eg

ree

)

-2

-1.5

-1

-0.5

0

0.5

1

0 5 10 15 20 25 30Pout (dBm)

Normalized Gain

Ga

in D

isto

rtio

n(d

B)

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High Speed Device&Circuit Group

DSP Control Strategy

Given input signal &desired Pout, choose optimum Vgg2, A2/A1 and Φ2(t)-Φ1(t) to maintain relatively constant gain, phase with maximum efficiency

Signal

splitter

a1(t)/a2(t)

Base band X(t)

Power level

X1(t) --- to Main PA

Look-up-table

θ2(t)-θ1(t)

X2(t) --- to Aux PA

Bias of Aux PA

DSP Block

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High Speed Device&Circuit Group

77.5

88.5

99.510

10.511

11.512

0 5 10 15 20

0

10

20

30

40

50

60

10 15 20 25 30

Pin (dBm)Pin (dBm)

Normalized Phase

Gain

DSP Control Algorithm ---Based on simulation data

When Pin < 10 dBm Choose: A1/A2=1.5

Φ2-Φ1 = 100° Vgg2 = - 4.4 V

When 10 < Pin < 15 dBm Change Vgg2 (-3.8 to -3.92 V)

Dra

in E

ffic

ien

cy

(%

)

Pout (dBm)

Ph

as

e D

isto

rtio

n(d

eg

ree

)

Ga

in D

isto

rtio

n(d

B)

Vgg2

Vgg2

Vgg2

-6

-4

-2

0

2

4

6

0 5 10 15 20

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High Speed Device&Circuit Group

-4

-2

0

2

4

6

8

0 5 10 15 20

7

7.58

8.59

9.5

1010.5

1111.5

12

0 5 10 15 20

0

10

20

30

40

50

60

10 15 20 25 30

Pin (dBm)Pin (dBm)

Normalized Phase

Gain

Dra

in E

ffic

ien

cy

(%

)

Pout (dBm)

Ph

as

e D

isto

rtio

n(d

eg

ree

)

Ga

in D

isto

rtio

n(d

B)

Vgg2

Vgg2

Vgg2

When 15 < Pin < 18 dBm Choose: A1/A2=1.5 Φ2 - Φ1 = 90° Vgg2 = - 3.80 V

DSP Control Algorithm ---Based on simulation data

04/21/23

High Speed Device&Circuit Group

4

5

6

7

8

9

10

11

12

5 10 15 20 25-5

0

5

10

15

20

5 10 15 20 25

0

10

20

30

40

50

60

10 15 20 25 30

Pin (dBm)Pin (dBm)

Normalized Phase

GainD

rain

Eff

icie

nc

y (

% )

Pout (dBm)

Ph

as

e D

isto

rtio

n(d

eg

ree

)

Ga

in D

isto

rtio

n(d

B)

Vgg2

Vgg2

Vgg2

When Pin > 18 dBm Choose: A1/A2=1.5 Φ2 - Φ1 = 85° Vgg2 = - 3.92 V

DSP Control Algorithm ---Based on simulation data

04/21/23

High Speed Device&Circuit Group

-5

0

5

10

15

-10 -5 0 5 10 15 20 25

0

5

10

15

-10 -5 0 5 10 15 20 25

Simulated Amplifier with DSP Control

PA’s behavioral model with DSP control (Blue)

and the “best” without DSP control (Red) (choose A2/A1 = 1.5,Φ2 - Φ1 = 90°,Vgg2= -3.44V)

Pin (dBm)Pin (dBm)

Ph

as

e D

isto

rtio

n(d

eg

ree

)

Ga

in D

isto

rtio

n(d

B)

Normalized PhaseGain

04/21/23

High Speed Device&Circuit Group

-2 -1.5 -1 -0.5 0 0.5 1 1.5 2

frequency (MHz)

-70

-60

-50

-40

-30

-20

-10

0

10 15 20 25 30

0

10

20

30

40

50

60

Simulation Results --- ACPR&Efficiency

ACPR (dBc) Efficiency(%)

Pout (dBm)

Blue,with DSP

Red,without DSP

Use matlab to compute spectrum of CDMA signal

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High Speed Device&Circuit Group

Conclusions

Extended Doherty amplifier can achieve high efficiency over wide output power range

PA Simulation based on behavior model shows CDMA ACPR specification can be met with DSP optimization

We believe DSP can make circuit design easier and improve performance significantly