USB and PCIe Compliance and Test

– Planned Success

July 24, 2014 Kimberly McKay

Product Line Manager

Agenda

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Standard’s committee’s and their purpose

USB

PCIe

Other’s (MIPI, NVMe…)

Working Groups

Compliance Workshops

Electrical Compliance

Protocol Layer Compliance

Interoperability

Teledyne LeCroy Introduction

LeCroy’s Protocol Solutions Group (PSG) was formed in October 2004 with the acquisition of CATC Corporation CATC began with USB protocol in 1995

PSG Headquarters in Santa Clara, CA

Part of the Serial Data Division of LeCroy

Catalyst was acquired & added to PSG in 2006

Teledyne acquires LeCroy in 2012

PSG specializes in providing complete protocol solutions for a wide range of serial data standards PCIe, USB, DDR3/4, SATA, SAS, Fibre Channel

Products range from production tools to full protocol analysis systems with intuitive user interfaces and complete traffic generation

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About the USB-IF

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“USB Implementers Forum, Inc. is a non-profit corporation founded by the

group of companies that developed the Universal Serial Bus specification. The

USB-IF was formed to provide a support organization and forum for the

advancement and adoption of Universal Serial Bus technology. The Forum

facilitates the development of high-quality compatible USB peripherals

(devices), and promotes the benefits of USB and the quality of products that

have passed compliance testing.”

737 Member companies

Annual membership fee US$4,000

USB-IF Benefits

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USB-IF introduced trademark-protected logos for use with qualified

products To qualify for the right to display the certified USB logo the product must

pass USB-IF compliance testing for product quality

Member benefits include Eligibility to participate in free USB-IF sponsored quarterly Compliance

Workshops

Free Vendor ID (if one has not been previously assigned)

Opportunities to participate in USB-IF marketing programs and events

A company listing in the USB key contacts list

Eligibility for inclusion in the USB current products list on the usb.org web site

A waived logo administration fee when joining the USB-IF logo program

Discounts on Developer Conferences, products in the e-store, etc

Eligibility to participate in Device Working Groups

And many others...

About the PCI-SIG

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PCI-SIG: Peripheral Component Interconnect Special Interest Group PCI, PCI-X and PCI Express

Formed in 1992 initially as a ‘compliance program’

Became a nonprofit officially named PCI-SIG in 2000

>800 member companies

PCI-SIG Board of Directors has representatives from Intel

Agilent

AMD

Dell

HP

Synopsys

NVIDIA

Qualcomm

IBM

PCIe increasing speed and complexity

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PCI Express

specification

page count for

each generation

As of July 2014 the

Gen 4 spec is at

version 0.3

PCIe Gen 4 Bandwidth

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PCIe Gen 4 aims to solve the problem of “Big Data” bottleneck

• PCIe Gen 4 doubles per lane

throughput to 16GT/s

• Full duplex for total bandwith

of 32GT/s

• Information coming out in

stages prior to spec being

released

• Expected to be the last

generation to be transmitted

over copper wires

• Complicated electronics

design with numerous

electrical and mechanical

issues involved

NVMe

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NVM Express, NVMe, or Non-Volatile Memory Host Controller Interface

Specification (NVMHCI), is a specification for accessing (SSDs) attached through

the PCIe bus. “NVMe was designed from the ground up to provide a very high

performance, low latency interface for PCIe SSD devices that would additionally

allow some of the special characteristics and attributes of NAND flash to be

exposed and exploited by upper layers of the system”

Rapid enhancements to SSD technology are driving faster performance

The storage protocols reside within the PCI Express payload data, and requires

further decoding

It is possible that the only interface to these devices is PCI Express

NVMe 1.0 specification was released on March 1, 2011

NVMe Trace Example

10

The NVMe Commands are actually

PCI Express Memory Reads and

Writes to specific addresses

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NVM Express Workgroup

Companies Driving Enterprise NVMHCI

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The NVMHCI Workgroup includes 90+ members, focused on delivering streamlined NVM solutions.

TM

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Working Groups

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Examples of the USB-IF, Inc. Working

Committees are:

Device Working Group

Compliance Committee

Marketing Committee

On-The-Go Working Group

Standards groups will typically have a number of Working Groups which

participate in various technical activities. These groups contribute to

specifications, consider and debate technology choices and capabilities.

Examples of the PCI Working Groups

are:

IO Virtualization

PCI Express - Cabling

PCI Express – SFF Connector

PCIe over M-PHY

Serial Enabling

Marketing Workgroup

Compliance Testing “Plugfests”

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USB-IF Compliance Workshop #92

July 28 – Aug 1, 2014

The Embassy Suites

Portland, Oregon

PCI-SIG Compliance Workshop #91

October 28-31, 2014

The Westin Taipei

Taipei, Taiwan

PCI-SIG Compliance Workshop #92

December 2-5, 2014

Embassy Suites Silicon Valley

Milpitas, California

First NVMe plugfest May 2013

Location is UNH-IOL

11 participating companies

6 products added

to NVMe Integrators List

Teledyne LeCroy Summit

T3-8/Z3-16 System used

for compliance

14 7/23/2014

Independent Test Houses

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SuperSpeed USB certification testing is now available at several certified independent test labs for all

SuperSpeed USB peripherals, peripheral silicon, and end user hosts using certified host silicon

Example GRL

The SuperSpeed USB Platform Interoperability Lab (PIL) is available for assistance with SuperSpeed

product development

The lab is open for USB-IF members only

PCI-SIG has recently implemented the “PCIe Third Party Test Program”

Designed to alleviate the growing demand for compliance testing

Approved by the PCI-SIG to conduct compliance testing using the same standards

Currently only one approved Third Party Test Lab

May expand to include additional test labs in the future

USB 3.0 Device Compliance Test Requirements

3.0 Electrical Test Spec TX, RX, and Current

Device (& hub) Framework Spec USB-CV (Ch:9)

3.0 Interop Test Procedure

Simplified 3.0 “Gold Tree”

Device Specific Test Spec

Mass Storage Device Class

Others: TBD

3.0 Backward Compatibility Test

Procedure

3.0 Link Layer Test Spec

USB 3.0 devices must first pass USB 2.0 compliance

* Additional test requirements for xHCI host & hubs

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PCISIG Compliance Test Requirements

Compliance testing is split out into sections: Configuration Space

Using PCIECV tool from PCISIG

System BIOS Testing

Using PCIEPT tool from PCISIG

Link and Transaction Layer

Transaction Layer testing

Data Link Layer testing

Testing Link Training

Electrical

Link Equalization/De-emphasis testing

Transmitter Signal Quality

Receiver Jitter Tolerance

17

Data Link

Transaction

Physical

Application

Logical Sub Block

Electrical Sub Block

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Physical Layer Testing

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Physical Layer Transmitter Testing (Tx)

Traditional form of compliance testing

Verify that the output from the device under test (DUT) is transmitted within the compliance limits Ensures signal has sufficient signal quality

Typically tests include: Eye diagrams

Characterization of the SSC (spread-spectrum clock)

Jitter (total, random, and deterministic)

Wide range of other physical-layer tests

As bit rates have increased, this has driven a need for new test methodology to ensure reliable data transfer and interoperability

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PCI Express 3.0 PHY Layer

IC System Board PCIE Connector Add-In Card IC

Signal degrades over long transmission path and connectors

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Normative Jitter measurements are required to be tested at the end of the channel

The measurement tool (oscilloscope) will embed the spec required channel (.s4p) to

simulate the lossy channel and the measurement will be done after the channel has

been emulated

Embed using

EyeDoctor2

Software in the

Oscilloscope

Channel Emulation

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Tx Equalization: De-Emphasis and Preshoot

Equalization schemes account for lossy channel

In USB3.0 continuous time linear equalization (CTLE) is specified

PCIe 3.0 defines de-emphasis and preshoot

Before performing compliance testing the compliance channel must be emulated and the signal must be equalized

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Automated compliance test packages increased speed of testing and reduce complexity for the operator

The scope is used to acquire data and pass the results to SigTest

In USB3.0 the PeRT3 is used to generate precise number of LFPS ping commands to request the DUT to change patterns

This enables fully automated transmitter compliance testing

Automated Tx Testing

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The evolution of receiver test

Receiver testing was not typically required for compliance to older standards, but

is becoming a requirement for newer standards which operate at higher bit rates

Transmitting higher bit-rate signals over the same backplane materials means

that electrical margins at the receiver continue to become tighter:

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Eye at transmitter Eye at receiver

1.5 Gbps

3.0 Gbps

6.0 Gbps

Receiver testing fundamentals

Receiver testing seeks to ensure that the receiving device interprets

the incoming electrical signal as the correct sequence of 1’s and 0’s

From a compliance standpoint, the concept is that if the receiver

works correctly when subjected to a “worst case” electrical input

signal, it should interoperate with any compliant transmitting device.

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Receiver test 101

A typical receiver test consists of two stages:

Calibration: This is an iterative process which adds precise levels of

specific electrical impairments to the output of a receiver tester

(usually a PeRT or BERT). An oscilloscope is used to analyze the

quality of the signal output.

Loopback testing: The calibrated signal is now applied to the device

under test, which interprets it as a pattern of 0’s and 1’s. The DUT re-

transmits the received pattern, which the receiver tester checks for

errors against its transmitted pattern.

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Stage 1: Calibration

The purpose of calibration is to ensure the receiver tester is transmitting

a “worst case” signal:

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PeRT Oscilloscope

Clean eye with no added jitter Added multiple jitter types Added differential-mode noise After long physical channel

Stage 2: Loopback

The receiver tester then compares the the digital pattern as

interpreted by the DUT against what it transmitted, and counts any

errors:

Compliant DUTs must perform to better than a specified Bit Error

Ratio on a signal with the calibrated impairments

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PeRT

DUT

101101010010111

101101010010101

Link equalization

Standards such as PCIExpress Gen3 require that the transmitter equalization settings be negotiated between the transmitter and receiver.

There are two fundamental parts to this type of testing: Does the transmitter switch to the correct equalization setting when requested

to do so by the receiver?

Does this equalization change occur within the specified response time?

This requires test equipment which operates at both the electrical and protocol layers: Protocol-enabled Receiver Tester (PeRT) to operate as link partner to the

DUT and request equalization changes

Oscilloscope with protocol analysis software to check DUT’s transmitter equalization settings and measure response time

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Link equalization example: response time measurement

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PeRT

DUT

Oscilloscope

1. PeRT requests

equalization

change from DUT

2. DUT changes

transmitter equalization

3. Oscilloscope

measures time between

protocol-layer request

and physical-layer

response

Electrical Compliance Test Software

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QualiPHY

QualiPHY is designed to reduce the time and

effort needed to perform compliance testing

Wide array of high-speed serial buses

Selecting a new standard or test setup is

done without leaving the main screen, and

the user can start testing with a single button

press.

QualiPHY

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The QualiPHY framework dialog illustrates the overall software flow, from general set up through

running individual compliance tests. Work from left to right, making all desired settings on each sub-

dialog.

Electrical Compliance Test Software

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The QualiPHY software automates report generation

The Test Report includes a summary table

with links to the detailed test result pages

Link Layer Testing

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Why test the USB 3.0 Link Layer ?

Reliable Delivery of Header Packets

Enables Receiver Detect

Controls Link Training & Bring up

Manages Entry and Exit from Low Power states

Signals & Detects In band Reset

Link error handling

Needed to Gain

Certification!

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USB 3.0 Link Layer Compliance

What is Tested?

Link and Packet Robustness

CRC Error handling

Invalid Link Commands

Timer Deadlines

LGOOD / LCRD Sequences

U0/U1/U2/U3 under controlled conditions

Link Reset

Detection and Initiation

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Link Training Status State Machine (LTSSM)

SS Disabled

SS Inactive

RX Detect

Polling

U0 – Active

U1, U2, U3

Compliance

Recovery

Loop Back

Hot Reset

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Link Polling Sub-states (LTSSM)

Exit Polling to U0 Detect Logical Idle – Must Detect Logical Idle before exiting to U0 TS2 – Polling Configuration TS1 – Polling Active

TSEQ (RX_EQ) – Training Sequence Equalization Both devices must send 65,536 TSEQ

LFPS Polling – Low Frequency Periodic Signaling LFPS will Automatically transition to RX_EQ

RX Detect – Detects Far-End Termination

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TD.7.01 Link Bring Up Test (All devices)

LFPS_Polling

Polling RX_EQ

(TSEQ)

Polling Active

(TS1)

Polling Config.

(TS2)

Exit to U0

The test fails unless PUT Completes

LTSSM

• Send LFPS handshake

• Send TSEQ (at least 65530)

• Send TS1 (at least 8)

• Send TS2 (at least 16)

PUT

Performs

Correct Link

Bring-up

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TD.7.01 Link Bring Up Test (Cont.)

PUT Performs Correct Link Bring-up The test fails unless PUT sends: • Correct Header ACK

•LGOOD_7

• Correct LCRD Advertisement

• LCRD A, B, C, D

• Correct LMP packets

•within tPortConfiguration timeout

• Link stays in U0 50ms

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TD.7.03 Link Command CRC-5 Test

PUT should not accept link commands if either of the Link Command Words has a CRC-5

error

The test fails if:

• link doesn’t go to

recovery within 5ms

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TD.7.09 Header Ack Deadline Test

When LGOOD_x is delayed, PUT must observe 3µs Header ACK time-out before starting Recovery

The test fails if:

• link doesn’t wait 3 µs

for LGOOD

handshake

• link doesn’t stay U0

for at least 50 ms.

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TD.7.08 TX Header Packet Re-transmission

•The test fails unless:

•PUT sends LBAD

•PUT Waits for Retried

packet

•PUT confirms Retried

Packet is same

•PUT Acks Retried packet

• PUT must correctly handle Re-tried packet

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LeCroy USB 3.0 Compliance Suite

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Voyager Compliance Suite verifies ~400 Individual Link, Protocol, PHY, & hub test points for USB 3.0 (USB 3.1 test spec is in development):

Nested

tree

structure

allows you

to select

individual

tests to run

Test monitoring console

LeCroy’s USB 3.0 Compliance Line up

Electrical Test Spec

Transmitter Test

Electrical Test Spec

Receiver Test

Cable & Connector Test Spec

TDR Test

Device (& hub) Frame Work

USB CV

Link Layer Test Spec

Supplemental Hub Tests Interop Tests

WaveMaster 8zi

PeRT3 Test System

TDR S-parm Test

Voyager Protocol Analyzer- Exerciser

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LeCroy’s PCIe Compliance Line up

Electrical Test Spec

Transmitter Test

Electrical Test Spec

Receiver Test

Link and Transaction Layer Tests

WaveMaster 8zi

PeRT3 Test System

Summit T3-8 Analyzer- Exerciser

PCIe Protocol Test Card (PTC)

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NVMe Compliance and Interoperability Testing

UNH-IOL(University Of New Hampshire

IOL) and the NVM Express Promoters

Group are collaborating to create an

Interop and Conformance test program

centered at UNH-IOL.

They have created a test bed to help

products prove interoperability, and

conformance test services to prove that

products follow the NVMe specification

correctly.

Recent Plugfest Feb 2014

Summit Z3-16 Protocol Exerciser

Company Confidential 47 7/23/2014

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Thank You!