Print: First Name: ............................. Last Name:

Student Number:...............................................

University of Toronto Faculty of Applied Science and Engineering

Final Examination - April 18, 2017

ECE342S - Computer Hardware

Examiner - Prof. Natalie Enright Jerger

There are 7 questions and 20 pages. Do all questions. The total number of marks is 120. The duration of the test is 150 minutes.

ALL WORK IS TO BE DONE ON THESE SHEETS! Use the back of the pages if you need more space. Be sure to indicate clearly if your work continues elsewhere.

Please put your final solution in the box if one is provided.

Clear and concise answers will be considered more favourably than ones that ramble. Do not fill space just because it exists!

You are permitted any printed or written materials you wish.

You may use a faculty-approved non-programmable calculator.

Always give some explanations or reasoning for how you arrived at your solutions to help the marker understand your thinking.

State your assumptions. Show your work. Use your time wisely as not all questions will require the same amount of time. If you think that assumptions must be made to answer a question, state them clearly. If there are multiple possibilities, comment that there are, explain why and then provide at least one possible answer and state the corresponding assumptions.

Page 1 of 20

This page is for grading purposes only. The marks breakdown is given for each question.

l[18]

2 [16]

3 [13]

4 [20]

5 [12]

6 [251

7 [16]

Total [120]

Page 2 of 20

I. Testing

[8 marks] (a) Considering the following circuit, fill in the table below that shows which stuck-at faults on the wires a, b, c. and f can he tested with all possible test vectors for this circuit. Place an x in the table entry where each fault is tested.

X1 a

x2 f

x3 E , =Doi C

x1x2x3 a/O a/i b/U b/i c/U c/I f/U f/I

000

001

010

011

100

101

110

Ill

Page 3 of 20

[10 marks] (b) Determine the minimum test set that covers all possible faults in the circuit (you may ignore faults in muxes and FFs).

my

Page 4 of 20

2. Timing analysis.

Assume that tcq and t,, for flip-flops is 1 ns, and t1, is 0.5 ns; the delay through a logic gate is given by 1 + k x 0. 1 ns. where k is the number of inputs to the gate. Consider the circuit below.

clock

16 marksi (a) Assuming = = = = On,s, what is the critical path in the circuit, and what is the minimum clock period for which this circuit will work properly?

Critical path from flip-flop to flip-flop

PageS of 20

[6 marks] (b) Repeat part (a) assuming A, = 0.8ns, A2 = Ons. = 0.5ns. IA4 = 3.Ons.

Critical path from flip-flop to flip-flop

T7ni7 =

[4 marks] (c) Assuming i = 0ns, 2 = 1.8ns. = 3.0im. = 1.7ns, identify all possible hold time violations.

Page 6 of 20

3. From lab

[2 marks] (a) In lab 5. you created an Avalon slave component for your line-drawing algorithm (LDA) module. The LDA module had 6 memory-mapped registers, which were mapped from address Ox 007 00000 to Ox 00700017, therefore taking 24 addressable locations. Why were they not mapped from address Ox 0070000 to OxO 0700005, therefore only taking 6 addressable locations?

[2 marks] (b) Calculate how many clock cycles are needed to execute following segment on a processor similar to what you designed in Lab 6. Assume all instructions take exactly one clock cycle, the R7 register is used as the program counter and data is provided in binary.

mvi R11 #001 %Load to Ri

mvi R2,#010 %Load to R2

mvi R3,#iii %Loopl length

my R5,R7 %Save address of Li

mvi R4,#110 %Loop2 length

my R6,R7 %Save address of L2

sub R4,R2 %Decrement loop2

mvnz R7,R6 %jnz L2

sub R3,Ri %Decrement loopi

mvnz R7,R5 %jnz Li

Clock cycles =

Page 7 of 20

[4 marks] (c) Please complete the Avalon master timing diagram. Based on this figure, what mode is the processor operating in?

CIK

Address

Read ............'""T

Waitrequest

Readdata

PC OXOS

[2 marks] (d) In lab 3. you implemented the LDA program and displayed the result using the VGA pixel buffer. The following code snippet is used to ensure synchronization between Nios II and the VGA controller. How-ever, there is a problem with this code, please point out why this may not work correctly and how it can

he fixed.

/* variable declarations */

int* buffer req = (int*) 0xFF203020; int* resolution_req = (int*) 0xFF203028; int* status_req = (int*) 0xFF20302C;

int main()

draw_line (x0, vU, xl, yl)

while (status_req & 0x0000 0001) ; // masking

Page 8 of 20

[1 mark] (e) In the second week of Lab 6, a simple branching instruction is introduced. This instruction along with the others can be used to scroll a message across the 7 segment displays of the DE I. To provide enough time for us to see the output, a delay loop is used. Why is it required to nest the delay loop for the processor that you designed?

[2 marks] (f) The following diagram shows an incomplete system diagram of Lab 4. Complete the diagram by adding and labeling the missing signals.

WS-0

Page 9 of 20

4. Pipelining

Consider the following code:

=1; while (1) tmpA =

tmpB = tmpA * 7; if (tmpA % 2 == 0) tmpB *= B[i-1];

B[i] = tmpB + i;

Assuming the following latencies:

memory 20 ns multiply 15 ns add 8 n mux 2 n

tsu 2 n tcq 2 n

14 marks] (a) On the next page, draw a pipelined datapath that implements the code given above that gives the maximum clock frequency. Assume that you have 1 memory that holds array B and I memory that holds array A. A memory block can do a read or a write (BUT NOT BOTH) in the same cycle. You can assume the memories are infinitely large. The functional units given above (memory, multiply, add, mux) cannot be subdivided across multiple clock cycles. Be sure to clearly label all wires and functional units in your datapath. You do not need to draw the control logic.

Page 10 of 20

Part (a) Pipelined datapath answer

Page 11 of 20

[2 marks] (b) What is the maximum clock frequency of your pipeline?

Max Frequency =______________

[2 marks] (c) If array A holds only odd numbers, what is the throughput of your pipeline?

Throughput=_________________

[2 marks] (d) If array A holds only even numbers, what is the throughput of your pipeline?

Throughput =

Page 12 of 20

[12 marks] 5. Processors

On the next page, draw the modifications to the datapath that are necessary to implement the Reverse Subtract with Carry instruction:

RSC Rd, Rn, 1mm which performs Rd = 17nm - Rn - C

The instruction encoding is given below:

31:28 27:26 25:20 19:16 15:12 11:0

cond op funct Rn Rd Inm

You do not need to draw the control logic but clearly indicate if any new control signals are needed to implement this instruction.

Page 13 of 20

4

Extend

ResuUW

CLK CLK

PCSrcM PGdrW

R& 'ril kip rik V McmtoRegM li ile V MeidNrileM

Cond Unit

CLK

ALUFIO r WE

LURtUItE A RD L ReidDataW

Data

I Memory

WD WdtoDtaE.

CLK

CScl) P( E Control rwru o P ReqvvWeE Un it Unt

Mni l 2 L M lck,l

Folyl

Rd

Ll/Vit 1) ALU(lcP

P Al Id

N1 W I OF

AW( PrrxhF

A li&E

2

FlapVV tnD FwjWrdE rnPrc 0

CLK GLK

Al WEJRDI A RD

Instruction A2 RD2 Memory

A3 Register W 0 File

R15

CLK

CLK

CIK

F (r' Cool

RjWtoD wlit Frnt'RgD

Op ALUCotwft) L1 1hffYJ 'n.1

r hi) 8,r anchE /\1FJ rD ALL)SrcE

ky'/nF 13 F jWr tL

CLK CLK

LRiD WE3 A RD

—1115

RD 1

Instruction [LLA2D A2 RD2 Memory

L A3 Register WD3 File

PCP1 4F R15

4 1

Extend

CLK CLK

PCSrM

MomtoRojM liF 13rgW

Ph

Cond Unit

) CLK

WE

AIUResultE TI A RD

-

Data Memory

WriteDataE WD

ResultW

6. Asynchronous Circuits 1

(a) For the table given below, reduce the flow table by using the concept of compatible states. First, transform the FSM to a Mealy Model. Show your work using merger diagrams and draw the simplified flow table for the resulting finite state machine.

9 marks] i. Fill in the Mealy outputs

Present state w2wl =00

Next 01 State

10 11 Output

z Output (Mealy)

00 01 10 11

A A C - 0

B D B - E 0

C G -

- 1

D A C - 0

E - B -

0

F - B OF -

G - F H

H

I A(JD - - i

[6 marks] ii. Merger Diagrams

[10 marks] iii. Simplified Flow Table (provided table may contain more entries than needed)

Present state

Next State w2w1 =00 01 10 11

Mealy Output (z) 00 01 10 11

Page 16 of 20

7. Asynchronous Circuits 2

(a) Given the flow table below: Present

state Next State

w2wl=00 01 10 11 Output z2zl

A A C B 00

B I) B C® 10

C © D © B 01

D A OD C B 11

[4 marks] i. Fill in the relabeled Flow Table below

Present state

Next State w2w 1 =00 01 10 11

Output z

[8 marks] ii. Draw the transition diagram. Indicate the encoding used for each state.

Page 17 of 20

[4 marks] iii. Provide the final excitation table that resolves any state transition problems

Page 18 of 20

This page is intentionally left blank. You may use this as scratch to solve the exam but make sure your answers are clearly written in the space provided by the question.

Page 19 of 20

This page is intentionally left blank. You may use this as scratch to solve the exam but make sure your answers are clearly written in the space provided by the question.

Page 20 of 20