1/12/2020

Xilinx Vivado 2019.2 WebPack (or full-licensed version) installation steps on a Windows 10 machine for EE354L and EE560.

1. If you do not have an account with Xilinx, create an account at https://www.xilinx.com/registration/create-account.html If you have an account already, go to any Xilinx site (say Xilinx.com) and login.

Go to the top right corner, click on and sign in.

2. Make sure that you have adequate disc space (about 40 GB) for this installation.

2.1 Make sure that you have administrative privileges on your windows laptop. 2.2 Installation Guide (keep the following two items open so that we can refer to them if we encounter any problems.

Vivado Design Hub - Installation and Licensinghttps://www.xilinx.com/support/documentation-navigation/design-hubs/dh0013-vivado-installation-and-licensing-hub.html

Vivado Design Suite User Guide UG973 (v2019.2) December 17, 2019 Release Notes, Installation, and Licensinghttps://www.xilinx.com/content/dam/xilinx/support/documentation/sw_manuals/xilinx2019_2/ug973-vivado-release-notes-install-license.pdf

2. After logging into your account, go to https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools/2019-2.html Scroll down and locate the following.

And click on the Xilinx Unified Installer 2019.2: Windows Self Extracting Web Installer link.

3. That takes you to another page displaying your profile information and the following download button.

4. The following gets downloaded to your downloads folder.

5. Double-click on it to extract it. It will ask your permission to run a setup.exe and then you will see the following

Click on Allow access.

6. Next screen

6.1 Check your OS version.

Select the Start button > Settings > System > About

On mine today

6.2 Select Start > Settings > Update & Security > Windows Security > Virus & threat protection > Manage settings

I had the protection turned on by default.

I have set it off for this installation.

6.3 We need to remember to turn it on again.

6.4 Now press next on the Xilinx screen

7. Select Download and Install now and also provide your login credentials

8. Agree to the three license agreement requests

9. Select Vivado

10. Though we have licenses and can install any of the three, WebPACK is adequate for us.

11. EE354L and EE560 students can skip SoCs to save some disc space. VDI installers: Please select SoCs also, as we may be using ZYNQ SoC (System on Chip) for future projects.

12. Note all the details. Hope you have enough space available on your hard disc. Click next.

13. Note the details and click on Install.

14. Now you are going to babysit for a while. So, you can work on something in parallel occasionally checking the progress of downloading and installing. It is better to do this installation at school as download speeds are higher there.

It wasn’t bad. Finally, it took 42 minutes to download the 11.34 GB.

14.1. Override any firewall blockages during the installation process.

14.2 It took one hour to install. Not bad 😊.

14.3 Click OK.

15. Notice the icon placed on your desktop.

16. Now we us talk about licenses.Extract from page 8/61 of ug973

So, nothing more needs to be done! 😊

16.1 In future, if you (or the VDI installers) need to upgrade to full installation, you can point your LM_LICENSE_FILE variable to

Then if you are invoking the tool from home, you need to do VPN to access USC Xilinx licenses served by the USC license server lic-xilinx.usc.edu

17. Please go to your windows setting and turn on It was

After turning on protection

17. Disc usage after deleting the 67 MB file in the downloads folder

I checked my C:\ drive and noted that this installation consumed 15.3 GB (63.41 – 48.10).

18. Add Nexys 4 board file to Vivado:

Reason for adding a board file:Vivado recognizes some boards made by Xilinx and Digilent through board files. The Nexys 4 FPGA board, that we are using, is made by Digilent. By adding Nexys 4 board file to Vivado, we can specify the board as Nexys 4 rather than selecting the specific FPGA part, its package style, and speed grade carefully.

For example, without adding the board file for Nexys 4, we have to select the FPGA part as xc7a100t and package as csg324 and speed grade as 1.

But we often do not remember all that. We certainly remember that we are using Nexys 4 board.

Procedure to add the board file: I have downloaded the board file the Digilent site and held it in a zip file as nexys4.zip. Please download the zip file, extract the folder nexys4 and place it in the board_files directory C:\Xilinx\Vivado\2019.2\data\boards\board_files in the Viviado installation directory as shown below.

This facilitates selecting the board as nexy4 while setting up a new project.

Your selection of the board as Nexys 4, when you create a project, results in recognizing the FPGA device as

19. Synthesizing a sample project, thereby testing your Vivado installation: Your TA will cover this in detail using the following two files in the Verilog design source file: test_nexys4_verilog.vXilinx Design Constraints file (.xdc file): test_nexys4_verilog.xdclinks to files and folders:ee254l_lab_manual test_nexys4_verilog_sources_only test_nexys4_verilog.zip

19.1 A short 21-minute video walking you through setting up the project for test_nexys4_verilog and synthesizing the same .mp4 19.2 the snapshots of the above synthesis process: Xilinx_project_synthesis_on_Vivado .docx .pdf19.3 Some references for the TAs:ug893-vivado-ide.pdfhttps://www.xilinx.com/content/dam/xilinx/support/documentation/sw_manuals/xilinx2019_2/ug893-vivado-ide.pdf