University of Hawaiiidlab/project_files/salt/... · 2002-09-17 · Return to your MySPIE ToDo list and approve or disapprove this submission. Your manuscript will not be published

Monolithic Multi-channel GSa/s Transient Waveform Recorder for

Measuring Radio Emissions from High Energy Particle Cascades

Gary S. Varner*a

, Peter Gorhama, and Jing Cao

b

aDepartment of Physics and Astronomy, University of Hawaii at Manoa

bCollege of Engineering, University of Hawaii at Manoa

ABSTRACT

A number of particle astrophysics initiatives to exploit radio emission from high energy particle cascades require high-

frequency sampling of antenna array signals. Nyquist-limited sampling of GHz frequency radio signals for an antenna

array may be accomplished by commercially available test units. However, these technologies are incompatible with

the size, power and cost constraints of long-duration balloon or satellite flight. Taking advantage of low trigger rates

for such arrays, high resolution digitization may be performed a postori, at much slower speed and power, on

waveforms stored in analog storage cells. This paper presents the design and performance simulation of a multi-

channel CMOS VLSI ASIC named STRAW (Self-Triggered Recorder for Analog Waveforms), optimized for low

duty-cycle, high sampling frequency operation.

Keywords: GSa/s, digitizer, RF, CMOS, UHE cosmic rays, transient waveform recorder

1. INTRODUCTION In the history of astronomy surprises have occurred in every new regime explored, and frequently the most important

results have not been those that were predicted. An example of contemporary interest has been the window which is

opening to the observation of Ultra High Energy (UHE) cosmic ray

events[1]. Observation of such events, in excess of several times

1019 eV, has spawned a great deal of experimental and theoretical

interest. Notably, no clear cutoff in particle energies has been

observed to date from a variety of experiments[2], in contrast to

expectations for the removal of such events through interaction with

the cosmic microwave background[3], as may be seen in Figure 1.

Placing constraints on the cornucopia of theoretical models[4],

which have arisen to explain the energy spectrum at highest

energies, has led to the development of vast detector arrays[5]. At

some point the practical limits of extending these proven air shower

detection techniques will be exhausted. This may be seen in the

overall cosmic ray energy spectrum as shown in Figure 2. Such low

event rates at the upper end of the energy spectrum require

significant detection volumes. One promising technique for

improving the effective detection volume is by means of measuring

coherent radio pulses produced in a shower medium as predicted by

G.A. Askaryan[6]. Recent beam test measurements[7] of this

technique in both sand and salt have demonstrated the viability of

this technique. Figure 3 depicts the beam test configuration used at

SLAC to measure the Askaryan-effect RF pulses for simulated large

electro-magnetic showers as produced in high energy cosmic

showers in dense material.Figure 1: Upper end of detected cosmic ray

spectrum.

*Corresponding author: [email protected]

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Figure 2: Cosmic ray flux fall-off at high energies.

Figure 3: Askaryan-effect measurement set-up at the SLAC Final Focus

Test Beam facility.

Results from the beam tests at the SLAC Final Focus Test Beam facility are shown in Figures 4 and 5. Figure 4 shows

the expected shower profile with measured data points overlaid, indicating excellent agreement with expectation. The

inset diagram in Figure 4 shows the time-domain response of an antenna to an Askaryan pulse.

Figure 4: Shower profile and temporal signature for gamma-ray emulation of a cosmic ray shower event.





0 2 4 6 8

Time (ns)

Figure 5: Detailed antenna response and polarization measurement.

In Figure 5 above is seen the temporal response of a pair of cross-polarized antennas, clearly indicating near total linear

polarization of the recorded RF pulse. Note that the depolarization after about 2ns is due to reflections inside the test

box. This polarization may be exploited to clearly identify Askaryan-effect RF-pulses from other background sources

since thermal noise is incoherent and anthropogenic noise is largely circularly polarized. Another key feature of this

measurement technique is the ability to determine the shower energy with a single-point measurement, a huge

advantage over calorimetric methods. In Figure 6 the scaling of the total shower energy is seen from the SLAC

experiment.

The left-hand side of Figure 6 demonstrates

the functional dependence of the measured

electric field strength from the shower. On

the right, the frequency dependence of the

electric field is plotted. Fitting to an empirical

formula[8] for the field strength scaling:

)/(4

1

0.011 0

0

TeV

W

R

KAE T

where R is the distance to the source, is the

radio frequency, and is the decoherence

frequency (2500 MHz for silica sand and

scales roughly as the radiation length). A0

and have empirically determined values[7]

and WT gives the shower energy as a product

of the total number of electrons Ne: WT = Ne

We , where is the thickness of the radiator in

radiation lengths and We the electron energy.

Figure 6: Field strength scaling with shower energy and frequency.





Finally, K and account for material and aperture corrections, respectively. Armed with such a scaling law and

needing only to determine the distance to the shower, a good estimate of the shower energy may be obtained.

Returning to the right-hand side of Figure 6, it may be clearly seen that significant signal strength exists at GHz

frequencies. Taking these requirements into consideration, as well as practical limitations on atmospheric propagation,

antenna response and low-noise amplifiers, the requirements for a data recording system may be summarized:

>= 1GHz analog input bandwidth

multi-GSa/s sampling rate

minimum phase distortion for clean polarization determination

maximum dynamic range (>= 9 bits)

internal Analog to Digital Conversion (ADC)

short recording period (100-200ns if optimally matched)

self-triggering with fine threshold adjustment strongly desired

deadtimeless

The next section compares these requirements to capabilities of published and available methods. Based upon the

shortcomings of what is already available, Section 3 defines the operating specifications and simulated performance for

a CMOS chip capable of meeting the requirements.

2. HIGH SPEED TRANSIENT DIGITIZERS It has long been the dream of experimentalists to utilize the flexible triggering, high analog input bandwidth and high

sampling speed of modern digital sampling oscilloscopes as a Data AcQuisition (DAQ) system. For a very limited

number of channels and with large readout latencies, this is an option. The high cost per channel, limited dynamic

range within gain scale and unneeded agility in time base and gain are not well matched to large channel count, fixed

parameter, long-term installations. Likewise, a more traditional solution of using fast ADCs followed by some type of

post sample processing has limitations. High analog input bandwidth and high sampling speed ADCs suffer from low

precision, high cost, high power consumption and the need for high-speed digital signal processing downstream.

Thus, the dream may be recast as desiring to have “an oscilloscope on a chip”. A number of analog pipeline and

waveform digitizing systems have been developed for High Energy Physics (HEP) systems in which detector signals

are captured as “snap shots”, that is, sampled at high frequency for a limited period of time. These signals may be

stored in a fast analog memory and retrieved at a lower rate and digitized with a slower ADC before a new waveform is

acquired[9]. Coming full circle, this scheme has in the past formed the core of the LeCroy high-speed

oscilloscopes[10].

A survey of the literature indicates that previous successful analog pipeline/Switched Capacitor Array(SCA)

implementations have been generally optimized for two different detector readout modes. The first, well-suited to a

colliding beam environment, is based on sampling at a given fixed rate. Keeping an analog record of the signal before

and after the event of interest allows for pile-up rejection and even signal extraction from the tail of a preceding signal,

essential for a high rate environment. A second implementation is intended for intermittent, triggered applications. As

such it has been successfully used for reading out Photo-Multiplier Tubes (PMTs), for instance from large channel

count optical Cherenkov detector arrays. Upon closer inspection the various analog storage architectures are

conceptually very similar and are distinguishable only in terms of their operating mode (common start versus common

stop), means of storing and retrieving a stored signal on a sampling capacitor and the means of converting this

information into a digital value. An excellent comparative summary of these distinctions for various SCAs is given in

Ref. [11]. Based on this and augmented by recent publications and private communication, Figure 7 provides a

summary of the sampling speed and analog bandwidth for various designs. Because of space limitations, the reader is

referred to the references for further details on the specifics for each design. In most cases, the analog input bandwidth

has not been specified and so an estimate has been made based upon the input capacitance and technology or through

communication with the authors. Figure 7 in addition compares the performance for a few commercially available





ADCs. This is somewhat misleading in that the channel density for these devices is low, the power high and the

resolution only marginal. Even so, the SCA-based schemes still compare favorably.

High Speed Digitizer Comparison

10

100

1000

10000

10 100 1000 10000

Analog Bandwidth [MHz]

Sa

mp

lin

g R

ate

[M

Sa

/s]

ZEUS[12]

RD2[13]

Kleinfelder[14]

Haller[15]

ADeLine1[11]

DSC/DRS[16]

AD9410[17]

CLC5957[18]

TLV5580[19]

ADS5102[20]

MAX1449[21]

Desired Max.

Operating Region

Figure 7: A comparison of high-speed digitizers with > 8 effective bits.

Apart from possibly the DRS chip, none of these devices are obvious matches to the performance requirements stated in

the previous section. Implemented in a deep sub-micron process, the DRS design is potentially suitable, though the

horizontal error bar indicates that there is still uncertainty in the analog bandwidth as it has yet to be measured[17].

Also, it should be mentioned that the author is aware of a revised version of the Kleinfelder design[22], which is

potentially suitable. At the moment, however, none of the proven designs has the required analog input bandwidth,

sampling rate and self-triggering features needed for the next generation of RF detector readout.

3.THE STRAW2 CHIP Based upon the desired performance outlined above, a chip design has been pursued which attempts to extend the

successful SCA architectures mentioned above to higher sampling frequencies and analog input bandwidths. In

addition, as it is envisioned that operation independent of an external trigger will be the normal operating mode, self-

triggering capability is essential. During the procedure of exploring what is possible via SPICE simulation for a deep

sub-micron (0.25mm) CMOS process, the concept of a Self-Triggered Recorder for Analog Waveforms (STRAW) took

shape. In the initial version, STRAW1, 32 RF input channels were considered as well as rather simplistic triggering

circuitry. Further study indicated that better input impedance matching and elaborate triggering was required, radical

enough a redesign as to increment the design number to clearly distinguish. In Table 1 is codified the design

parameters for the STRAW2 design. Essential to the design is the performance of the analog input bandwidth and

triggering. These will be addressed in following subsections. It might be argued that 12 bits of ADC aren’t really

needed, as the dynamic range is rather modest. However, since the signals to be extracted are largely buried in the

noise, a number of bits dedicated to sampling the noise baseline with high precision are considered important. Since

the ADC is of Successive Approximation (SAR) type, only fractional additional deadtime is incurred by extending to

12 bits.





Table 1: Critical design parameters for the STRAW2 chip.

> 1GHz common

256 ind. Adj.

32 OR of 16

16 multiplicity

1-2 GHz high+low

12 32 bits/ch.

16 ms cascade

Triggering

STRAW2 Design Parameters

Input bandwidth

# of channels

# of RF inputs

Sampling rate

Analog

ADC (SAR) bits

Digitize deadtime

High level threshold

Low level threshold

High level logic

Low level logic

Comparator type

Monitor scalers

Trigger type

# SCA/channel

Another item of note in Table 1 is the digitization deadtime. As will be seen below, provision will also be made to use

an external ADC. In this case the deadtime could be reduced to a few mili-seconds, but still represents a significant

deadtime once a trigger is accepted. Rather than focus on a fractional increase by parallelizing the readout and

digitization, another strategy has been pursed. No matter how rapid the acquisition deadtime, there is still a finite

chance of missing events of interest. To address this issue, it is expected that multiple STRAW2 chips will be used in

parallel. Each chip generates a trigger signal and this information is collected externally by a trigger sequencer, which

subsequently issues a hold to one chip per trigger. Given the low rate for real events, and the desire to catch possible

“double-bang” events, two or three deep buffering is expected to be adequate. One other item of note in the Table is the

provision for monitoring scalers. These are intended to monitor the noise trigger rate for the low-level threshold

comparators. In order to operate right at the noise threshold, multiplicity logic is used on the random noise triggers to

distinguish a possible event signal from pure noise. In order to “ride” the noise level, feedback on the individual

channel trigger singles rates is a necessary input for adjusting the trigger threshold. More on the triggering details will

be provided in subsection 3.3 below.

A block diagram of STRAW2 functionality is shown in Figure 8, with each of the key functional blocks indicated.

Figure 8: Block diagram illustrating the functional components of the STRAW2 design.





As seen in Figure 8, 16 RF signals are brought into the array of 32 rows by 256 columns. Every other SCA channel is

used to log analog trigger information on a per-channel basis. The purpose of this is twofold: for diagnostics of the

recorded transient signals that lead to the generation of a trigger, as well as monitoring comparator status. The ADC,

analog multiplexing and trigger control elements in this block diagram are straightforward. Emphasis in the next three

subsections focus on design elements crucial to the success of the design. Specifically, the first subsection on the

storage of the analog waveforms addresses the sampling frequency, linearity and gain. A second subsection analyzes

the critical issue of analog input bandwidth. Finally, in the last subsection, a preliminary study of triggering on high-

speed bipolar signals is presented.

3.1. Analog Waveform Recording

The design and performance expectations for the SCA storage elements are similar to those for other designs targeted

for a deep sub-micron (0.25 m) process[16,22]. Delay timing is implemented with an inverter chain whose propagation

delay time is adjustable by means of either voltage rail or bias current adjustment.

Figure 9 shows a SPICE simulation of

the sampling frequency versus

adjustment voltage for a simple ring-

oscillator circuit implemented in the

TSMC 0.25 m process. This process

can be tuned to use a 3.3V Vdd (thick

oxide option) or 2.5V. Throughout the

rest of this document, results are

shown for Vdd = 2.5V. Adjustment of

the control voltage as shown in the

figure indicates operation the sampling

frequency of interest for the design

specification, 1-2GHz, should be

possible. In the future it may be

possible to frequency lock the

sampling frequency to an external

clock reference using an internal

Delay Locked Loop (DLL), however

for the current iteration it is considered

unnecessary and a simple control loop

will be added externally, if necessary.

Simulated Frequency Adjustment range

0

0.5

1

1.5

2

2.5

1.2 1.7 2.2 2.7

Vadjust [V]

Sam

plin

g F

req

[G

Hz]

Figure 9: Sampling frequency SPICE simulation results.

Similar to other previous designs, the input voltage is not buffered, but directly switched onto the storage capacitive

element. However, as may be seen in Figure 10, the actual readout is mechanism is different. Specifically, during

readout neither the charge nor the stored voltage is directly transferred, but rather the conductance through the storage

FET. This technique is reminiscent of that employed for the readout of an active pixel sensor[23]. Avoiding the direct

transfer of the stored quantity avoids issues of readout cross-talk and parasitic bus capacitances. In addition, each

storage element can be made quite compact, allowing for a dense array of storage cells. In the STRAW2 design the

storage FET is sensed across a variable pull-up resistor. By changing the resistor, the effective voltage gain may be

changed. Figure 11 illustrates the expected output swing versus stored waveform input voltage with a 40k pull-up

resistor. For small signal amplitudes, the output response is rather linear. However, to obtain maximal linearity, it is

expected that a dedicated calibration would need to be performed. One disadvantage of this method is that the limited

dynamic range of these inputs could become even more modest. Based upon the storage capacitance an idealized

estimate for the rms noise for each sample:

mVC

kTv

store

rms 23.0





Storage Cell Simulation

y = 6.2891x - 2364.8

R2 = 0.993

0

100

200

300

400

500

600

700

350 400 450 500

St o red W avef o rm ( V in) [ mV ]

Rload = 40k

Gain:

Figure 11: SPICE simulation of SCA gain and linearity.

Figure 10: SCA cell simplified schematic.

An estimate for the working voltage of this configuration is something like 1V, which corresponds to approximately 12-

bits of dynamic range. The effective gain of the readout may then be considered to be the amount by which the least

significant bits of the ADC will be buried in the noise. That is, a gain of 8 corresponds to 3 bits of ADC noise

sensitivity. In summary, simulation and simple calculations indicate that the analog storage performance should

suffice.

3.2. Analog Input Bandwidth

A relative lack of examples of mixed-signal components optimized for high analog input bandwidth operation is a

concern. Package manufacturers have invested a lot of time studying degrading factors in their chip carriers. For high

frequency but narrow bandwidth operation, choices can be made in the input matching that are not possible when

considering operation over a wide range of input bandwidths. Layout of the CMOS chip has been carefully done to

ensure a 50 impedance controlled stripline internally, with a terminator at the end of the transmission line. A simple

estimate for the analog input frequency roll-off can be made based upon the input impedance and capacitance. In Table

2 is listed an estimate of the sources of capacitance for an RF channel of the STRAW2 chip.

Table 2: Input capacitance estimate for a STRAW2 RF input.

Component Length/area Unit Factor Funit Total [fF]

Input traces 5 cm 0.2 pF/cm 1000 w.a.g.

bonding wire 150 mil 0.3 pF/wire 300 w.a.g.

input pad 60 um^2 187 fF/pad 187 Tanner

input protection 594 1.1 pF/ckt 1100 SPICE

stripline area 2500 um^2 43 aF/um^2 107.5 MOSIS

stripline fringe 5 mm 60 aF/um 300 MOSIS

Switch Drains 256 switches 5.6 fF/drain 1433.6 SPICE

Open Switches 6 open 87 fF/gate 522 SPICE

TOTAL 4.9501 pF

Based upon this and a bonding wire R=5 a f3dB estimate for the input is .4.62

13 GHz

RCf dB





However, this estimate ignores the importance of bonding wire inductance and impedance mismatch. Therefore an

effort has been made to perform a full 3-D Electromagnetic simulation of the input, using LC[24].

3.2.1. 3-D EM Modeling

For convenience, it is preferable to package the STRAW2 die in a 100-pin plastic Thin Quad Flat Pack (TQFP)

package. While it is acknowledged that flip-chip bonding to a Ball Grid Array (BGA) or Chip Scale (CS) package

would have benefits, no suitable standard package has been found. Development of a custom package is an expensive

proposition. Therefore, if the TQFP package can be shown to perform adequately, it will be used. In Figure 12 is

shown the geometry used to simulate an input including printed circuit board trace, package and CMOS die.

LC is a potentially very powerful tool as it applies

a Finite Difference Time Domain (FDTD)

methodology to the challenging task of full 3-D

EM field solving. However, because of

constraints on using simple geometries in LC,

trapezoidal structures have had to be emulated

with a series of rectangular structures. The main

elements modeled in the simulation are the printed

circuit board, with 50 stripline impedance, the

plastic TQFP package, including bonding wires,

and the die, with emulation of the ~2mm long

impedance matched stripline. Analysis of the S-

parameters for the input response is shown in

Figure 13 below. Limitations on the number of

grid points and computation time required

simplifications to the number of simulated input

channels as well as the extent of the printed circuit

board.Figure 12: Geometry used for LC simulation of analog input response.

A preliminary S-parameter simulation

result is shown in Figure 13. These

initial results look promising. At 1 GHz

the VSWR is about 1.8 and rises to

about 1.9 at 2GHz. As a limit on the

number of lattice points was employed

in the simulation, it is possible that

important effects have been neglected.

Therefore more detailed simulations will

continue to be pursued. Taken at face

value, this result indicates little

performance loss up to about 2GHz.

This is well-matched to the fact that the

antennae that are planned to be used for

either ANITA[25] or a possible NaCl

detector[26]array are envisioned to have

modest bandwidth above about 1.5GHz.

STRAW2 Packaging S-Parameters

0

0.2

0.4

0.6

0.8

1

1.2

0 1 2 3

Frequency [GHz]

S11

S21

Figure 13: Preliminary S-parameter results for geometry in Figure 12.





3.3. Triggering on RF Signals

Triggering on pulses with broad bandwidth content up to and including 1GHz is an interesting problem. In addition to

requiring a comparator with a high gain bandwidth product, some account for the bipolar nature of the pulse is required.

In fact, depending upon orientation and line-of-sight to the shower charge separation, the largest amplitude (primary)

received pulse can be predominantly positive or negative. This is somewhat visible in the raw antenna pulse seen in the

top waveform trace in Figure 15. A straightforward way around this problem is to use dedicated positive and negative

amplitude discriminators. As mentioned above, for small signals, a multiplicity requirement is placed upon the RF

channels being monitored to help resolve true signals from noise. In addition, it is desirable to issue a trigger when a

large signal is seen in any one channel, independent of the status of the other channels. This is useful for the case when

the other channels may correspond to antennae that are pointing in a different direction and no signal correlation should

be expected. In Figure 14 is a simplified schematic of a single-channel trigger. The positive and negative comparator

thresholds are set with a DAC for each channel individually. Figure 15 shows a SPICE simulation of trigger

performance for an attenuated version of a waveform recorded in the SLAC beam test indicating functionality.

Figure 14: Simplified schematic of the per-channel trigger logic.

Figure 15: SPICE simulation of response to digitized antenna pulse. At the top the input signal used is a x100 attenuated version of

the raw beamtest digitized high-bandwidth pulse, with a 200ps risetime. In the middle is a x10 buffer amplified signal response. At

the bottom is the subsequent trigger pulse.





4.SUMMARY AND SUBMISSION PLANS Evolution in the trigger parameters as a result of discussion of the triggering requirements has thus far delayed

submission of the design twice. Indeed, it was the strong conviction of the author that having a chip fabricated and test

results in advance of presentation of the design at this conference was essential. However, this simply was not possible.

A preliminary floorplan diagram showing the total chip layout is provided in Figure 16. Pending a design review in

mid-August, the current plan is to submit the STRAW2 design to MOSIS for fabrication at the beginning of September.

Packaged parts for testing should be available approximately 3 months thereafter.

32x256

SCA bank

ADC

Trigger

scalers

DACs

Figure 16: Floorplan diagram of the STRAW2 chip, with various key elements identified.





5.ACKNOWLEDGEMENTSWe wish to acknowledge support from the Department of Energy under Grant # DE-FG 03-94ER40833.

6.REFERENCES1. J. Linsley, Phys. Rev. Lett. 10, 146 (1963).

2. D.J. Bird et al., “Evidence for Correlated Changes in the Spectrum and Composition of Cosmic Rays at Extremely

High Energies,” Phys. Rev. Lett. 71, 3401 (1993); H. Hayashida et al., Ap. J. 522, 225 (1999); C.C.H. Jui et al., 26th

International Cosmic Ray Conference Invited, Rapporteur, and Highlight papers (AIP Conf. Proc 516), 370

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3. K. Greisen, “End to the Cosmic Ray Spectrum?,” Phys. Rev. Lett. 16, 748 (1966); G.T. Zatsepin and V.A.

Kuz’min, JETP Letters 4, 78 (1966).

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Wick, T.W. Kephart, T.J. Weiler astro-ph/0102002; G. Sigl, S. Lee, P. Bjhattacherjee and S. Yoshida, Phys. Rev.

D 59, 4354 (1999) and numerous others.

5. The Auger Collaboration, The Pierre Auger Project Design Report, FERMILAB-PUB 96-024 (1996).

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Eksp. Teor. Fiz. 48, 988 (1965) [Soviet Physics JETP 21, 658 (1965)].

7. P.W. Gorham, D.P. Saltzberg, P. Schoessow, et al., “Radio-frequency measurements of coherent transition and

Cherenkov radiation: Implications for high-energy neutrino detection,” Phys. Rev. E 62, 8590 (2000); D. Saltzberg,

P. Gorham, D. Walz et al., “Observation of the Askaryan Effect: Coherent Microwave Cherenkov Emission from

Charge Asymmetry in High Energy Particle Cascades,” Phys. Rev. Lett. 86, 2802 (2001).

8. J. Alvarez-Muniz, R.A. Vazquez and E. Zas, Phys. Rev. D 62, 063001 (2000).

9. see for example: F. Anghinolfi et al., Nucl. Instr. Meth., A334 (1994); D. Munday et al., Nucl. Instr. Meth. A326

(1993) among others.

10. W.O. Lecroy, “Current-sampling waveform acquisition for digital oscilloscope and detector applications,” 5th

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14. S. Kleinfelder, IEEE Trans. Nucl. Sci., Vol. 37, No. 3, 1230-1236, June 1990.

15. G.M. Haller, “High-speed, high-resolution Analog Waveform Sampling in VLSI Technology”, PhD Dissertation,

Stanford University, 1994; G. Haller and B. Wooley, IEEE Trans. Nucl. Sci., Vol. 41, No. 4, 1203-1207, August

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16. Domino Sampling Chip (DSC): C. Bronnimann, R. Horisberger and R. Schnyder, Nucl. Instrum. Meth., A420:

264-269, 1999; Domino Ring Sampler (DRS): Stefan Ritt, private communication and talk on the PSI

MUEGAMMA experiment given at TRIUMF, May 2002:

http://meg.web.psi.ch/doc/talks/s_ritt/may02_triumf/meg.ppt

17. Analog Devices Datasheet for the AD9410: http://products.analog.com/products/info.asp?product=AD9410

18. National Semiconductor Datasheet for the CLC5957: http://www.national.com/ds/CL/CLC5957.pdf

19. Texas Instruments Datasheet for the TLV5580:

http://focus.ti.com/docs/prod/productfolder.jhtml?genericPartNumber=TLV5580

20. Texas Instruments Datasheet for the ADS5102:

http://focus.ti.com/docs/prod/productfolder.jhtml?genericPartNumber=ADS5102

21. MAXIM Datasheet for the MAX1449: http://dbserv.maxim-ic.com/quick_view2.cfm?qv_pk=2368

22. Stuart Kleinfelder, private communication.

23. G. Claus et al., Nucl. Instr. Meth.., A456: 120-124 (2000).

24. Available for free under Linux: http://lc.cray.com

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26. R. Milincic et al., “Testbed for measurements of coherent radio Cherenkov emission from cosmic ray induced

cascades”, these proceedings [4858-17].





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