Unit 9 Latches and Flip-Flops - National Chiao Tung …moblie123.cm.nctu.edu.tw/101 logical design/Unit 09.pdfLogic Design Unit 9 Latches and Flip-Flops Sau-Hsuan Wu The T flip-flop

Department of Communication Engineering, NCTU 1

Unit 9 Latches and Flip-Flops


9.1 Introduction


Logic Design Unit 9 Latches and Flip-Flops Sau-Hsuan Wu

What is the characteristic of sequential circuits in contrastto combinational circuits? The output of a sequential circuit depends not only on the

present input, but also on the past sequence of inputs In effect, sequential circuits are able to remember the past

history of inputs

Two of the commonly used memory devices in sequentialcircuits are latches and flip-flops

Flip-flops change states in response to a clock input,however latches change states in response to data inputs

Either latches of flip-flops are formed through feedbacks



A unstable feedback

A bi-stable feedback

How do we control stable outputs?


9.2 Set-Reset Latch



Introducing control inputs to a feedback circuit

0101

1010

Pn-1Qn-100

0/10/111

PQRS

Unstable when S and R bothswitch from 1 to 0 simultaneously



The response time of a latch

The duration of the S (or R) input pulse must be longerthan in order for a change in the state of Q to occur



0 1

We use the term present state to mean the state of Q atthe time the inputs are applied, and the term next state tomean the state of Q after the latch or flip-flop has reactedto the inputs

Characteristic EquationQ(t +ε) =S(t) + R(t)’Q(t)



Debouncing circuit with a S-R latch When a mechanical switch is opened or closed, the switch

contacts tend to vibrate or bounce open or closed severaltimes before settling down to their final positions


9.3 Gated D Latch



A gated D latch has two inputs- a data input (D) and agate input (G).

When G = 0, the output Q doesn’t change. When G=1, theQ output follows the D input



The symbol and the truth table for gated D-latch


9.4 Edge-Trigged D Flip-Flop



The output of a D flip-flop (FF) changes only in responseto a clock, not a change in D

A D flip-flop has two inputs, D (data) and Ck (clock) A D-FF is said to be triggered on the rising edge of the

clock if the output can change in response to the 0-to-1transition on the clock input

If the output can change upon the 1-to-0 clock transition,then the D-FF is said to be triggered on the falling edge



The time diagram for a falling-edge-triggered D-FF



A rising-edge-triggered D-FF



In order to function properly, the D input to a edge-triggered FF must be held constant for a period of timebefore and after the active edge of the clock

If D changes at the same time as the active edge, thebehavior is unpredictable

Setup time Hold time

Propagation delay



The minimum clock period


9.5 S-R Flip-Flop



A S-R FF is similar to a S-R latch in that S=1 sets Q to 1,and R=1 set Q to 0. The difference is that the flip-flop hasa clock input



The master-slave S-R FF



There is a subtle difference between the master-slave andthe edge-trigged flip-flop For a rising-edge-triggered flip-flop, the value of the input

is sensed at the rising edge of the clock, and the input canchange while the clock is low

For the master-slave flip-flop, if the input change while theclock is low, the flip-flop output may be incorrect See an example at the previous page The problem can be solved if we only allow the S and R

inputs to change while the clock is high


9.6 J-K Flip-Flop



J-K flip-flop is an extended version of the S-R flip-flop The J-K FF has three inputs, J, K and clock:

J corresponds to S and K corresponds to K

Unlike the S-R FF, a 1 input may be appliedsimultaneously to J and K. Q →Q’when J=K=1



The timing diagram of J-K FF



The master-slave J-K FF Because S= JQ’Clk’and R=KQClk’, only one of S and R

inputs to the first latch can be 1 at any given time Notice that a master-slave FF is different from the edge-

trigged FF


9.7 T Flip-Flop



The T flip-flop is also called the toggle flip-flop When T=1, the flip-flop changes state after the active

edge of the clock. When T=0, no state change occurs



Two common methods to implement a T-FF (a) Conversion of J-K to T (b) Conversion of D to T , D＝T⊕Q


9.8 Flip-Flops with AdditionalInputs



Flip-flop with clear and preset inputs A logic 0 applied to ClrN will reset Q to 0 A logic o applied to PreN will set Q to 1 ClrN and PreN are often referred to as asynchronous clear

and preset inputs



The operation of the clear and preset inputs



When designing a synchronous system, we frequentlyencounter situations where we want some flip-flops tohold existing data even if the data input to the flip-flopsmay be changing. There are two approaches: Gating the clock → may results in loss of synchronization A flip-flop with clock enable → cost extra power

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Unit 9 Latches and Flip-Flops - National Chiao Tung …moblie123.cm.nctu.edu.tw/101 logical design/Unit 09.pdfLogic Design Unit 9 Latches and Flip-Flops Sau-Hsuan Wu The T flip-flop