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Unit 11 Latches and Flip-Flops. Ku-Yaw Chang [email protected] Assistant Professor, Department of Computer Science and Information Engineering Da-Yeh University. Outline. 11.1Introduction 11.2Set-Reset Latch 11.3Gated D Latch 11.4Edge-Triggered D Flip-Flop 11.5S-R Flip-Flop - PowerPoint PPT Presentation
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Unit 11Unit 11Latches and Flip-FlopsLatches and Flip-Flops
Ku-Yaw ChangKu-Yaw [email protected]@mail.dyu.edu.tw
Assistant Professor, Department of Assistant Professor, Department of Computer Science and Information EngineeringComputer Science and Information Engineering
Da-Yeh UniversityDa-Yeh University
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OutlineOutline
11.111.1 IntroductionIntroduction11.211.2 Set-Reset LatchSet-Reset Latch11.311.3 Gated D LatchGated D Latch11.411.4 Edge-Triggered D Flip-FlopEdge-Triggered D Flip-Flop11.511.5 S-R Flip-FlopS-R Flip-Flop11.611.6 J-K Flip-FlopJ-K Flip-Flop11.711.7 T Flip-FlopT Flip-Flop11.811.8 Flip-Flops with Additional InputsFlip-Flops with Additional Inputs11.911.9 SummarySummary
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IntroductionIntroduction
Sequential switching circuitsSequential switching circuits The output depends onThe output depends on
Present inputPresent input
Past sequence of inputsPast sequence of inputs ‘‘remember’ something about the past history of the remember’ something about the past history of the
inputsinputs
Two commonly used memory devices in Two commonly used memory devices in sequential circuitssequential circuits Latches – no clock inputLatches – no clock input Flip-flopsFlip-flops
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FeedbackFeedback
The output of one of the gates is connected The output of one of the gates is connected back into the input of another gate in the circuit back into the input of another gate in the circuit so as to form a closed loop.so as to form a closed loop.
The rate at which the circuit oscillates is The rate at which the circuit oscillates is determined by the propagation delay in the determined by the propagation delay in the inverter.inverter.
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Two Inverters withTwo Inverters witha Feedback Loopa Feedback Loop
Two stable conditionsTwo stable conditions Often referred to as stable statesOften referred to as stable states
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OutlineOutline
11.111.1 IntroductionIntroduction
11.211.2 Set-Reset LatchSet-Reset Latch11.311.3 Gated D LatchGated D Latch11.411.4 Edge-Triggered D Flip-FlopEdge-Triggered D Flip-Flop11.511.5 S-R Flip-FlopS-R Flip-Flop11.611.6 J-K Flip-FlopJ-K Flip-Flop11.711.7 T Flip-FlopT Flip-Flop11.811.8 Flip-Flops with Additional InputsFlip-Flops with Additional Inputs11.911.9 SummarySummary
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Set-Reset LatchSet-Reset Latch
Introduce feedback into a NOR-gate circuitIntroduce feedback into a NOR-gate circuit S=R=0 is a stable conditionS=R=0 is a stable condition S=1 and R=0 is a stable conditionS=1 and R=0 is a stable condition
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Set-Reset LatchSet-Reset Latch
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Set-Reset LatchSet-Reset Latch
This circuit is said to have memory because This circuit is said to have memory because its output depends not only on the its output depends not only on the present present inputsinputs, but also on the , but also on the past sequence of past sequence of inputsinputs..
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Set-Reset LatchSet-Reset Latch
R = S = 1 is not allowedR = S = 1 is not allowed The outputs P and Q are always complements, The outputs P and Q are always complements,
that is, P = Q’.that is, P = Q’. The circuit is in cross-coupled form.The circuit is in cross-coupled form.
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Set-Reset LatchSet-Reset Latch
An input S = 1 An input S = 1 setssets the output to Q = 1 the output to Q = 1
An input R = 1 An input R = 1 resetsresets the output to Q = 0 the output to Q = 0
R and S cannot be 1 simultaneouslyR and S cannot be 1 simultaneously
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Improper S-R Latch OperationImproper S-R Latch Operation
The latch may continue to oscillate if the gate The latch may continue to oscillate if the gate delays are equal.delays are equal.
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Timing DiagramTiming Diagram
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S-R Latch OperationS-R Latch Operation
S(t)S(t) R(t)R(t) Q(t)Q(t) Q(t+Q(t+))
00 00 00 00
00 00 11 11
00 11 00 00
00 11 11 00
11 00 00 11
11 00 11 11
11 11 00 --
11 11 11 --
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Map and Equation of the LatchMap and Equation of the Latch
Next-state equation, or characteristic equationNext-state equation, or characteristic equation QQ++ = S + R’ Q (SR=0) = S + R’ Q (SR=0)
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S-R Latch ApplicationsS-R Latch Applications
Components in more complex latches and flip-Components in more complex latches and flip-flopsflops
Debouncing switchingDebouncing switching
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S-R LatchS-R Latch
An alternative form of the S-R latch uses An alternative form of the S-R latch uses NAND gatesNAND gates
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S-R LatchS-R Latch
S = 0 will set Q to 1S = 0 will set Q to 1
R = 0 will set Q to 0R = 0 will set Q to 0
S = R = 0 is not allowedS = R = 0 is not allowed
SS RR QQ QQ++
11 11 00 00
11 11 11 11
11 00 00 00
11 00 11 00
00 11 00 11
00 11 11 11
00 00 00 --
00 00 11 --