Unifying approach for Jitter Transfer Analysis of Bang-Bang CDR Circuits

Ahmed Gabr Department of Electronics

Carleton University Ottawa, Canada

agabr@doe.carleton.ca

Tad Kwasniewski Department of Electronics

Carleton University Ottawa, Canada

tak@doe.carleton.ca

Abstract—Clock and data recovery (CDR) circuits using bang-bang phase detectors (BBPDs) are widely used in high speed serial links. The BBPD quantizes the phase difference between the input data and the recovered clock, generating a two state output for the loop filter (LF). The two-state output causes the behavior of the BBPD to be highly nonlinear and difficult to analyze. This paper provides a detailed analysis of the jitter transfer for second order bang-bang CDR circuits. Two popular representations of the second order bang-bang CDR circuits are used for our analysis. A detailed derivation of the jitter transfer expression is presented using each representation. Then a modified expression is derived, which is then verified by a phase-domain model implemented in Simulink. Simulation results show good agreement with the derived expression.

Keywords- Bang-Bang, CDR, Clock and Data Recovery, jitter Transfer, Phase Detector.

I. INTRODUCTION CDR circuits are critical components in high speed serial

communication. Recently, bang-bang phase detectors (BBPDs) incorporated in CDR circuits have shown advantages over their linear counterparts. BBPDs have a simpler structure and they can operate at much higher speeds. However, the nonlinear behavior of BBPDs makes the analysis for jitter performance difficult.

Several methods have been proposed for analyzing the

nonlinear behavior of BBPDs [1-4]. Fig. 1 shows one representation for the second order bang-bang CDR circuit presented in [1]. This representation has two paths modelling the loop filter components. Equations were derived in [1] explaining the behavior of the loop by making an analogy with Delta modulation. A second representation, based on RC type analog filter, was used to analyze jitter performance, as shown in Fig. 2. In order to simplify the analysis, a piece-wise linear function was utilized in describing the behavior of the bang-bang CDR circuit. In this paper we will use both representations to analyze the jitter transfer characteristics for the second order bang-bang CDR circuit. Expressions for jitter transfer from [1] and [2] are presented and analyzed. A more accurate expression is derived and verified by simulation.

Figure 1. Bang-bang CDR circuit block diagram with two paths.

Figure 2. Bang-bang CDR circuit block diagram with analog filter.

Figure 3. Jitter transfer curve.

Section II includes a review of jitter transfer characteristics. In section III, we analyze the expression for jitter transfer based on the two CDR representations. Section IV presents the simulation results and in section V we conclude the paper.

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Figure 4. Jitter transfer measurement process where fi denotes the jitter

transfer test sinusoidal frequency

II. JITTER TRANSFER CHARACTERSTICS Jitter transfer is defined as the relationship between the

applied input jitter and the resulting output jitter as a function of frequency. It is a measure of how much jitter is attenuated or amplified from the input to the output of network equipment. If the jitter transfer mask is met, then there is no amplification of jitter by the network equipment as that jitter traverses multiple repeaters.

Fig. 3 shows the jitter transfer of SONET/SDH network

equipment interfaces according to ITU-TG.783/ ANSIT1.105.03 requirements. As an example, in the case of SONET OC-192, the cutoff frequency, fC, is 8 MHz and the dc gain, P, is 0.1dB. In order to meet this requirement, the CDR must not exceed the jitter transfer mask shown in Fig. 3.

To measure jitter transfer, the amplitude of the output

jitter is compared to the amplitude of the input jitter, as shown in Fig. 4 [5]. According to the jitter transfer definition, only the amplitude of the fundamental frequency component of the output jitter is compared to the amplitude of the input jitter. As a result, the fundamental frequency component is extracted from the output jitter by employing a very narrow-band tracking filter [6] in the test measurement process. This process is illustrated in Fig. 4, where the narrow band-pass filter is centered at fi, same frequency as the sinusoidal input test signal.

III. JITTER TRANSFER ANALYSIS A typical second order bang-bang CDR circuit consists of

a binary phase detector, a charge pump (CP), a loop filter (LF) and a voltage controlled oscillator (VCO). The binary phase detector, as the name implies, has only two states. The two states correspond to the sign of the phase difference between the incoming data and the recovered clock. Thus, no information is provided by the binary phase detector regarding the magnitude of the phase error. On the other

hand, a linear PD generates an output that is proportional to the magnitude of the phase difference.

Two equivalent representations of the second order bang-

bang CDR circuits have been used by researchers [1-4]. The first representation, which was first introduced by Walker [1], is shown in Fig. 1. This representation models the LF components as two separate paths. One path is called the proportional path (or BB path) and it models the resistor in the LF, while the other path is called the integral path and it models the capacitor in the LF. Thus the VCO input control voltage, �Vin, is the sum of the BB voltage step, �Vbb, and the integral voltage step, �Vint, and is given by [3]:

���� � ���� � ���,

where

���� � � �

����� � � � ���

�

�� ��

The second representation is shown in Fig. 2 and has a

conventional RC loop filter. Even though this representation is a more straightforward illustration of the physical circuit, the first representation is easier to comprehend making the operation of the loop more understandable. The effect of the capacitor, C, can be neglected at high jitter frequencies. This assumption is valid for large capacitor values.

Jitter transfer is measured by applying a sinusoidal jitter

at the input, �in(t) = Ainsin(�jt), and measuring the output jitter at the same frequency. The input jitter amplitude is specified according to the jitter tolerance mask. At low frequencies the bang-bang loop can track the input jitter, and the gain is close to zero dB. As the jitter frequency increases, the loop cannot track the input and the phase error (�err = �in – �out) increases. The region where the loop tracks is represented by the horizontal line on the jitter transfer curve in Fig. 3. The –20dB/dec slope is where the loop is slewing resulting in large errors. The corner frequency, which differentiates these two regions, is called the –3dB bandwidth (corner frequency) of the jitter transfer, �–3dB.

Sections A and B below examine in detail how the two

representations for the second order bang-bang CDR circuits were employed to find an expression for the corner frequency of the jitter transfer. However, in the analysis of both representations, the jitter transfer definition was disregarded leading to inaccurate results. Consequently, we had to apply the jitter transfer definition to derive a more accurate expression.

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Figure 5. Slewing mechanism in CDR loop: (a) Onset of slewing. (b) Heavy slewing: loop cannot track the input sinusoidal shape.

A. Representation 1 A useful analogy can be made between the bang-bang

CDR circuit and the Delta modulator. The bang-bang CDR circuit can be viewed as a second order Delta modulator in the phase domain. This analogy allows us to explain the bang-bang CDR circuit using existing theory on Delta modulation (DM).

In the DM, two types of distortion exist: quantization

distortion (granular noise) and slope overload distortion. If the DM output is able to track the sinusoidal input signal, there is no error and the quantizer output frequently changes its sign. This tracking behavior can be seen in Fig. 5(a). If, on the other hand, the DM output is unable to follow the sinusoidal input signal shape, errors start to occur and the loop is said to experience slope overload [7], as shown in Fig 5(b).

Slewing, which occurs on the jitter transfer curve, is

the same phenomena as slope overload in DM. This analogy enables us to derive an expression for the slewing condition based on DM theory.

For a sinusoidal input signal with amplitude Ain and

frequency �j, the slope of the input signal is

���� ��� � ���� ��� � !������. (1) As mentioned earlier, the integral path is neglected

reducing the loop to a first order loop. The maximum rate of increase of �out(t) is equal to the proportional path gain. Thus,

�"#�� ��� � $%�&� (2)

where Kv is the VCO gain in rad/V.s. Slope overload is avoided if �’in,max � �’out , and therefore from (1) and (2):

����� ' $%�. (3)

The amplitude-frequency product defines the

condition, so as to avoid slope overload. The loop starts to overload when either the amplitude or the frequency increases. Thus, the maximum input jitter frequency where the loop can track the input jitter can be expressed as:

�( � )*+

,-. . (4)

In this expression, the maximum input jitter frequency is inversely proportional to the jitter amplitude. �W can be thought of as the corner frequency for the CDR circuit as in a linear model. In other words, using this bandwidth will ensure that the CDR circuit never slews.

B. Representation 2 Sinusoidal jitter with a specified amplitude is applied

to the block diagram in Fig. 2, and the frequency is increased until slewing occurs. To analyze the jitter transfer we use Fig. 6 where the CDR loop is slewing. The output jitter is a triangular waveform with amplitude Aout and frequency �j. We can find the output jitter peak-to-peak amplitude by a simple integration of the slope for a duration of Tj/2 (Tj = 2�/�j), that is,

�"#� � )*+�/

0 . (5) Therefore, the jitter transfer function can be represented as

1,234,-. 1 �

5)*+6,-.7/

. (6) This expression shows the dependency of the jitter

transfer on the input jitter amplitude Ain,p. This dependency explains why the loop bandwidth of bang-bang CDR circuits cannot be defined in a strict sense. An approximate value for the maximum frequency of the triangular waveform when Aout = Ain can be found as:

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Figure 6. CDR loop is slewing.

�8 � 5)*+6,-. . (7)

This is the same expression derived in [2]. However, in

order to comply with the definition, the output jitter must be measured at the same frequency as the input jitter. Consequently, in this paper we expand the output waveform into its Fourier series and measure the peak amplitude of the fundamental frequency only. Considering only the fundamental frequency component corresponds to the describing function method used to analyze non linear systems [8]. For a triangle waveform the Fourier expansion is as follows:

9��� � :

;6 �!<=�� > ? !<=@�� �

AB !<=B�� >C�

Thus, the jitter transfer function can be modified to be

�DEFG � 0)*+

5,-. . (8)

Equation (8) gives the -3dB bandwidth of the jitter transfer curve when both input and output jitter amplitudes are measured at the same frequency. In our analysis we use the physical output waveforms from simulation results to derive the jitter transfer expression.

IV. SIMULATION RESULTS In order to validate the jitter transfer analysis, a phase domain model for the second order bang-bang CDR circuit was constructed in Matlab Simulink as shown in Fig. 7. A phase-domain model simulates the phase of the CDR signals. Details of each cycle are averaged and as a result faster simulations are achieved. The model is assumed to operate at 4Gb/s and a sinusoidal jitter signal is fed to the BBPD. The model uses the design parameters outlined in table I. A very narrow band-pass filter is used at the output jitter signal. Jitter transfer was simulated by sweeping the jitter frequency between 1 Mrad/sec and 1 Grad/sec using an

input jitter amplitude of 0.15 UI. At each frequency, the input and resulting jitter amplitudes are recorded. Jitter transfer is then calculated as the ratio between the input and output jitter amplitudes at a given frequency. The bang-bang CDR bandwidth can be estimated from its cutoff frequency. Simulation results are then compared with the theoretical analysis. From (4), (7) and (8) the entire jitter transfer curve can be approximated as a single pole curve:

H� � 7IJKL7IJKL�M�N . (9)

Fig. 8 shows the predicted and simulated jitter transfer curves. Jitter curves show a -20dB/decade slope when the loop is in the slewing region. Equation (8) is the best fit for the simulated jitter transfer curve, as illustrated in Fig. 8. Different input jitter amplitudes were simulated, as shown in Fig. 9. Input jitter amplitudes of 0.15UI, 0.25UI and 0.5UI were simulated and compared with (8).

Figure 7. Phase-domain model of second order bang-bang CDR circuit

TABLE I

Design parameters for CDR circuit [9]

KV (rad/V.s) 1.26 x 109 ICP (A) 40 x 10–6 R (�) 500 C (F) 5 x 10–9

Figure 8. Predicted and simulated jitter transfer.

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Figure 9. Predicted and simulated jitter transfer for different input

amplitudes.

V. CONCLUSION Bang-bang CDR circuits have become increasingly

popular for high-speed serial transceivers. In this paper, we analyzed the jitter transfer characteristics of the second order bang-bang CDR circuits. Two popular bang-bang CDR representations are studied, one is with proportional and integral paths, and the other is with a conventional RC loop filter. The difference in the two representations was addressed and a more accurate expression was derived. Simulation results using a Simulink phase-domain model show the accuracy of our modified expression.

ACKNOWLEDGMENT A. G. gratefully acknowledges S. I. Ahmed for his

useful discussions.

REFERENCES

[1] R. C. Walker, “Designing Bang-bang PLLs for Clock and Data Recovery in Serial data transmission Systems,” in Phase-Locking in High-Performance Systems, B. Razavi, Ed:IEEE Press, 2003, pp. 34-45.

[2] J. Lee, “Analysis and Modeling of Bang-Bang Clock and Data Recovery Circuits,” IEEE Journal of Solid State Circuits, Vol. 39, No 9, pp. 1571-1580, Sep 2004.

[3] M. Ramezani, C. Andre, and T. Salama, “Analysis of a Half-Rate Bang-Bang Phase-Locked-Loop,” IEEE Trans. Circuits and Systems II: Analog and Digital SignalProcessing, Vol. 49, No. 7, pp. 505-509, 2002.

[4] Y. Choi, D-K. Jeong, W. Kim, “Jitter Transfer Analysis of Tracked Oversampling Techniques for Multigigabit Clock and Data Recovery,” IEEE Trans. Circuits and Systems II, Analog and Digital Signal Processing, vol. 50, no. 11, Nov. 2003.

[5] “Understanding Jitter and Wander measurement and standards” second edition. Agilent Technologies. Available: http://www.home.agilent.com

[6] A. Alpert, “Jitter measurements in Telecom Transmission Systems – improving accuracy and repeatability”, White paper, 2008. Available: http://www.jdsu.com

[7] R. Steel, “Delta Modulation systems”, New York/Toronto, Wiley 1975.

[8] A. Gelb, W.E. Vander Velde “Multiple-input describing functions and nonlinear system design”, McGraw-Hill, New York, Wiley 1968.

[9] F. A. Musa and A. Chan Carusone, “Modeling and Design of Multilevel Bang-bang CDRs in the Presence of ISI and Noise”, IEEE Transactions on CAS I, Vol. 54, No. 10, pp. 2137-2147, Nov. 2007.

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