IEEE ELECTRON DEVICE LETTERS, VOL. 31, NO. 5, MAY 2010 461

Understanding and Use of IR Belt Furnace forRapid Thermal Firing of Screen-Printed

Contacts to Si Solar CellsIan B. Cooper, Abasifreke Ebong, John S. Renshaw, Robert Reedy, Mowafak Al-Jassim, and Ajeet Rohatgi

Abstract—We have simulated the rapid thermal firing processusing a high-throughput conveyor belt furnace to study the physicsof solar cell contact formation in mass production. We show thatas sinter dwell time decreases, a lower Ag finger contact resistanceis observed. Scanning electron micrographs reveal a correlationbetween glass thickness at the Ag/Si finger interface and Ag fingercontact resistance. Secondary ion mass spectrometry shows thatglass-frit and Ag emitter penetration are controlled by sinter dwelltime. The observed trends in contact formation lead to lower seriesresistance, higher fill factors, and greater efficiencies with rapidfiring.

Index Terms—Contacts, photovoltaic cell metallization, silicon.

I. INTRODUCTION

THE photovoltaic industry focuses on decreasing the cost ofmaterial processing while increasing device performance.

Si solar cell processing consists of four basic steps: surfacetexturing → dopant diffusion → antireflection (AR) coating→ contact formation. Screen-printed-contact cofiring is criticalto device performance since overfiring causes p-n-junctionshunting while underfiring leads to high contact resistance dueto the nonuniform etching of dielectric and formation of fewerAg crystallites to conduct carriers to the grid.

High-quality metal–Si contacts are achieved, in p-type Si,via heavily doped emitter formation (ND > 1019 cm−3) [1],[2]. Here, an ohmic contact can form where the final devicedisplays linear or quasi-linear I–V characteristics [2]. In thisscenario, carrier transmission across the metal–Si interfacefollows a thermionic/field-emission mechanism where carrierstunnel through the contact barrier [1]. Series-resistance powerlosses in solar cells arise when carriers travel through theemitter, across the metal–Si interface, through grid and busbars, and through bulk Si [3]. Series resistance is minimizedthrough emitter and metal–Si contact optimization. Since frontand rear contacts are formed together, process and furnacedesigns are crucial to produce low-resistance ohmic contacts.

Manuscript received February 17, 2010. Date of publication April 5, 2010;date of current version April 23, 2010. The review of this letter was arrangedby Editor C. Jagadish.

I. B. Cooper, A. Ebong, J. S. Renshaw, and A. Rohatgi are with the School ofElectrical and Computer Engineering, Georgia Institute of Technology, Atlanta,GA 30332 USA (e-mail: ian.cooper@gatech.edu).

R. Reedy and M. Al-Jassim are with the National Renewable EnergyLaboratory, Golden, CO 80401 USA.

Color versions of one or more of the figures in this letter are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/LED.2010.2044363

The contact-formation step confers the following: 1) ohmiccontact of Ag grid; 2) uniform Al back surface field (Al-BSF);and 3) bulk defect hydrogenation (in defective materials). Inprevious studies of screen-printed-contact formation throughrapid thermal processing (RTP), a fast ramp-up rate to sinteringtemperature was the key to the formation of a high-qualityAl-BSF [4]. High fill factors (FFs) were achieved via the RTPcofiring of contacts in which short sinter dwell times were used[5]. The advantage of RTP contact firing lies in accelerated tem-perature ramp-up and cool-down rates. However, most resultshave been observed using RTP systems capable of single waferprocessing. For industrial-scale production, device quality andhigh throughput must be achieved simultaneously. High-speedbelt furnaces have become staples of solar cell manufactur-ing. To combine the quality of RTP with the throughput ofa conveyor-belt system, one must understand the physics ofcontact formation as it relates to high-throughput processing.

II. MATERIALS AND FABRICATION

Solar cells fabricated on 156-mm2 2-Ω · cm 200-μm-thickp-type Cz–Si wafers were textured by random pyramid forma-tion. Emitters were formed by POCl3 diffusion. Wafers werecoated with SiNX AR coating via PECVD. A front collectiongrid was created using screen-printed glass-fritted Ag paste.Al paste was printed on the back with Ag/Al tabbing stripes.Finally, a contact was formed by firing wafers in an IR beltfurnace from Thermal Processing Solutions (Mountain View,CA). Firing conditions were calibrated for a sintering peak of750 ◦C ± 5◦C. A dependence on Ag particle size has beenobserved during firing [6]; thus, the same Ag paste was usedfor all conditions.

III. RESULTS AND DISCUSSION

Conveyor-belt contact firing consists of the following fourtemperature regions:

Region 1) initial temperature ramp-up, where paste solventsare volatilized;

Region 2) paste binding agent burnout;Region 3) sintering, where the glass frit melts to assist in

Ag contact formation at temperatures below theAg–Si eutectic point [7];

Region 4) wafer cool down.Front-contact formation depends most on the conditions of

region 3). Here, at temperatures above 700 ◦C, melting the glass

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462 IEEE ELECTRON DEVICE LETTERS, VOL. 31, NO. 5, MAY 2010

TABLE ISINTER DWELL TIMES, RAMP RATES, AND SOLAR CELL LIGHT I–V PARAMETERS AT 1 SUN FOR EACH FIRING CONDITION

Fig. 1. (Red triangle) Interfacial glass-layer thickness and (black circles) Agfinger specific contact resistance as a function of sinter dwell time. Error barsrepresent one standard deviation.

frit causes Ag and Si to melt [6]. Short times at high temperaturehave benefited high-quality ohmic contacts due to the formationof small evenly dispersed Ag crystallites and thinner glasslayers [5]. To gain a deeper understanding of contact formation,we have varied the sinter dwell time during solar cell firing.Due to furnace design, the sinter ramp rate was also changed.As mentioned, high sinter ramp rates lead to the formationof a more uniform Al-BSF [4]. Although scanning electronmicrograph (SEM) measurements revealed thicker BSFs at highramp rates (data not shown), open circuit voltage (VOC) was notaffected. Table I gives the range of sinter dwell times and ramprates used. Sinter dwell time is the time a wafer spends above700 ◦C. Sinter ramp rate is the slope of temperature increasebetween 500 ◦C and 750 ◦C. Table I also shows solar cell lightI–V parameters as measured at 1 sun.

To understand the effects of dwell time on contact formation,the factors contributing to series resistance were scrutinized.Following the method of [8], series-resistance componentswere measured for all firing conditions. The series-resistancevalues derived were similar to the values estimated by lightI–V measurements. Only the gridline and contact resistanceswere significantly affected by changes in sintering. Gridlineresistance changed by less than 10% (data not shown). How-ever, specific contact resistance showed greater than 50% im-provement as dwell time decreased. Fig. 1 shows the effect ofdwell time on Ag finger specific contact resistance (red curve).Further insight into the origin of improved specific contactresistance was gained from measurements of glass-layer thick-

Fig. 2. SEM of wafer cross sections for interfacial glass-layer thicknessmeasurements for firing conditions (A) 1 and (B) 5.

ness at the Ag/Si interface. Improved contact resistance canarise from thinner interfacial glass layers between the Ag fingerand bulk Si [5]. Indeed, the overfiring of Ag contacts leads toelongated Ag crystallites and extensive PbO glass coverage [9].Fig. 1 also shows the effect of dwell time on interfacial glass-layer thickness (black curve). Fig. 1 confirms that increasingsinter dwell time causes a thicker interfacial glass layer beneathAg fingers. A thicker glass layer leads to higher Ag fingerspecific contact resistance. Furthermore, the trends observed inmeasurement standard deviation show that glass-layer thicknessand specific contact resistance are more tightly controlled atshorter dwell times.

Fig. 2 shows the SEMs of the interfacial glass layer forfiring conditions 1 (A) and 5 (B). The glass layer was exposedfor thickness measurements by removing Ag fingers in HNO3

without damaging the underlying glass layer [5]. The glass-layer thickness was measured only at texture pyramid verticeswith the assumption that glass-layer formation physics are com-parable in these areas and allow differences in firing conditionsto be observed.

To differentiate the interfacial glass layer from bulk Si orpossible debris, energy dispersive X-ray spectroscopy (EDS)was employed. EDS allows elemental analysis via detection ofcharacteristic X-ray emission. EDS was performed at texturepyramid vertices to simulate the measurement areas of Fig. 2.Fig. 3 shows the EDS spectra taken from suspected interfacialglass (1) and bulk Si (2) (see SEM inset). Probing area 1 (redcurve) revealed emission peaks from N, O, Si, Pb, and Ag onthe order of emission energy [10]. Common Ag pastes containPbO-based glass frits [5], [6]. Probing area 2 (black curve)revealed only one emission peak from Si. These data verify thatinterfacial glass layers grow at texturing pyramid vertices andthat glass-layer thickness measurements are valid.

Secondary ion mass spectrometry (SIMS) performed onHNO3-treated Ag fingers showed decreasing O and Ag emitterpenetrations with decreasing sinter dwell time. Fig. 4 shows

COOPER et al.: UNDERSTANDING AND USE OF IR BELT FURNACE 463

Fig. 3. EDS spectra of (1, red curve) suspected interfacial glass and (2, blackcurve) bulk Si for a solar cell processed at the lowest sinter dwell time. Spectrawere acquired at 15-keV accelerating voltage. (Inset) SEM of areas probedfor EDS.

Fig. 4. Log plot of SIMS profiles for (green curves) O and (red curves) Agindicating decreasing glass-frit (O) and Ag penetrations with decreasing sinterdwell time. The dashed line shows average P concentration and indicates p-n-junction depth. SIMS curves darken in color as sinter dwell time increases.Arrows show the trend of O and Ag concentrations and depth as sinterdwell time decreases. (Inset) Diagram of SIMS measurements (gray feature =HNO3-treated Ag finger).

the O and Ag surface concentrations for each firing condition.The arrows in Fig. 4 show the trend of O and Ag concentrationand depth as sinter dwell time is decreased. The black dashedcurve indicates average P concentration and p-n-junction depth.The high O concentrations detected by SIMS arise from Si andPb oxides in the interfacial glass layer. In light of the trendobserved in specific contact resistance and interfacial glass-layer thickness, SIMS data suggest that the depth of emitterpenetration by Ag and the glass frit dictates contact quality.High sinter dwell times cause a deeper emitter penetration by

Ag and the glass frit that may create shunt paths and inefficientcarrier tunneling.

IV. CONCLUSION

We have shown that contact quality in 156-mm2 Si solarcells can be controlled via a high-throughput RTP-type IR beltfurnace. Ag specific contact resistance and Ag/Si interfacialglass-layer thickness decrease as sinter dwell time decreases. Athinner glass layer allows a more efficient tunneling of carriersand lower series resistance. SIMS data suggest that a lessaggressive emitter penetration by the glass frit and Ag enablesefficient carrier tunneling. Solar cells produced in this studysaw better FFs and RSERIES’s as sinter dwell time decreased.The combination of contact quality and high throughput can en-hance the megawatt output and profit margin of manufacturersemploying this advancement. Future work includes extensionto multicrystalline devices and model development.

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