UMC_180nm_mm_rf_FDK_CDN_userguide_vB04_PB_3

UM180FDKMFC000000A_B

UMC Confidential

Ver. B04_PB 1

Copyright UMC, 2005 All information contained herein is subject to change without prior notice. No liability shall be incurred from its use or application.

UMC 0.18um 1P6M

Mixed-Mode/RF

Thick Top Metal (20KA) Process

Foundry Design Kit (PDK) User Guide


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Ver. B04_PB 2

Contents 0. Release Notes ..…………………………………………………….. 4 1. Overview ………………………………...………..………..…….. 7 2. Foundry Data ………….………………...………..…..………….. 8 3. What makes up a PDK? ..………………...………..…..…………. 9 4. Installation of the PDK ..………………...………..…..………….. 10 5. PDK Install Directory Structure/Contents ..………..………….. 11

6. Creation of a Design Project ............……...……………..………... 12 7. Techfile Methodology ..……......………...……………..………... 14 8. Customizing Layer Display Properties Using Display.drf File .. 15 9. Schematic Design …….……………………………………………. 17 10. Library Device Setup ……………………………………………… 18 11. Supported Devices ………………………………………………… 20 12. Views provided …………………………………………………….. 23 13. CDF parameters …………………………………………………… 24 14. Component Label Defaults ………………………………………. 37 15. Simulation Models ………………………………………………… 40 16. AddWire Utility ……………………………………………………… 41 17. UpdateCDFs Utility …………………………………………………. 42 18. Setting Environment Variables ………………………………….. 43 19. Techfile Layers ……………………………………………………… 45 20. Virtuoso XL ………………………………………………………….. 46 21. Dracula Support ……………………………………………………… 48 22. Assura Decks ………………………………………………………. 49 23. DEVICE SPECIFICATIONS ………………………………………… 59


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Ver. B04_PB 3

24. DEVICE DATASHEETS ……………………………………………… 72 25. Known Problems and Solutions …………………………………. 253

Appendix A.1 Revision History ………………………………………………….. 258

A.2. UMC Utilities …………………………………………………………… 258

A.2.1. Callback Re-trigger Utility ………………………………………………………………….…… 258

A.2.2. Alphabet Generator ……………………………………………………….... 259


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Ver. B04_PB 4

0 Release Notes

0.1 Foundry Process Documents The following documents were used to develop or verify this Design Kit.

Classification Spec. No. Version Date Design Support Manual G-01-MIXED_MODE/RFCMOS18-1.8V/3.3V-1P6M-MMC-DSM-8C 2.0_P2 8/25/2005 Electrical Design Rule G-02-MIXED_MODE/RFCMOS18-1.8V/3.3V-1P6M-MMC-EDR 1.4_P1 11/29/2005

Topological Layout Rule G-03-MIXED_MODE/RFCMOS18-1.8V/3.3V-1P6M-MMC-TLR 2.8_P1 11/16/2005

Interconnect Capacitance G-04-MIXED_MODE/RFCMOS18-1P6M-MMC-INTERCAP 1.1_P2 5/9/2003

SPICE Modeling G-05-MIXED_MODE/RFCMOS18-1.8V/3.3V-TRI_WELL/MMC-SPICE-8C 1.4_P1 11/4/2005

G-05-MIXED_MODE/RFCMOS18-1.8V/3.3V-TWIN_WELL/MMC-SPICE-8C 1.5_P1 11/4/2005

GT-DBT-030922-007 (MM salicide resistors and metal resistors) B.B1PB 9/22/2003

Mask Tooling G-06-MIXED_MODE/RFCMOS18-1.8V/3.3V-1P6M-MMC-MASKTOOL-8C

2.4_P1 11/2/2005

DRC Rule Deck G-DF-MIXED_MODE/RFCMOS18-1.8V/3.3V-1P6M-MMC/CALIBRE-DRC 2.8_P1 11/23/2005

LVS Rule Deck G-DF-MIXED_MODE/RFCMOS18-1.8V/3.3V-1P6M-MMC/CALIBRE-LVS 1.3_P3 10/24/2005

LPE Rule Deck G-DF-MIXED_MODE/RFCMOS18-1.8V/3.3V-1P6M-MMC/XRC-LPE 1.1_P13 7/14/2005

Official Layer Mapping Table G-DF-GENERATION18-VIRTUOSO-TF 2.3_P1 11/4/2005

NOTE: The model files and rule decks included in this release Design Kit were available at the time of this revision. The user should keep accessing the latest model files and rule decks. Please contact your Account Manager if you failed to access them.

0.2 EDA Tools Supported and Verified for Use with this FDK (PDK)

Classification EDA Tools Version

Schematic Entry Cadence Composer 5.10.41_USR1.7.43Simulation Interface Cadence Analog Design Environment 5.10.41_USR1.7.43

Cadence Spectre 5.10.41_USR1.7.43 Simulation Tool Synopsys Hspice 2003.09 Layout Editor Cadence Virtuoso 5.10.41_USR1.7.43DRC Tool Mentor Calibre 2005.1_10.20 LVS Tool Mentor Calibre 2005.1_10.20 Parasitic RC Extractor Mentor XRC 2005.1_10.20

NOTE: This Design Kit did not verify the other EDA tools not mentioned above.


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Ver. B04_PB 5

0.3 Component List

Dev

ice

Typ

e

Dev

ice

Nam

e

Term

inal

s

Sym

bol V

iew

Mod

el T

ype

Spec

tre

Net

list

Hsp

ice

Net

list

CD

L N

etlis

t

Layo

ut V

iew

SDL

Che

ck

Spec

tre

Sim

.

Hsp

ice

Sim

.

DR

C C

heck

LVS

Che

ck

MOS P_18_MM 4 V C* V V V V V V V V V N_18_MM 4 V C* V V V V V V V V V N_BPW_18_MM 4 V C* V V V V V V V V V P_33_MM 4 V C* V V V V V V V V V N_33_MM 4 V C* V V V V V V V V V N_BPW_33_MM 4 V C* V V V V V V V V V P_LV_18_MM 4 V C* V V V V V V V V V N_LV_18_MM 4 V C* V V V V V V V V V N_ZERO_18_MM 4 V C* V V V V V V V V V P_LV_33_MM 4 V C* V V V V V V V V V N_LV_33_MM 4 V C* V V V V V V V V V N_ZERO_33_MM 4 V C* V V V V V V V V V P_L18W500_18_RF 4 V S* V V V V V V V V V P_PO7W500_18_RF 4 V S* V V V V V V V V V N_L18W500_18_RF 4 V S* V V V V V V V V V N_PO7W500_18_RF 4 V S* V V V V V V V V V P_L34W500_33_RF 4 V S* V V V V V V V V V P_PO7W500_33_RF 4 V S* V V V V V V V V V N_L34W500_33_RF 4 V S* V V V V V V V V V N_PO7W500_33_RF 4 V S* V V V V V V V V V

BJT PNP_V50X50_MM 3 V C* V V V V V V V V V PNP_V100X100_MM 3 V C* V V V V V V V V V

Diode DION_MM 2 V C* V V V V V V V V V DIONW_MM 2 V C* V V V V V V V V V DIOP_MM 2 V C* V V V V V V V V V

RES RSND_MM 3 V S* V V V V V V V V V RSPD_MM 3 V S* V V V V V V V V V RNND_MM 3 V S* V V V V V V V V V RNPD_MM 3 V S* V V V V V V V V V RNNPO_MM 3 V S* V V V V V V V V V RNPPO_MM 3 V S* V V V V V V V V V RNHR1000_MM 3 V S* V V V V V V V V V RSNWELL_MM 3 V S* V V V V V V V V V RM1_MM 2 V S* V V V V V V V V V RM2_MM 2 V S* V V V V V V V V V RM3_MM 2 V S* V V V V V V V V V RM4_MM 2 V S* V V V V V V V V V RM5_MM 2 V S* V V V V V V V V V RM6_MM 2 V S* V V V V V V V V V RNNPO_RF 3 V S* V V V V V V V V V


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Ver. B04_PB 6

RNPPO_RF 3 V S* V V V V V V V V V RNHR_RF 3 V S* V V V V V V V V V

CAP NCAP_MM 3 V C* V V V V V V V V V PCAP_MM 3 V C* V V V V V V V V V MIMCAPS_MM 2 V S* V V V V V V V V V MIMCAPM_RF 3 V S* V V V V V V V V V

IND L_SLCR20K_RF 3 V S* V V V V V V V V VVAR VARMIS_18_RF 3 V S* V V V V V V V V V

VARDIOP_RF 2 V S* V V V V V V V V VPAD PAD_RF 2 V S* V V V V V V V V V* C means compact model, and S means sub-circuit model.

0.4 Verification Notes

Calibre LVS:

(1) Please let LVS setup options of “LVS REDUCE PARALLEL CAPACITORS” and

“LVS REDUCE SERIES CAPACITORS” be NO when you run Calibre LVS rule eck

on RF Capacitors (MIMCAPM_RF, VARDIOP_RF & VARMIS_18_RF). RF

capacitors defined in Calibre LVS rule deck trace geometrical parameters (L, W, NX,

NY, NF) instead of the capacitance.


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Ver. B04_PB 7

1 Overview

The purpose of this User Guide is to describe the technical details of the UMC .18 MM/RF, 1P6M thick top metal (20KA) Process Design Kit (“PDK”) provided by Cadence Design Systems, Inc. (“Cadence”). NOTE: The RM6_MM resistor uses thick metal (20KA) values. This PDK requires the following environmental variables “CDS_Netlisting_Mode” to be set to “Analog” “CDS_INST_DIR” to be set to the Cadence DFII installation path Cadence DFII Tool Training is not provided as part of this PDK.

1.1 Software Releases The following releases of software were used to develop and test this PDK:

Cadence DFII Version: 5.0.33_USR3.16.35 (USR3) Cadence Assura DRC/LVS Versions: 3.1.3.USR1 Cadence Assura RCX Version: 3.1.3.USR1


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Ver. B04_PB 8

2 Foundry Data G-03-MIXED_MODE/RFCMOS18-1.8V/3.3V-1P6M-MMC-TLR

0.18 um Mixed Mode/RFCMOS Technology 1.8V/3.3V 1P6M Process Topological Layout Rule (With Metal/Metal Capacitor Module) (Rev. 2.8_P1)

G-02-MIXED_MODE/RFCMOS18-1.8V/3.3V-1P6M-MMC-EDR

0.18um Mixed Mode/RFCMOS Technology 1.8V/3.3V 1P6M Electrical Design Rule (With Metal/Metal Capacitor Module) (Ver. 1.4_P1)

G-04-MIXED_MODE/RFCMOS18-1P6M-MMC-INTERCAP

0.18um 1P6M Mixed Mode with MMC Process Interconnect Capacitance Model (Ver. 1.1_P2)


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Ver. B04_PB 9

3 What makes up a PDK?

PDK stands for Process Design Kit. A PDK contains the process technology and needed information to do device-level design in the Cadence DFII environment.

VirtuosoXLLayout

AnalogFront-endDesign

Device Generation/Cell Design

Virtuoso XL (Advanced Layout Editor)

Interconnect Wire Editor/RoutingVirtuoso Custom Router (VCR)

Interactive Physical VerificationDiva, Dracula, Assura

Simulation Spectre

Analog Design Environment

Schematic (Composer)

PDK Cadence Tool

Foundry

Physical Verification

- DRC- LVS- LPE

Techfile:- Layer maps- Layer props- symbolics- Connectivity- VCR setup

FixedLayouts

ParameterizedCells

Spectre Models

AnalogSimulation& callbacks

SchematicSymbols

& CDF

VirtuosoXLLayoutVirtuosoXLLayout







Simulation Spectre











Simulation Spectre


Simulation Spectre

Simulation Spectre



PDK Cadence ToolPDK Cadence Tool

Foundry


- DRC- LVS- LPE


FixedLayouts

ParameterizedCells

Spectre Models


SchematicSymbols

& CDF

Foundry


- DRC- LVS- LPE


FixedLayouts

ParameterizedCells

Spectre Models


SchematicSymbols

& CDF


- DRC- LVS- LPE


- DRC- LVS- LPE



FixedLayouts

ParameterizedCells

FixedLayouts

ParameterizedCells

Spectre ModelsSpectre Models



SchematicSymbols

& CDF

SchematicSymbols

& CDF


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Ver. B04_PB 10

4 Installation of the PDK

Logon to the computer as the user who will own and maintain the PDK. Choose a disk and directory under which the PDK will be installed. This disk should be exported to all client machines and must be mounted consistently across all client machines. Connect to the directory where the PDK will be installed: cd <pdk_install_directory> Extract the PDK from the archive using the following commands: gzip -d <path_to_pdk_tar_file>/ xxx.tar.gz tar xvf xxx.tar The default permissions on the PDK have already been set to allow only the owner to have write, read and execute access. Other users will have only read and execute access.


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Ver. B04_PB 11

5 PDK Install Directory Structure/Contents

REVISION - ASCII file containing the PDK revision history. cds.lib - file containing the Cadence initialization file. display.drf - ASCII version of display resources file icc.rules - Virtuoso Custom Router and Virtuoso Custom Placer rules file Models – directory containing SPICE model files used to test the PDK umc18mmrf.tf - ASCII version of technology file umc18mmrf – UMC .18 MM/RF Process PDK Cadence Library RuleDecks – directory containing Calibre rule decks used to test the PDK celview.cellmap – cell map file for Calibre view


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Ver. B04_PB 12

6 Creation of a Design Project A unique directory should be created for each circuit design project. The following command can be executed in UNIX:

mkdir ~/circuit_design

cd ~/circuit_design

All work by the user should be performed in this circuit design directory. The following file should be copied from the PDK install directory to begin the circuit design process. The following command can be used:

cp <pdk_install_directory>/display.drf .

Next the user should create a "cds.lib" file. Using any text editor the following entry should be put in the cds.lib file:

INCLUDE <pdk_install_directory>/cds.lib

Where "pdk_install_directory" is the path to where the UMC .18 MM/RF PDK was installed.

Because the UMC .18 MM and UMC .18 MM/RF PDK, differ in their top metal thicknesses, you can not use the same techfile for both PDKs. The UMC .18 MM PDK uses thin top metal, and the UMC .18 MM/RF PDK uses thick top metal. The symbolic contacts for M6_M5 and the path width for ME6 differ between these two PDKs. Both of these settings are defined in the techfile. This will require a techfile for each PDK. Given that two techfile are required, what follows is a step by step flow that can be executed to switch between PDK's. For example, If you would like to reuse an existing test library (developed for UMC .18 MM) for your UMC .18 MM/RF tests, please do the following: ***NOTE: Assuming that the test library that you want to change is named "umc18mm_test" 1) Rename the reference library: In the library manager select Edit->Rename Reference Library... Make sure that the following fields are entered:


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Ver. B04_PB 13

In Library umc18mm_test From Library umc18mm To Library umc18mmrf Then click on the "OK" button. 2)Attach the UMC .18 MM/RF technology file: In the CIW window, select Technology File->Attach To... Make sure that the "Design Library" field is set to "umc18mm_test". Make sure that the "Technology Library" is set to "umc18mmrf" Then click on the "OK" button. 3) Update CDFs: In the CIW window, enter the following command: umc18mmrf_updateCDFs("umc18mm_test") Once all 3 of these steps have been executed, you will then be able to reuse existing designs in the "umc18mm_test" library that was developed in "umc18mm" on the "umc18mmrf" PDK.


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Ver. B04_PB 14

7 Techfile Methodology

The umc18mmrf Library techfile will be designated as the master techfile. This techfile will contain all required techfile information. There is an ASCII version of this techfile shipped with the PDK. This ASCII version represents the techfile currently compiled into the umc18mmrf library

The attach method should be used for any design library that is created. This allows the design database techfile to be kept in sync with the techfile in the process PDK. To create a new library that uses an attached techfile, use the command File->New->Library from either the CIW or library manager and select the Attach to an existing techfile option. Select the umc18mmrf library when asked for the name of the Attach To Technology Library.


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Ver. B04_PB 15

8 Customizing Layer Display Properties Using Display.drf File

The display.drf can be autoloaded at Cadence start-up time or manually loaded during the Cadence session. For the file to be autoloaded, the display.drf file must be located in the Cadence start-up directory. To manually load the display.drf file (or load a new version), choose Tools->Display Resources->Merge Files... from the CIW and enter the location of the display.drf file that you want to use. If the display.drf file is not autoloaded and you do not manually load it, you will get error messages about missing packets when you try to open a schematic or layout view and you will not be able to see any process specific layers.

The UMC .18 MM/RF 1P6M process display.drf file can be found in the PDK install directory.

Listed below are the packet, color, lineStyle, and stipplePattern definitions for a ME3 drawing layer. The packet info references predefined color, lineStyle, and stipplePattern definitions. Any of these can be changed to suit an individual user’s preferences in the project copy of the display.drf file.

drDefinePacket(

;( DisplayName PacketName Stipple LineStyle Fill Outline )

( display m3 dots solid green green )

)

drDefineColor(

;( DisplayName ColorName Red Green Blue Blink )

( display green 0 204 102 nil )

)

drDefineLineStyle(

;( DisplayName LineStyle Size Pattern )

( display solid 1 (1 1 1) )

)

drDefineStipple(


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Ver. B04_PB 16

;( DisplayName StippleName Bitmap )

( display dots (

(0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0)

(0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)

(0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1)

(0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)

(0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0)

(0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)

(0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1)

(0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)

(0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0)

(0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)

(0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1)

(0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)

(0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0)

(0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)

(0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1)

(0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)


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Ver. B04_PB 17

9 Schematic Design

The user should follow the guidelines listed below while building schematics using Composer:

Project libraries should list the primitive PDK library as a reference library in the library properties form.

Users can add instances from the PDK library to designs stored in the project libraries.

When performing hierarchical copy of schematic designs care should be taken to preserve the references to the PDK libraries. These references should not be copied locally to the project directories and the references set to the local copy of PDK cells. This would prevent your designs from inheriting any fixes done to the PDK library from an upgrade.

Users should exercise caution when querying an instance and changing the name of the cell and replacing it with a reference to another cell. While like parameters will inherit values, callbacks are not necessarily executed. This would cause dependent parameters to have incorrect values.

Schematics should be designed with schematic driven layout methodology in mind. Partitioning of schematics, hierarchical design, input and output ports, should be done in a clean and consistent fashion.

Usage of pPar and iPar in a schematic design context is discouraged. While this works fine in schematic design, this could lead to problems while performing schematic driven layout.


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Ver. B04_PB 18

10 Library Device Setup 10.1 Resistors

The resistors in the library consist of two types; diffused and insulated. The diffused types include n+ and are 3 terminal resistors with diode backplates. The insulated resistors are those that are isolated from silicon by an insulator (oxide) such as poly resistors. The resistors in this PDK are 3 terminal devices. Serpentine resistor layouts are not allowed. Dog-bone configurations are allowed.

Units: The width is specified in meters for schematic simulation. All parameters entered into the resistor form must be integers or floating-point numbers. No design variables are supported due to the calculations that must be performed on the entries.

Calculation: The width and length are snapped to grid, and the resistances are recalculated and updated on the component form based on actual dimensions.

Simulation:

The UMC provided model definitions are used to model the resistors.

10.2 Capacitors All capacitors in the PDK library are 2 and 3 terminals. The capacitors for this process are MIMCAPS_MM, MIMCAPM_RF, NCAP_MM and PCAP_MM. MIMCAPS_MM and MIMCAPM_RF are metal on metal capacitors and they have 2 and 3 terminals respectively. The NCAP_MM and PCAP_MM are MOSFET capacitors and they have 4 terminals.

Units: The length and width are specified in meters for schematic simulation. All parameters entered into the capacitor form must be integers or floating-point numbers. Design variables are supported here.

Calculation:

The width and length are snapped to grid, and the capacitance is recalculated and updated on the component form based on actual dimensions.

Simulation:

The UMC provided model definitions are used to model the capacitors.

10.3 MOSFETS All mosfets in the PDK library are 4 terminal, with the body terminal explicitly connected. To conform to electromigration rules, customer must choose proper finger width, finger number, or source/drain metal width according to device operating point.


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Ver. B04_PB 19

Units: Length and width are in meters, with areas and perimeters in meters squared and meters, respectively. Design variables are allowed for Length and Width entries.

Calculation:

The area and perimeter parameters for the sources and drains are calculated from the width and the number of fingers used. This calculation assumes that the drain will always have the lesser capacitance (area) when there is an even number of fingers (odd number of diffusion areas). The Width per finger is calculated by dividing the width by the number of fingers. This parameter is for viewing by the designer.

Simulation:

The UMC provided model definitions are used to model the MOSFET devices.

10.4 Bipolar Transistors This PDK contains 2 vertical PNP transistors that have a substrate collector. The device has fixed dimensions for its emitter size.

Units: The emitter size is specified in meters for schematic entry. All parameters entered into the PNP_V50X50_MM and PNP_V100X100_MM forms must be integers or floating-point numbers.

Simulation:

The UMC provided model definitions are used to model the bipolar transistors.


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Ver. B04_PB 20

11 Supported Devices 11.1 MOSFETS

• N_18_MM – 1.8 volt NMOS transistor

• P_18_MM – 1.8 volt PMOS transistor

• N_33_MM – 3.3 volt NMOS transistor

• P_33_MM – 3.3 volt PMOS transistor

• N_LV_18_MM – 1.8 volt low vt NMOS transistor

• P_LV_18_MM – 1.8 volt low vt PMOS transistor

• N_LV_33_MM – 3.3 volt low vt NMOS transistor

• P_LV_33_MM – 3.3 volt low vt PMOS transistor

• N_ZERO_18_MM – 1.8 volt zero vt NMOS transistor

• N_ZERO_33_MM – 3.3 volt zero vt NMOS transistor

• N_BPW_18_MM – 1.8 volt triple-well NMOS transistor

• N_BPW_33_MM – 3.3 volt triple-well NMOS transistor

• N_L18W500_18_RF - 1.8 volt variable finger RF NMOS transistor

• N_L34W500_33_RF - 3.3 volt variable finger RF NMOS transistor

• N_PO7W500_18_RF - 1.8 volt variable length RF NMOS transistor

• N_PO7W500_33_RF - 3.3 volt variable length RF NMOS transistor

• P_L18W500_18_RF - 1.8 volt variable finger RF PMOS transistor

• P_L34W500_33_RF - 3.3 volt variable finger RF PMOS transistor

• P_PO7W500_18_RF -1.8 volt variable length RF PMOS transistor

• P_PO7W500_33_RF - 3.3 volt variable length RF PMOS transistor

11.2 RESISTORS • RSPD_MM – P+ diffused resistor w/salicide

• RSND_MM – N+ diffused resistor w/ salicide

• RNPPO_MM – P+ poly resistor w/o salicide

• RNNPO_MM – N+ poly resistor w/o salicide

• RSNWELL_MM – N-Well resistor

• RNHR1000_MM – High Resistive poly resistor

• RNND_MM – N+ diffused resistor w/o salicide

• RNPD_MM – P+ diffused resistor w/o salicide


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Ver. B04_PB 21

• RM1_MM – Metal 1 resistor






• RNHR_RF - RF High resistive poly resistor

• RNNPO_RF - RF N+ poly resistor w/o salicide

• RNPPO_RF - RF P+ poly resistor w/o salicide

11.3 CAPACITORS • MIMCAPS_MM – Single-squared mixed-mode metal-to-metal capacitor

- CapA = 0.001F/M^2 CapP = 7.5e-11F/M

• NCAP_MM - NMOS transistor configured as a capacitor

• PCAP_MM - PMOS transistor configured as a capacitor

• MIMCAPM_RF – RF Metal Capacitor

11.4 BIPOLARS • PNP_V50X50_MM - 5x5 CMOS vertical substrate PNP

• PNP_V100X100_MM - 10x10 CMOS vertical substrate PNP

11.5 DIODES • DION_MM – N+/psub diode

• DIONW_MM – Nwell/psub diode

• DIOP_MM – P+/nwell diode

11.6 Inductors • L_SLCR20K_RF– Circular spiral RF inductor

11.7 Bond Pads • PAD_RF – RF Bond Pad

11.8 Varactors • VARDIOP_RF - P+/Nwell RF diode varactor

• VARMIS_18_RF - 1.8V N+/Nwell RF MIS varactor


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11.9 PARASITICS NOTE: These symbols are used for internal use only. They are placed in the

extracted view of a layout to display parasitic values. They are not devices that designers should use in their designs.

• pcapacitor

• presistor


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Ver. B04_PB 23

12 Views provided 12.1 MOSFETS

• Four terminals (D, G, S, B)

• symbol, spectre, auLvs, auCdl, ivpcell, hspiceS, layout (Pcells)

12.2 RESISTORS • Two terminals (PLUS, MINUS) for RM1_MM, RM1_MM, RM3_MM, RM4_MM,

RM5_MM, RM6_MM

• Three terminals (PLUS, MINUS, B) for RSPD_MM, RSND_MM, RNPPO_MM, RNNPO_MM, RSNWELL_MM, RNHR1000_MM, RNND_MM, RNPD_MM, RNHR_RF, RNNPO_RF, RNPPO_RF


12.3 CAPACITORS • Two terminals (PLUS, MINUS) for MIMCAPS_MM

• Three terminals (PLUS, MINUS, B) for NCAP_MM, PCAP_MM, MIMCAPM_RF


12.4 BIPOLARS • Three terminals (C, B, E)

• symbol, spectre, auLvs, auCdl, ivpcell, hspiceS, layout (Fixed)

12.5 DIODES • Two terminals (PLUS, MINUS)

• symbol, spectre, auLvs, auCdl, ivpcell, hspiceS, layout (Fixed)

12.6 Inductors • Three terminals (PLUS, MINUS, B)


12.7 Bond Pads • Two terminals (PLUS, MINUS)


12.8 Varactors • Two terminals (PLUS, MINUS) for VARDIOP_RF

• Three terminals (PLUS, MINUS, B) for VARMIS_18_RF



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13 CDF parameters 13.1 MOSFETS

• l (M) - gate length in meters

• w (M) - gate width in meters

• Number of Fingers - Number of poly gate stripes used in layout (w/nf width)

• Source Drain Metal Width (M) – Width of metal on Source and Drain in meters.

• Width Per Finger - Width of each gate stripe (non-editable)

• Multiplier - Number of Parallel MOS devices

• Calc Diff Params - cyclic which controls the calculation of area and periphery of the source/drain regions for simulation. Default is true which auto calculates the values. If nil, the user can enter the values.

• Source diffusion area - Calculated source diffusion area in square meters

• Drain diffusion area - Calculated drain diffusion area in square meters

• Source diffusion periphery - Calculated source diffusion periphery in meters

• Drain diffusion periphery - Calculated source diffusion periphery in meters

NOTE: To conform to electromigration rules, customer must choose proper finger width, finger number, or source/drain metal width according to device operating point.

13.2 RF MOSFETS • Width per Finger (M) - gate width in meters

• Length (M) - gate length in meters



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MOSFET ADD INSTANCE FORM


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13.3 RESISTORS • Resistance - Resistance value used for simulation

• w (M) - resistor width in meters

• l (M) - resistor length in meters (non-editable)

• Rho - resistor layer sheet rho (non-editable)

• Area (M^2) - resistor area for parasitics in meters squared(non-editable)

• Perim (M) - resistor perimeter for parasitics in meters (non-editable)

13.4 RF RESISTORS • Resistance - Resistance value used for simulation

• Width (M) - resistor width in meters

• Length (M) - resistor length in meters (non-editable)

• Rsh (ohm/sq) - resistor layer sheet rho (non-editable)

• Rend (ohm-um) – resistor end sheet rho (non-editable)

• delta Width (um) – resistor delta width (non-editable)

• delta Length (um) – resistor delta length (non-editable)


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RESISTOR ADD INSTANCE FORM


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13.5 CAPACITORS – MIMCAPS_MM • Capacitance - capacitance value used in simulation (non-editable)

• Total Capacitance - Capacitance multiplied times Multiplier (non-editable)

• w (M) - capacitor width in meters

• l (M) - capacitor length in meters

• CapA (F/M^2) - Plate Capacitance (non-editable, units are Farads per Meter Squared)

• CapP (F/M) - Fringe Capacitance (non-editable, units are Farads per Meter)

• Multiplier - Number of devices in layout (non-editable for mimcap)

13.6 CAPACITORS – NCAP_MM, PCAP_MM • Capacitance – capacitance value used in simulation ( based on rough

calculation)

• Total Capacitance – total capacitance value is Capacitance * Multiplier (non-editable)

• Spec – cyclic used to choose capacitor entry method (Capacitance, Cap & l, l & w)

• l (M) – capacitor length in meters

• w (M) – capacitor width in meters

• Multiplier - Number of Parallel MOS devices

• CapA (F/M^2) – Plate Capacitance (non-editable, units are Farads per Meter Squared)

• CapP (F/M) – Fringe Capacitance (non-editable, units are Farads per Meter)


• Width Per Finger - Width of each gate stripe (non-editable using totalWidth)

• Calc Diff Params - cyclic which controls the calculation of area and periphery of the source/drain regions for simulation. Default is true which auto calculates the values. If nil, the user can enter the values.

• Source diffusion area - Calculated source diffusion area in square meters


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• Drain diffusion area - Calculated drain diffusion area in square meters

• Source diffusion periphery - Calculated source diffusion periphery in meters

• Drain diffusion periphery - Calculated source diffusion periphery in meters

13.7 CAPACITORS – MIMCAPM_RF • Capacitance - capacitance value used in simulation

• Multi Square X - multiple square capacitors in x-direction

• Multi Square Y - multiple square capacitors in y-direction

• Width (X) - capacitor width in meters

• Length (Y) - capacitor length in meters


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CAPACITOR ADD INSTANCE FORM


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13.8 BIPOLARS • Model name - Spectre model name (non-editable)

• Multiplier - Number of Parallel Bipolar devices

• Width (M) – Emitter Width in metres (non-editable)

• Length (M) – Emitter Length in metres (non-editable)

• Emitter area – Calculated emitter area in meters squared (non-editable)

• Device initially off – bolean to turn device model off for simulation start-up.

• Estimated operating region – Simulation operating region (off, fwd, rev, sat)

• Linearized Region – Simulation operating region (yes, no)


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BIPOLAR ADD INSTANCE FORM


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13.9 DIODES • Device Area - Calculated junction area in meters squared (non-editable)

• Multiplier - Number of Parallel Diode devices

• Length (M) - diode length in meters

• Width (M) - diode width in meters

DIODE ADD INSTANCE FORM


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13.10 Inductors • Inductance – Inductance in Henries

• Inner Diameter (M) – inner diameter in meters

• Width (M) – width of inductor in meters

• Number of Turns – number of inductor turns.

INDUCTOR ADD INSTANCE FORM


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13.11 Bond Pads • Specified Index – multi layer number of PAD metal (1, 2, 3, 4, 5)

INDUCTOR ADD INSTANCE FORM

13.12 Varactors – VARDIOP_RF • Capacitance (zero bias) – zero bias capacitance value

• Number of Fingers – number of finger stripes used in layout

• Parasitic Cap. (fF/um^2) – area capacitance in fF/um2

• Fringe Cap. (fF/um) – fringe capacitance in fF/um

13.13 Varactors – VARMIS_18_RF • Capacitance (max) – maximum capacitance value

• Number of Fingers – number of finger stripes used in layout


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• Parasitic Cap. (fF/um^2) – area capacitance in fF/um2

• Fringe Cap. (fF/um) – fringe capacitance in fF/um

VARACTOR ADD INSTANCE FORM


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14 Component Label Defaults 14.1 MOSFETS

• component parameters: model, l, w, fingers, m

• operating point: ids, vgs, vds, vth, vdsat

• model: vtho, vsat

• instance name prefix: NM, NP

14.2 RF MOSFETS • component parameters: model, l, w, nf

• operating point: ids, vgs, vds, vth, vdsat

• model: vth, vsat

• instance name prefix: NM, NP

14.3 RESISTORS • component parameters: model, r, w, l

• operating point: v i res

• model: -

• instance name prefix: R

14.4 RF RESISTORS • component parameters: model, r, w, l

• operating point: v, res

• model: -

• instance name prefix: R

14.5 CAPACITORS – MIMCAPS_MM • component parameters: model, c, l, w, m

• operating point: cap

• model: -

• instance name prefix: C

14.6 CAPACITORS – NCAP_MM, PCAP_MM • component parameters: model, c, l, w, fingers, m


• model: vtho, tox, cj


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14.7 CAPACITORS – MIMCAPM_RF • component parameters: model, nx, ny, w, l


• model: -


14.8 BIPOLARS • component parameters: model, area, m

• operating point: betadc, ic, vce

• model: bf, is, vaf

• instance name prefix: Q

14.9 DIODES • component parameters: model, area, m

• operating point: id, vd, region

• model: is, rs, n

• instance name prefix: D

14.10 VARACTORS • component parameters: model, nf, c

• operating point: -

• model: -


14.11 Bond Pads • component parameters: model, index

• operating point: - i

• model: -


14.12 Inductors • component parameters: model, d, w, n

• operating point: - i, ind

• model: -


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15 Simulation Models The following simulators are supported in the PDK: Spectre hSpiceS UltraSim NOTE: MMSIM60 is recommended to run Spectre or UltraSim simulations. The following model library setup is done automatically when the user first opens the umc18mmrf library or uses a component from that library. The user may disable or modify this feature by editing the libInitCustomExit.il file found in the umc18mmrf library. Spectre: <pdkInstallDir>/Models/Spectre/018-rf-v2d4-control.scs <pdkInstallDir>/Models/Spectre/MM180_BJT_V112.mdl.scs <pdkInstallDir>/Models/Spectre/MM180_DIODE_V113.mdl.scs <pdkInstallDir>/Models/Spectre/MM180_LVT18_V113.lib.scs tt <pdkInstallDir>/Models/Spectre/MM180_LVT33_V113.lib.scs tt <pdkInstallDir>/Models/Spectre/MM180_MIMCAP_V101.lib.scs mimcaps_typ <pdkInstallDir>/Models/Spectre/MM180_REG18BPW_V123.lib.scs tt <pdkInstallDir>/Models/Spectre/MM180_REG18_V123.lib.scs tt <pdkInstallDir>/Models/Spectre/MM180_REG33BPW_V123.lib.scs tt <pdkInstallDir>/Models/Spectre/MM180_REG33_V113.lib.scs tt <pdkInstallDir>/Models/Spectre/MM180_RES_V111.lib.scs res_typ <pdkInstallDir>/Models/Spectre/MM180_RES_V132.lib.scs res_typ <pdkInstallDir>/Models/Spectre/MM180_ZVT18_V113.lib.scs tt <pdkInstallDir>/Models/Spectre/MM180_ZVT33_V113.lib.scs tt Where <pdkInstallDir> is the path where the UMC90nm PDK is installed and the second entry is the simulation corner that the user wants to simulate.

The user should follow the instructions provided with the device models from UMC to ensure the proper selection of sections for simulation.


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16 AddWire Utility Certain devices in the library have bulk pins (i.e N_18_MM, P_18_MM, RSND_MM, etc..). A utility has been added to the PDK to automatically wire these bulk terminals to user specified signals (i.e. gnd!, vdd!, etc..). This will help reduce schematic clutter while maintaining required circuit hookup. The following picture shows the result of executing the "addWire" routine.

There are no arguments to run the program, the user must type umc18mmrf_addWire() in the CIW. If you don’t have a schematic cellview open it will give you an error message.

If the user has instances selected when they run addWire, it will prompt them for the label name for those specific instances and will only add the wires to those instances. It does nothing to the schematic hierarchy.

If no instances are selected then the program will wire up all instances that have their bulk nodes unconnected. The user gets prompted for the label name for each type of instance, and they also have the option of running it down through the hierarchy or just at the current cellview.

And, finally, if the user does not want to use gnd! or vdd! as the label name, there is an entry box for the user to type in an alternative net name. If another wire name is used, it will be added to the cyclic list of label name choices - but only for that DFII session. Once you exit the dfII session, the cyclic is reset to gnd! and vdd!


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17 UpdateCDFs Utility When changes are made to a device inside the PDK, these changes often affect circuit design, which have already been created. For example, a sheet rho value may change on a resistor, which affects the length of the device passed to the simulator and used to generate the layout.

These parameters are not automatically updated in each of the designer’s circuit libraries. A function has been written and included as a part of the PDK to complete the update to an existing library such that all modifications made to a PDK since a previous release are reflected in each of the circuit designs inside a library.

The name of the function for this PDK is called "umc18mmrf_updateCDFs". There is a single argument to this function, which represents the design library, which is to be updated with the new CDF information. Once this routine has been run, all design schematics in the designated library will be in sync with the latest release of the PDK. Please note, however, that possible LVS violations may arise as a result of running this routine depending upon what changes have been made to the PDK. For example, a sheet rho change as specified earlier could cause a resistor to shrink in length in the schematic thus causing a mismatch as far as LVS is concerned. Please be sure that you verify again each design in simulation, DRC, and LVS to insure that no unintended modifications have been overlooked.

The syntax for this function is as follows:

In the CIW, type umc18mmrf_updateCDFs(libName) for the library which you wish to operate on. For example, given a library named designLib, the proper syntax for this routine would be:

umc18mmrf_updateCDFs("designLib")

Please be sure that the library name you choose to pass as an argument is present in the library manager window (i.e. - be sure that it is visible and located in your cds.lib file)


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18 Setting Environment Variables Environment variables control how various DFII commands work by default. These variables can be stored in the Library .cdsenv file which is located in the umc18mmrf directory. This library .cdsenv file is loaded by default in the PDK libinit.il file. The .cdsenv file, which is provided with the UMC .18 MM/RF PDK, contains five environment variables; setPPConn, xSnapSpacing, ySnapSpacing, updatePCellIncrement, and InitIOPinLayer.

1. setPPConn is a boolean layoutXL editor environment variable which

recognizes pseudo-parallel nets. These nets can be connected, or not connected as in the schematic, to produce an electrically equivalent layout. If set to nil, pseudo-parallel nets are ignored. These nets then require interconnect that matches the schematic exactly. In this PDK the setPPConn environment variable has been set to nil.

The designer can change the value of the setPPConn environment variable by editing the following line in the .cdsenv file:

layoutXL setPPConn boolean nil

The valid values for setPPConn are nil and t.

2. xSnapSpacing is a floating-point layout editor environment variable which controls the minimum distance the cursor moves in the X direction. In this PDK the xSnapSpacing environment variable has been set to 0.01.

The designer can change the value of the xSnapSpacing environment variable by editing the following line in the .cdsenv file: layout xSnapSpacing float 0.01 The valid values for xSnapSpacing are 0.01 to the desired value.

3. ySnapSpacing is a floating-point layout editor environment variable which controls the minimum distance the cursor moves in the Y direction. In this PDK the ySnapSpacing environment variable has been set to 0.01.

The designer can change the value of the ySnapSpacing environment variable by editing the following line in the .cdsenv file: layout ySnapSpacing float 0.01


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The valid values for ySnapSpacing are 0.01 to the desired value.

4. updatePCellIncrement is a floating-point layout editor environment variable

specifying how often the system updates pcell parameters and regenerates the pcell during a stretch operation.

The designer can change the value of the updatePCellIncrement environment variable by editing the following line in the .cdsenv file: layout updatePCellIncrement float 0.01 The valid values for updatePCellIncrement are 0.01 to the desired value.

5. initIOPinLayer is a string layoutXL editor environment variable specifying the default layer to use in the Gen From Source Form for I/O Pin creation.

The designer can change the value of the initIOPinLayer environment variable by editing the following line in the .cdsenv file: layoutXL initIOPinLayer string “ME1 drawing” The valid values for initIOPinLayer are any layer defined in the techfile.


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19 Techfile Layers Cadence will provide a standard display setup, and will not support desired changes to the display. The customer is free to modify the display.drf file used on-site to achieve any desired display.

Techfile layers defined in this PDK are done in accordance with UMC document G-06LMT-GENERATION18-LAYER_MAPPING_TABLE, Revision 2.3_P1 (UMC Official Layer Mapping Table). The user is referred to this UMC document for a complete listing of all layer/levels of the process technology.


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20 Virtuoso XL The standard Cadence Virtuoso XL design flow will be implemented. This includes basic connectivity of connection layers, wells, and substrate, and symbolic contacts. The M factor will be used for device instance multiplier - there will be no conflict with the parameter used in cell operation. Names will be displayed on the layout views to aid in schematic-layout instance correlation. Auto-abutment of MOSFET devices is supported. Pin permuting of MOSFET and Resistor device is also supported. The skill pcell layouts are compiled into the PDK.

The users should follow the guidelines listed below for layout design:

The VirtuosoXL tool requires a separate license for operation.

Users obtain maximum leverage from the PDK by doing schematic driven layout in the Virtuoso XL environment. This flow will produce a correct design layout. The Virtuoso Custom Router (IC Craftsman) can be used to finish the interconnects in the layout.

The VCR rules file for the target process is provided with the PDK.

Abutment is currently supported only for MOS transistors. Note, abutment will work only on schematic driven layouts.

Schematic Driven Layout is recommended over Netlist Driven Layout.

NOTE: Skill pcell source code is not included in the PDK kit.


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20.1 SYMBOLIC CONTACTS • M1_NACTIVE – Metal 1 to NPLUS DIFF contact

• M1_NWELL – Metal 1 to NWEL contact

• M1_PACTIVE – Metal 1 to PPLUS DIFF contact

• M1_POLY – Metal 1 to PO1 contact

• M1_PSUB - Metal1 to Substrate contact

• M2_M1 – Metal 2 to Metal 1 via contact





ADD CONTACT FORM


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21 Dracula Support No Dracula support will be provided with the exception of creating an auCdl netlist. Listed below is an example of the CDL netlist for each device.

CDL OUT FORM


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22 Assura Decks NOTE: This PDK revision B04_PB does not incorporate Assura Decks. The following descriptions are for reference only

The user needs to do the following in order to implement and use the Assura Verification decks:

1) Create a directory named:

• assura_umc18mmrf_tech 2) Place all Assura decks in the directory created above

( assura_umc18mmrf_tech).

3) Create a file named:

• assura_tech.lib

4) In this file ( assura_tech.lib ), the user needs to enter only one line:

DEFINE umc18mmrf_rcx ./assura_umc18mmrf_tech

Once these four steps have been completed, the user will then be able to run Assura Verification on this PDK.

The user needs the licenses for these tools to perform verification. When performing verification you have to provide the library name to the verification deck. Select the desired switches before starting the verification run. Refrain from working on the target layout being verified while the run is in progress.

Following are the tar files for the description of Assura verification setup only:

Assura RCX tar file name: G-DF-MIXED_MODE_RFCMOS18-1.8V_3.3V-1P6M-MMC-ASSURA-LPE-1.1-P3 Files Included: Topm_20k.tar g-df-mixedmode_rfcmos18-1.8V_3.3V-1p6m-mmc-assura-lvs-1.2-p5-extract.rul g-df-mixedmode_rfcmos18-1.8V_3.3V-1p6m-mmc-assura-lvs-1.2-p5- compare.rul bind.Model Version: 1.2_p5 Date: 05/12/03

Assura DRC tar file name: G-DF-MIXEDMODE_RFCMOS18-1.8V-3.3V-1P6M-MMC-Assura-drc-2.2-p5 Files Included: g-df-mixedmode_rfcmos18-1.8V_3.3V-1p6m-mmc-Assura-drc-2.2-p5.rul


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g-df-mixedmode_rfcmos18-1.8V_3.3V-1p6m-mmc-Assura-drc-2.2-p5.rsf umc_ant_assura_all.0.rul

umc_ant_assura_all-.0.rsf Version: DRC version: 2.2-p5

ANT version: 0 Date: DRC date: 04/11/03 ANT date: 04/21/03


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22.1 Assura DRC The following 3 Assura DRC files were tested with the PDK and were placed in the assura_umc18mmrf_tech directory:

• g-df-mixedmode_rfcmos18-1.8V_3.3V-1p6m-mmc-Assura-drc-2.2-p5.rul.

• umc_ant_assura_all.0.rul

• assuraESD.rul

The following switches are available in the

g-df-mixedmode_rfcmos18-1.8V_3.3V-1p6m-mmc-Assura-drc-2.2-p5.rul:

Technology Switches:

• BDSP_rule – checks rules for the bordered SP SRAM core regions

• BLSP1_rule – checks the rules for the borderless SP SRAM core regions

• BLSP_rule – checks the rules for the Virage SP SRAM core regions

• DP1_rule – checks the rules for the DP1 SRAM core regions

• DP2_rule – checks the rules for the DP2 SRAM core regions

• DP_rule – checks the rules for the DP SRAM core regions

• ROM_rule – checks the rules for the ROM regions

• metal2_is_top – specifies 2-Metal Technology




• top_metal_is_thick – specifies Thick Top Metal

Chip-Level Switches:

• SR – Seal ring rules are checked

Run-Time Intensive Switches:

• check_max_metal_space – Maximum Metal spacing rules are

checked

• check_density – Metal coverage rules are checked

• check_slots – Slot rules are checked


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By default, if none of the switches are set, the file will assume the following:

• The design incorporates 6-metal technology

• Off-grid checks will be performed

• The chip-level checks will NOT be performed

• The run-time intensive checks will NOT be performed.

22.2 Assura Antenna The following Assura Antenna file was tested with the PDK and was placed in the assura_umc18mmrf_tech directory:

• umc_ant_assura_all.0.rul

The following switches are available in the

assuraANT.rul file:

Technology Switches:



• metal3_is_top – specifies 3-Metal Technology • metal4_is_top – specifies 4-Metal Technology



By default, if none of the switches are set, the file will assume 6-metal process.

Antenna Check Format Switches:

• Check_All_Top_Antenna – Performs one level area and perimeter antenna checks. For example, checks m3 area/gate area and m3 perimeter/gate perimeter check.

• Check_Cumulative_Area_Antenna – Performs cumulative area

antenna checks.

• Check_Cumulative_Perimeter_Antenna – Performs cumulative perimeter antenna checks.


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22.3 Assura ESD The Assura Antenna files tested with the PDK were placed in the assura_umc18mmrf_tech directory and are named:

• assuraESD.rul

No switches are available in the assuraESD.rul file.

ASSURA DRC FORM


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22.4 Assura LVS The Assura LVS files tested with the PDK were placed in the assura_umc18mmrf_tech directory:

• g-df-mixedmode_rfcmos18-1.8V_3.3V-1p6m-mmc-assura-lvs-1.2-p3-extract.rul

• g-df-mixedmode_rfcmos18-1.8V_3.3V-1p6m-mmc-assura-lvs-1.2-p3-compare.rul

• bind.Model – for use with any devices from VST or Artisan libraries. Please see usage notes in extract.rul for more information.

The following switches are available in the extract.rul file:

• Artisan_Lib – for extraction of devices from Artisan libraries

• Skip_Soft-Connect_Checks - Select the switch to skip the reporting of multStamp, floating, and multConnect errors. By default, this

switch is not set.

• Top_Metal_Thickness--20K – Sets Metal Resistor Coefficients for 20KA thick Top Metal.

To avoid RCX run-time errors, use the switches below to skip the extraction statements of the devices without IVPCELL view.

• Skip_Logic_Device_Extraction—Skips extraction of logic devices.

• Skip_Mixed_Mode_Device_Extraction—Skips extraction of Mixed Mode ( _MM) devices.

• Skip_RF_Device_Extraction—Skips extraction of RF ( _RF) devices.

DO NOT SELECT ANY OF THE FOLLOWING SWITCHES:

• Top_Metal—ME4 – This is not supported in this PDK.

• Top_Metal—ME5 – This is not supported in this PDK.


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The default switch is for the 8KA 1P6M process.

ASSURA LVS FORM

22.5 Assura RCX The Assura RCX files tested with the PDK were placed in the following directory:

• assura_umc18mmrf_tech - Directory where Assura RCX files are provided


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Please consult the Assura RCX users manual for available RCX options.

NOTE: The av_extracted view is not supported in these Assura rules.

To enable av_extracted views please follow the instructions below:

1) Convert the extract rules with the “Skip_Logic_Device_Extraction” switch set for capgen input

The following files should be found in your assura_umc18mmrf_tech directory:

cap_coeff.dat - assura 3.0 binary file output from capgen -S run

compare.rul - compare rules for LVS

extract.rul - extract rules file for LVS

lvsfile - converted Assura extract file for RCX

p2lvsfile - layer mapping file for procfile & extract.rul

procfile - Process description file (SEE NOTE BELOW)

umc18mm_20k_rcx.rsf - sample RSF to run Assura RCX

Additional files - RCXdspfINIT, RCXspiceINIT, RCXutilities

- cap.so, s2d.log, caps2d

- paxfile_coeff, rcxfs.dat

The capgen lvsfile is created from the Assura extract rules

file. A sample RSF file, lvsfile.rsf is shown below to do this.

The Cadence PDK compatible Assura extract rules file, extract.rul

is included. You may use this or your own file. Change the

lvsfile.rsf file as needed. Within the assura_umc18mmrf_tech

directory, run Assura from Unix:

Sample lvsfile.rsf:

/**********************************************************************


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Assura RCX sample RSF for capgen lvsfile creation

Use this file to create the capgen "lvsfile" from extract.rul

***********************************************************************/

avParameters(

?rulesFile "extract.rul"

?rcxFile "lvsfile"

?inputLayout ("df2" "dummyLayoutName" )

?cellName "dummyCellname"

?viewName “dummyviewName”

?cdslib “./cds.lib”

?set “Skip_Logic_Device_Extraction”

?runName "lvs_convert"

?compileOnly t

)

Note: Set ?inputLayout, ?cellName and ?viewName to point to data.

2) Run “assura lvsfile.rsf > lvs_convert.log” from the Unix prompt

The output will be the file "lvsfile" which will be used

as an input to capgen. The other files from the run

(lvs_convert.???) can be deleted.

3) Execute the second capgen command from Unix prompt within the assura_umc18mmrf_tech.

% capgen -C -lvs lvsfile -p2lvs p2lvsfile -mos_diff_ap -cap_unit 1 .

Note: The period “.” at the end of the command stands for current directory.


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ASSURA RCX FORM


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23 DEVICE SPECIFICATIONS

Model and Layout Source

Device Description

Spectre Model

received

HspiceS Model

received

GDS or DFII

Sample Layout

Received

Fixed Layout or Variable Layout (Pcell)

Mos N_18_MM 1.8 volt NMOS transistor y y y Pcell N_BPW_18_MM 1.8 volt triple-well NMOS transistor y y y Pcell N_33_MM 3.3 volt NMOS transistor y y y Pcell N_BPW_33_MM 3.3 volt triple-well NMOS transistor y y y Pcell N_LV_18_MM 1.8 volt low vt NMOS transistor y y y Pcell N_LV_33_MM 3.3 volt low vt NMOS transistor y y y Pcell N_ZERO_18_MM 1.8 volt zero vt NMOS transistor y y y Pcell N_ZERO_33_MM 3.3 volt zero vt NMOS transistor y y y Pcell P_18_MM 1.8 volt PMOS transistor y y y Pcell P_33_MM 3.3 volt PMOS transistor y y y Pcell P_LV_18_MM 1.8 volt low vt PMOS transistor y y y Pcell P_LV_33_MM 3.3 volt low vt PMOS transistor y y y Pcell

RF Mos N_L18W500_18_RF 1.8 volt variable finger RF NMOS transistor y y y Pcell N_L34W500_33_RF 3.3 volt variable finger RF NMOS transistor y y y Pcell N_PO7W500_18_RF 1.8 volt variable length RF NMOS transistor y y y Pcell N_PO7W500_33_RF 3.3 volt variable length RF NMOS transistor y y y Pcell P_L18W500_18_RF 1.8 volt variable finger RF PMOS transistor y y y Pcell P_L34W500_33_RF 3.3 volt variable finger RF PMOS transistor y y y Pcell P_PO7W500_18_RF 1.8 volt variable length RF PMOS transistor y y y Pcell P_PO7W500_33_RF 3.3 volt variable length RF PMOS transistor y y y Pcell

Resistor RSND_MM N+ diffused resistor w/ salicide y y y Pcell RSPD_MM P+ diffused resistor w/ salicide y y y Pcell RNPPO_MM P+ poly resistor w/o salicide y y y Pcell


UMC Confidential

Ver. B04_PB 60

RNNPO_MM N+ poly resistor w/o salicide y y y Pcell RSNWELL_MM N-well resistor y y y Pcell RNHR1000_MM High resistive poly resistor y y y Pcell RNND_MM N+ diffused resistor w/o salicide y y y Pcell RNPD_MM P+ diffused resistor w/o salicide y y y Pcell RM1_MM Metal 1 resistor y y y Pcell RM2_MM Metal 2 resistor y y y Pcell RM3_MM Metal 3 resistor y y y Pcell RM4_MM Metal 4 resistor y y y Pcell RM5_MM Metal 5 resistor y y y Pcell RM6_MM Metal 6 resistor y y y Pcell

RF Resistor RNHR_RF RF High resistive poly resistor y y y Pcell RNNPO_RF RF N+ poly resistor w/o salicide y y y Pcell RNPPO_RF RF P+ poly resistor w/o salicide y y y Pcell

Capacitor MIMCAPS_MM Single-squared MM Metal capacitor y y y Pcell NCAP_MM NMOS gate capacitor y y y Pcell PCAP_MM PMOS gate capacitor y y y Pcell

RF Capacitor MIMCAPM_RF RF Metal capacitor y y y Pcell

Diode DION_MM N+/psub diode y y y Fixed DIONW_MM Nwell/psub diode y y y Fixed DIOP_MM P+/nwell diode y y y Fixed

BJT PNP_V50X50_MM Vertical substrate PNP ( 5x5 ) y y y Fixed PNP_V100X100_MM Vertical substrate PNP ( 10x10 ) y y y Fixed Inductor L_SLCR20K_RF Circular spiral RF inductor y y y Pcell Bond Pad PAD_RF Bond Pad y y y Fixed


UMC Confidential

Ver. B04_PB 61

Varactor VARDIOP_RF P+/Nwell RF diode varactor y y y Pcell VARMIS_18_RF 1.8V N+/Nwell RF MIS varactor y y y Pcell

23.1 MOS FORMAL PARAMETERS

l (gate length in microns) Device min Value Got from Design Rule # max Value Got from

N_18_MM 180n Design Rules 4.14Aa 50u Spectre model N_BPW_18_MM 180n Design Rules 4.14Aa 50u Spectre model N_33_MM 340n Design Rules 4.14Ab 50u Spectre model N_BPW_33_MM 340n Design Rules 4.14Ab 50u Spectre model N_LV_18_MM 240n Design Rules 4.7Aa 50u Spectre model N_LV_33_MM 500n Design Rules 4.9A 50u Spectre model N_ZERO_18_MM 300n Design Rules 4.8A 50u Spectre model N_ZERO_33_MM 500n Design Rules 4.7Ab 50u Spectre model P_18_MM 180n Design Rules 4.14Ba 50u Spectre model P_33_MM 340n Design Rules 4.14Bb 50u Spectre model P_LV_18_MM 240n Design Rules 4.4A 50u Spectre model P_LV_33_MM 500n Design Rules 4.5A 50u Spectre model

w (gate width in

microns) Device min Value Got from max Value Got from

N_18_MM 240n Spectre model 100u Spectre modelN_BPW_18_MM 240n Spectre model 100u Spectre modelN_33_MM 240n Spectre model 100u Spectre modelN_BPW_33_MM 240n Spectre model 100u Spectre modelN_LV_18_MM 240n Spectre model 100u Spectre modelN_LV_33_MM 800n Spectre model 100u Spectre modelN_ZERO_18_MM 240n Spectre model 100u Spectre modelN_ZERO_33_MM 800n Spectre model 100u Spectre model P_18_MM 240n Spectre model 100u Spectre modelP_33_MM 240n Spectre model 100u Spectre modelP_LV_18_MM 240n Spectre model 100u Spectre modelP_LV_33_MM 800n Spectre model 100u Spectre model


UMC Confidential

Ver. B04_PB 62

Fingers (number of fingers)

Device min Value Got from max Value Got from N_18_MM 1 Default 100 PDK standard N_BPW_18_MM 1 Default 100 PDK standard N_33_MM 1 Default 100 PDK standard N_BPW_33_MM 1 Default 100 PDK standard N_LV_18_MM 1 Default 100 PDK standard N_LV_33_MM 1 Default 100 PDK standard N_ZERO_18_MM 1 Default 100 PDK standard N_ZERO_33_MM 1 Default 100 PDK standard P_18_MM 1 Default 100 PDK standard P_33_MM 1 Default 100 PDK standard P_LV_18_MM 1 Default 100 PDK standard P_LV_33_MM 1 Default 100 PDK standard


UMC Confidential

Ver. B04_PB 63

23.2 RF MOS FORMAL PARAMETERS Device Name

Formal Parameters

l (Length) min Value Got from max Value Got from

N_L18W500_18_RF 180.0n Spectre model 180.0n Spectre model N_L34W500_33_RF 340.0n Spectre model 340.0n Spectre model N_PO7W500_18_RF 200n Spectre model 500n Spectre model N_PO7W500_33_RF 340.0n Spectre model 800n Spectre model P_L18W500_18_RF 180.0n Spectre model 180.0n Spectre model P_L34W500_33_RF 340.0n Spectre model 340.0n Spectre model P_PO7W500_18_RF 200n Spectre model 500n Spectre model P_PO7W500_33_RF 340.0n Spectre model 800n Spectre model Device Name

w (Finger Width)

min Value Got from max Value Got from N_L18W500_18_RF 5u Spectre model 5u Spectre model N_L34W500_33_RF 5u Spectre model 5u Spectre model N_PO7W500_18_RF 5u Spectre model 5u Spectre model N_PO7W500_33_RF 5u Spectre model 5u Spectre model P_L18W500_18_RF 5u Spectre model 5u Spectre model P_L34W500_33_RF 5u Spectre model 5u Spectre model P_PO7W500_18_RF 5u Spectre model 5u Spectre model P_PO7W500_33_RF 5u Spectre model 5u Spectre model

Device Name

nf (Finger Number)

min Value Got from max Value Got from N_L18W500_18_RF 5 Spectre model 21 Spectre model N_L34W500_33_RF 5 Spectre model 21 Spectre model N_PO7W500_18_RF 7 Spectre model 7 Spectre model N_PO7W500_33_RF 7 Spectre model 7 Spectre model P_L18W500_18_RF 5 Spectre model 21 Spectre model P_L34W500_33_RF 5 Spectre model 21 Spectre model P_PO7W500_18_RF 7 Spectre model 7 Spectre model P_PO7W500_33_RF 7 Spectre model 7 Spectre model


UMC Confidential

Ver. B04_PB 64

23.3 RESISTOR FORMAL PARAMETERS r (resistance in Ohms)

Device min Value Got from Design Rule # max Value Got from Design Rule # RSND_MM 168.000m Calculation Calc.1 33.3107K Calculation Calc. 3 RSPD_MM 168.000m Calculation Calc.1 33.3107K Calculation Calc. 3 RNPPO_MM 21.1085 Calculation Calc.1 2.62455M Calculation Calc. 3 RNNPO_MM 5.11481 Calculation Calc.1 1.35984M Calculation Calc. 3 RSNWELL_MM 31.376 Calculation Calc.1 6.19403K Calculation Calc. 3 RNHR1000_MM 43.263 Calculation Calc.5 7.56992M Calculation Calc. 6 RNND_MM 2.39596 Calculation Calc.1 291.817K Calculation Calc. 3 RNPD_MM 4.73918 Calculation Calc.1 484.5K Calculation Calc. 3 RM1_MM 2.82975m Calculation Calc.2 6.41667 Calculation Calc.4 RM1_MM 2.1545m Calculation Calc.2 4.42857 Calculation Calc.4 RM3_MM 2.1545m Calculation Calc.2 4.42857 Calculation Calc.4 RM4_MM 2.1545m Calculation Calc.2 4.42857 Calculation Calc.4 RM5_MM 2.1545m Calculation Calc.2 4.42857 Calculation Calc.4 RM6_MM 2.16275m Calculation Calc.2 1.86364 Calculation Calc.4

w (width In microns)

Device min Value Got from Design Rule # max Value Got from RSND_MM 240n Design Rules 4.1Aa 20u PDK Standard RSPD_MM 240n Design Rules 4.1Ab 20u PDK Standard RNPPO_MM 180n Design Rules 4.14Aa 20u PDK Standard RNNPO_MM 180n Design Rules 4.14Ba 20u PDK Standard RSNWELL_MM 1.5u Design Rules 4.2Ab 20u PDK Standard RNHR1000_MM 180n Design Rules 4.14Aa 20u PDK Standard RNND_MM 240n Design Rules 4.1Aa 20u PDK Standard RNPD_MM 240n Design Rules 4.1Ab 20u PDK Standard RM1_MM 240n Design Rules 4.20A 20u PDK Standard RM1_MM 280n Design Rules 4.22A 20u PDK Standard RM3_MM 280n Design Rules 4.24A 20u PDK Standard RM4_MM 280n Design Rules 4.26A 20u PDK Standard RM5_MM 280n Design Rules 4.28A 20u PDK Standard RM6_MM 440n Design Rules 4.31A 20u PDK Standard


UMC Confidential

Ver. B04_PB 65

Note: Calc.1 ( Salicided sheet resistance ) * ( minL + deltaL ) / ( maxW + deltaW ) + 2 * ( Non-salicided sheet resistance ) / ( maxW + deltaW ) Calc.2 ( Salicided sheet resistance ) * ( minL ) / ( maxW ) Calc.3 ( Salicided sheet resistance ) * ( maxL + deltaL ) / ( minW + deltaW ) + 2 * ( Non-salicided sheet resistance ) / ( minW + deltaW) Calc.4 ( Salicided sheet resistance ) * ( maxL ) / ( minW ) Calc.5 ( Salicided sheet resistance ) * ( minL -0.4um ) / ( maxW + deltaW ) + 2 * ( Non-salicided sheet resistance ) / ( maxW + deltaW ) Calc.6 ( Salicided sheet resistance ) * ( maxL -0.4um ) / ( minW + deltaW ) + 2 * ( non-salicided sheet resistance ) / ( minW + deltaW )


UMC Confidential

Ver. B04_PB 66

23.4 RF RESISTOR FORMAL PARAMETERS

Device Name Formal Parameters

r (Resistance)

min Value Got from max Value Got from

RNHR_RF 972.1002 Calculation 10.52856K Calculation RNNPO_RF 136.6264 Calculation 1.205465K Calculation RNPPO_RF 467.7584 Calculation 3.710338K Calculation

Device Name

w

(Width)

min Value Got from max

Value Got from

RNHR_RF 2u Spectre model 10u Spectre modelRNNPO_RF 2u Spectre model 10u Spectre modelRNPPO_RF 2u Spectre model 10u Spectre model

Device Name

l

(Length)

min Value Got from max

Value Got from

RNHR_RF 2u Spectre model 100u Spectre modelRNNPO_RF 2u Spectre model 100u Spectre modelRNPPO_RF 2u Spectre model 100u Spectre model


UMC Confidential

Ver. B04_PB 67

23.5 CAPACITOR FORMAL PARAMETERS

c (capacitance In Farads)

Device min Value Got from Design Rule # max Value Got from Design Rule # MIMCAPS_MM N/E N/E NCAP_MM 1.8618f Design Rules Dim.1 3.3011p Design Rules Dim.2 PCAP_MM 1.8618f Design Rules Dim.1 3.3011p Design Rules Dim.2

l (length in Metres)

Device min Value Got from Design Rule # max Value Got from MIMCAPS_MM 1.84u Design Rules Dim.3 100u Spectre model NCAP_MM 180n Design Rules 4.14Aa 20u Spectre model PCAP_MM 180n Design Rules 4.14Ba 20u Spectre model

W (width in Metres)

Device min Value Got from max Value Got from MIMCAPS_MM 1.84u Dim.3 100u Spectre modelNCAP_MM 440n Dim.4 20u Spectre modelPCAP_MM 440n Dim.5 20u Spectre model

Fingers (number of Fingers)

Device min Value Got from max Value Got from MIMCAPS_MM NCAP_MM 1 Default 50 PDK StandardPCAP_MM 1 Default 50 PDK Standard


UMC Confidential

Ver. B04_PB 68

Note: Dim.1 minW * minL * ( Area Capacitance ) + 2 * ( minW + minL ) * ( Fringe Capacitance ) Dim.2 maxW * maxL * ( Area Capacitance ) + 2 * ( maxW + maxL ) * ( Fringe Capacitance ) Dim.3 ( minWidth of VI5 ) + 2 * ( MMC enclosure of VI5 ) 4.30A 4.29D Dim.4 ( MinWidth of contact ) + 2 * ( Diffusion enclosure of Contact ) 4.19A 4.19G Dim.5 ( MinWidth of contact ) + 2 * ( Diffusion enclosure of Contact ) 4.19A 4.19F


UMC Confidential

Ver. B04_PB 69

23.6 RF CAPACITOR FORMAL PARAMETERS Device Name

Formal Parameters

c (Capacitance)

min Value Got from max Value Got from MIMCAPM_RF 103.00f Calculation 5.047p Calculation

Device Name

l (Length(Y))

min Value Got from max Value Got from MIMCAPM_RF 10u Spectre model 70u Spectre model

Device Name

w (Width(X))

min Value Got from max Value Got from MIMCAPM_RF 10u Spectre model 70u Spectre model

Device Name

nx (Multi Square X)

min Value Got from max Value Got from MIMCAPM_RF 1 Spectre model 7 Spectre model

Device Name

ny (Multi Square Y)

min Value Got from max Value Got from MIMCAPM_RF 1 Spectre model 7 Spectre model


UMC Confidential

Ver. B04_PB 70

23.7 INDUCTOR FORMAL PARAMETERS Device Name

Formal Parameters

l (Inductance)

min Value Got from max Value Got from L_SLCR20K_RF 567.9646p Calculation 14.27438n Calculation

Device Name

d (Diameter)

min Value Got from max Value Got from L_SLCR20K_RF 126u Spectre model 238u Spectre model

Device Name

w (Width) min Value Got from max Value Got from

L_SLCR20K_RF 6u Spectre model 20u Spectre model

Device Name

n (Turn Number)

min Value Got from max Value Got from L_SLCR20K_RF 1.5 Spectre model 5.5 Spectre model

23.8 BOND PAD FORMAL PARAMETERS

Device Name index min Value Got from max Value Got from

PAD_RF 1 Spectre model 5 Spectre model


UMC Confidential

Ver. B04_PB 71

23.9 VARACTOR FORMAL PARAMETERS

Device Name Formal Parameters

c (C(zero bias))

min Value Got from max Value Got from VARDIOP_RF 406.32f Calculation 1.62528p Calculation VARMIS_18_RF N/A N/A

Device Name c (Cmax) min Value Got from max Value Got from

VARDIOP_RF N/A N/A VARMIS_18_RF 1.030819p Calculation 5.154096p Calculation

Device Name

nf (Finger Number)

min Value Got from max Value Got from VARDIOP_RF 30 Spectre model 120 Spectre model VARMIS_18_RF 24 Spectre model 120 Spectre model

23.10 BIPOLAR FORMAL PARAMETERS

The bipolar devices have fixed layouts and do not have any formal editable parameters.

23.11 DIODES FORMAL PARAMETERS The diode devices have fixed layouts and do not have any formal editable parameters.


UMC Confidential

Ver. B04_PB 72

24 DEVICE DATASHEETS 24.1 N_18_MM – 1.8 volt NMOS Transistor

Spectre Netlist Spectre Model Name = “n_18_mm” NM0 (D G S B) n_18_mm w=2u l=180.0n as=9.8e-13 ad=9.8e-13 ps=4.98u \

pd=4.98u m=(1)*(1)

HspiceS Netlist

HspiceS Model Name = “N_18_MM” MNM0 D G S B N_18_MM L=180E-9 W=2E-6 AD=980E-15 AS=980E-15 PD=4.98E-6

+PS=4.98E-6 M=+1.00000000E+00

DIVA LVS Netlist

DIVA Device Name = “N_18_MM” ; N_18_MM Instance /NM0 = auLvs device M0

d N_18_MM D G S B (p D S)

i 0 N_18_MM D G S B " L 180e-9 W 2e-6 M 1.0 "

CDL Netlist

CDL Device Name = “N_18_MM” MMN0 D G S B N_18_MM W=2u L=180.0n M=1


UMC Confidential

Ver. B04_PB 73

Assura Netlist

Assura auLvs Device Name = “N_18_MM”

C N_18_MM MOS DRAIN B GATE B SOURCE B SUBSTRATE B ;;

* 4 pins

* 4 nets

* 0 instances i MN0 N_18_MM D G S B ; L 1.8e-07 W 2e-06 effW 2e-06 ;


UMC Confidential

Ver. B04_PB 74

N_18_MM (diagrammatic layout)

Device Layers Layer Color and Fill DIFF

NPLUS

PO1

CONT

ME1

SYMBOL (MMSYMBOL)

Device Derivation

Device Layer Derivation Recognition DIFF AND NPLUS CONTAINS PO1

G PO1

D DIFF AND NPLUS NOT PO1

S DIFF AND NPLUS NOT PO1

B Substrate

LVS Comparison

Parameter Calculation Length PO1 intersecting DIFF (illustrated above)

Width PO1 inside DIFF (illustrated above)

Width

Length


UMC Confidential

Ver. B04_PB 75

* S and D are PERMUTABLE


UMC Confidential

Ver. B04_PB 76

24.2 P_18_MM – 1.8 volt PMOS Transistor

Spectre Netlist

Spectre Model Name = “p_18_mm” PM0 (D G S B) p_18_mm w=2u l=180.0n as=9.8e-13 ad=9.8e-13 ps=4.98u \

pd=4.98u m=(1)*(1)

HspiceS Netlist

HspiceS Model Name = “P_18_MM” MPM0 D G S B P_18_MM L=180E-9 W=2E-6 AD=980E-15 AS=980E-15 PD=4.98E-6

+PS=4.98E-6 M=+1.00000000E+00

DIVA LVS Netlist

DIVA Device Name = “P_18_MM” ; P_18_MM Instance /PM0 = auLvs device M0

d P_18_MM D G S B (p D S)

i 0 P_18_MM D G S B " L 180e-9 W 2e-6 M 1.0 "

CDL Netlist

CDL Device Name = “P_18_MM” MPM0 D G S B P_18_MM W=2u L=180.0n M=1


UMC Confidential

Ver. B04_PB 77

Assura Netlist

Assura auLvs Device Name = “P_18_MM”

c P_18_MM MOS DRAIN B GATE B SOURCE B SUBSTRATE B ;;

* 4 pins

* 4 nets

* 0 instances i MP0 P_18_MM D G S B ; W 2e-06 effW 2e-06 L 1.8e-07;


UMC Confidential

Ver. B04_PB 78

P_18_MM (diagrammatic layout)

Device Layers Layer Color and Fill NWEL

DIFF

PPLUS

PO1

CONT

ME1

SYMBOL (MMSYMBOL)

Device Derivation

Device Layer Derivation Recognition NWEL AND DIFF AND PPLUS CONTAINS PO1

G PO1

D NWEL AND DIFF AND PPLUS NOT PO1

S NWEL AND DIFF AND PPLUS NOT PO1

B NWEL

LVS Comparison



Width

Length


UMC Confidential

Ver. B04_PB 79



UMC Confidential

Ver. B04_PB 80

24.3 N_33_MM – 3.3 volt NMOS Transistor

Spectre Netlist Spectre Model Name = “n_33_mm” NM0 (D G S B) n_33_mm w=2u l=340.0n as=1.28e-12 ad=1.28e-12 ps=5.28u \

pd=5.28u m=(1)*(1)

HspiceS Netlist

HspiceS Model Name = “N_33_MM” MNM0 D G S B N_33_MM L=340E-9 W=2E-6 AD=1.28E-12 AS=1.28E-12 PD=5.28E-6

+PS=5.28E-6 M=+1.00000000E+00

DIVA LVS Netlist

DIVA Device Name = “N_33_MM” ; N_33_MM Instance /NM0 = auLvs device M0

d N_33_MM D G S B (p D S)

i 0 N_33_MM D G S B " L 340e-9 W 2e-6 M 1.0 "

CDL Netlist

CDL Device Name = “N_33_MM” MMN0 D G S B N_33_MM W=2u L=340.0n M=1


UMC Confidential

Ver. B04_PB 81

Assura Netlist

Assura auLvs Device Name = “N_33_MM”

C N_33_MM MOS DRAIN B GATE B SOURCE B SUBSTRATE B ;;

* 4 pins

* 4 nets

* 0 instances i MN0 N_33_MM D G S B ; W 2e-06 effW 2e-06 L 3.4e-07;


UMC Confidential

Ver. B04_PB 82

N_33_MM (diagrammatic layout)


NPLUS

PO1

CONT

TG

ME1

SYMBOL (MMSYMBOL)

Device Derivation

Device Layer Derivation Recognition DIFF AND NPLUS AND TG CONTAINS PO1

G PO1

D DIFF AND NPLUS AND TG NOT PO1

S DIFF AND NPLUS AND TG NOT PO1

B Substrate

LVS Comparison



Width

Length


UMC Confidential

Ver. B04_PB 83



UMC Confidential

Ver. B04_PB 84

24.4 P_33_MM – 3.3 volt PMOS Transistor

Spectre Netlist Spectre Model Name = “p_33_mm” PM0 (D G S B) p_33_mm w=2u l=340.0n as=1.28e-12 ad=1.28e-12 ps=5.28u \

pd=5.28u m=(1)*(1)

HspiceS Netlist

HspiceS Model Name = “P_33_MM” MPM0 D G S B P_33_MM L=340E-9 W=2E-6 AD=1.28E-12 AS=1.28E-12 PD=5.28E-6

+PS=5.28E-6 M=+1.00000000E+00

DIVA LVS Netlist

DIVA Device Name = “P_33_MM” ; P_33_MM Instance /PM0 = auLvs device M0

d P_33_MM D G S B (p D S)

I 0 P_33_MM D G S B " L 340e-9 W 2e-6 M 1.0 "

CDL Netlist

CDL Device Name = “P_33_MM” MPM0 D G S B P_33_MM W=2u L=340.0n M=1


UMC Confidential

Ver. B04_PB 85

Assura Netlist

Assura auLvs Device Name = “P_33_MM”

c P_33_MM MOS DRAIN B GATE B SOURCE B SUBSTRATE B ;;

* 4 pins

* 4 nets

* 0 instances i MP0 P_33_MM D G S B ; effW 2e-06 L 3.4e-07 W 2e-06;


UMC Confidential

Ver. B04_PB 86

P_33_MM (diagrammatic layout)


DIFF

PPLUS

TG

PO1

CONT

ME1

SYMBOL ( MMSYMBOL)

Device Derivation

Device Layer Derivation Recognition NWEL AND DIFF AND PPLUS AND TG

CONTAINS PO1

G PO1

D NWEL AND DIFF AND PPLUS AND TG NOT PO1

S NWEL AND DIFF AND PPLUS AND TG NOT PO1

B NWEL

Width

Length


UMC Confidential

Ver. B04_PB 87

LVS Comparison





UMC Confidential

Ver. B04_PB 88

24.5 N_LV_18_MM – 1.8 volt low vt NMOS Transistor

Spectre Netlist Spectre Model Name = “n_lv_18_mm” NM0 (D G S B) n_lv_18_mm w=2u l=240.0n as=9.8e-13 ad=9.8e-13 ps=4.98u \

pd=4.98u m=(1)*(1)

HspiceS Netlist

HspiceS Model Name = “N_LV_18_MM” MNM0 D G S B N_LV_18_MM L=240E-9 W=2E-6 AD=980E-15 AS=980E-15

PD=4.98E-6 PS=4.98E-6 M=+1.00000000E+00

DIVA LVS Netlist

DIVA Device Name = “N_LV_18_MM” ; N_LV_18_MM Instance /NM0 = auLvs device M0

d N_LV_18_MM D G S B (p D S)

i 0 N_LV_18_MM D G S B " L 240e-9 W 2e-6 M 1.0 "

CDL Netlist

CDL Device Name = “N_LV_18_MM” MMN0 D G S B N_LV_18_MM W=2u L=240.0n M=1


UMC Confidential

Ver. B04_PB 89

Assura Netlist

Assura auLvs Device Name = “N_LV_18_MM”

C N_LV_18_MM MOS DRAIN B GATE B SOURCE B SUBSTRATE B ;;

* 4 pins

* 4 nets

* 0 instances i MN0 N_LV_18_MM D G S B ; W 2e-06 effW 2e-06 L 2.4e-07;


UMC Confidential

Ver. B04_PB 90

N_LV_18_MM (diagrammatic layout)


NPLUS

PO1

CONT

VT (VTNL)

ME1

SYMBOL (MMSYMBOL)

Device Derivation

Device Layer Derivation Recognition DIFF AND NPLUS AND VTNL CONTAINS PO1

G PO1

D DIFF AND NPLUS AND VTNL NOT PO1

S DIFF AND NPLUS AND VTNL NOT PO1

B Substrate

LVS Comparison



Width

Length


UMC Confidential

Ver. B04_PB 91

* PLUS and MINUS are PERMUTABLE


UMC Confidential

Ver. B04_PB 92

24.6 P_LV_18_MM – 1.8 volt low vt PMOS Transistor

Spectre Netlist Spectre Model Name = “p_lv_18_mm” PM0 (D G S B) p_lv_18_mm w=2u l=240.0n as=980e-15 ad=980e-15 ps=4.98u \

pd=4.98u m=(1)*(1)

HspiceS Netlist

HspiceS Model Name = “P_LV_18_MM” MPM0 D G S B P_LV_18_MM L=240E-9 W=2E-6 AD=980E-15 AS=980E-15

PD=4.98E-6 PS=4.98E-6 M=+1.00000000E+00

DIVA LVS Netlist

DIVA Device Name = “P_LV_18_MM” ; P_LV_18_MM Instance /PM0 = auLvs device M0

d P_LV_18_MM D G S B (p D S)

i 0 P_LV_18_MM D G S B " L 240e-9 W 2e-6 M 1.0 "

CDL Netlist

CDL Device Name = “P_LV_18_MM” MPM0 D G S B P_LV_18_MM W=2u L=240.0n M=1


UMC Confidential

Ver. B04_PB 93

Assura Netlist

Assura auLvs Device Name = “P_LV_18_MM”

c P_LV_18_MM MOS DRAIN B GATE B SOURCE B SUBSTRATE B ;;

* 4 pins

* 4 nets

* 0 instances i MP0 P_LV_18_MM D G S B ; W 2e-06 effW 2e-06 L 2.4e-07;


UMC Confidential

Ver. B04_PB 94

P_LV_18_MM (diagrammatic layout)


DIFF

PPLUS

VT (VTPL)

PO1

CONT

ME1

SYMBOL (MMSYMBOL)

Device Derivation

Device Layer Derivation Recognition NWEL AND DIFF AND PPLUS AND VTPL

CONTAINS PO1

G PO1

D NWEL AND DIFF AND PPLUS AND VTPL NOT PO1

S NWEL AND DIFF AND PPLUS AND VTPL NOT PO1

B NWEL

Width

Length


UMC Confidential

Ver. B04_PB 95

LVS Comparison





UMC Confidential

Ver. B04_PB 96

24.7 N_LV_33_MM – 3.3 volt low vt NMOS Transistor

Spectre Netlist Spectre Model Name = “n_lv_33_mm” NM0 (D G S B) n_lv_33_mm w=2u l=500.0n as=1.28e-12 ad=1.28e-12 ps=5.28u \

pd=5.28u m=(1)*(1)

HspiceS Netlist

HspiceS Model Name = “N_LV_33_MM” MNM0 D G S B N_LV_33_MM L=500E-9 W=2E-6 AD=1.28E-12 AS=1.28E-12

PD=5.28E-6 PS=5.28E-6 M=+1.00000000E+00

DIVA LVS Netlist

DIVA Device Name = “N_LV_33_MM” ; N_LV_33_MM Instance /NM0 = auLvs device M0

d N_LV_33_MM D G S B (p D S)

i 0 N_LV_33_MM D G S B " L 500e-9 W 2e-6 M 1.0 "

CDL Netlist

CDL Device Name = “N_LV_33_MM” MMN0 D G S B N_LV_33_MM W=2u L=500.0n M=1


UMC Confidential

Ver. B04_PB 97

Assura Netlist

Assura auLvs Device Name = “N_LV_33_MM”

C N_LV_33_MM MOS DRAIN B GATE B SOURCE B SUBSTRATE B ;;

* 4 pins

* 4 nets

* 0 instances i MN0 N_LV_33_MM D G S B ; W 2e-06 effW 2e-06 L 5e-07;


UMC Confidential

Ver. B04_PB 98

N_LV_33_MM (diagrammatic layout)


NPLUS

PO1

CONT

VTNHL

TG

ME1

SYMBOL (MMSYMBOL)

Device Derivation

Device Layer Derivation Recognition DIFF AND NPLUS AND TG AND VTNHL

CONTAINS PO1

G PO1

D DIFF AND NPLUS AND TG AND VTNHL NOT PO1

S DIFF AND NPLUS AND TG AND VTNHL NOT PO1

B Substrate

Width

Length


UMC Confidential

Ver. B04_PB 99

LVS Comparison


Width PO1 inside DIFF (illustrated above) * S and D are PERMUTABLE


UMC Confidential

Ver. B04_PB 100

24.8 P_LV_33_MM – 3.3 volt low vt PMOS Transistor

Spectre Netlist Spectre Model Name = “p_lv_33_mm” PM0 (D G S B) p_lv_33_mm w=2u l=500.0n as=1.28e-12 ad=1.28e-12 ps=5.28u \

pd=5.28u m=(1)*(1)

HspiceS Netlist

HspiceS Model Name = “P_LV_33_MM” MPM0 D G S B P_LV_33_MM L=500E-9 W=2E-6 AD=1.28E-12 AS=1.28E-12

PD=5.28E-6 PS=5.28E-6 M=+1.00000000E+00

DIVA LVS Netlist

DIVA Device Name = “P_LV_33_MM” ; P_LV_33_MM Instance /PM0 = auLvs device M0

d P_LV_33_MM D G S B (p D S)

I 0 P_LV_33_MM D G S B " L 500e-9 W 2e-6 M 1.0 "

CDL Netlist

CDL Device Name = “P_LV_33_MM” MPM0 D G S B P_LV_33_MM W=2u L=500.0n M=1


UMC Confidential

Ver. B04_PB 101

Assura Netlist

Assura auLvs Device Name = “P_LV_33_MM”

c P_LV_33_MM MOS DRAIN B GATE B SOURCE B SUBSTRATE B ;;

* 4 pins

* 4 nets

* 0 instances i MP0 P_LV_33_MM D G S B ; effW 2e-06 L 5e-07 W 2e-06;


UMC Confidential

Ver. B04_PB 102

P_LV_33_MM (diagrammatic layout)


DIFF

PPLUS

VTPHL

TG

PO1

CONT

ME1

SYMBOL (MMSYMBOL)

Device Derivation

Device Layer Derivation Recognition NWEL AND DIFF AND PPLUS AND TG AND

VTPHL CONTAINS PO1

G PO1

D NWEL AND DIFF AND PPLUS AND TG AND VTPHL NOT PO1

S NWEL AND DIFF AND PPLUS AND TG AND VTPHL NOT PO1

B NWEL

Width

Length


UMC Confidential

Ver. B04_PB 103

LVS Comparison





UMC Confidential

Ver. B04_PB 104

24.9 N_ZERO_18_MM – 1.8 volt zero vt NMOS transistor

Spectre Netlist Spectre Model Name = “n_zero_18_mm” NM0 (D G S B) n_zero_18_mm w=2u l=300.0n as=9.8e-13 ad=9.8e-13 ps=4.98u \

pd=4.98u m=(1)*(1)

HspiceS Netlist

HspiceS Model Name = “N_ZERO_18_MM” MNM0 D G S B N_ZERO_18_MM L=300E-9 W=2E-6 AD=980E-15 AS=980E-15

PD=4.98E-6 PS=4.98E-6 M=+1.00000000E+00

DIVA LVS Netlist

DIVA Device Name = “N_ZERO_18_MM” ; N_ZERO_18_MM Instance /NM0 = auLvs device M0

d N_ZERO_18_MM D G S B (p D S)

i 0 N_ZERO_18_MM D G S B " L 300e-9 W 2e-6 M 1.0 "

CDL Netlist

CDL Device Name = “N_ZERO_18_MM” MMN0 D G S B N_ZERO_18_MM W=2u L=300.0n M=1


UMC Confidential

Ver. B04_PB 105

Assura Netlist

Assura auLvs Device Name = “N_ZERO_18_MM”

C N_ZERO_18_MM MOS DRAIN B GATE B SOURCE B SUBSTRATE B ;;

* 4 pins

* 4 nets

* 0 instances i MN0 N_ZERO_18_MM D G S B ; W 2e-06 effW 2e-06 L 3e-07;


UMC Confidential

Ver. B04_PB 106

N_ZERO_18_MM (diagrammatic layout)


NPLUS

PO1

CONT

VTNI

ME1

SYMBOL ( MMSYMBOL)

Device Derivation

Device Layer Derivation Recognition DIFF AND NPLUS AND VTNI CONTAINS PO1

G PO1

D DIFF AND NPLUS AND VTNI NOT PO1

S DIFF AND NPLUS AND VTNI NOT PO1

B Substrate

LVS Comparison



Width

Length


UMC Confidential

Ver. B04_PB 107

• PLUS and MINUS are PERMUTABLE

24.10 N_ZERO_33_MM – 3.3 volt zero vt NMOS Transistor

Spectre Netlist Spectre Model Name = “n_zero_33_mm” NM0 (D G S B) n_zero_33_mm w=2u l=500.0n as=1.28e-12 ad=1.28e-12 ps=5.28u \

pd=5.28u m=(1)*(1)

HspiceS Netlist

HspiceS Model Name = “N_ZERO_33_MM” MNM0 D G S B N_ZERO_33_MM L=500E-9 W=2E-6 AD=1.28E-12 AS=1.28E-12

PD=5.28E-6 PS=5.28E-6 M=+1.00000000E+00

DIVA LVS Netlist

DIVA Device Name = “N_ZERO_33_MM” ; N_ZERO_33_MM Instance /NM0 = auLvs device M0

d N_ZERO_33_MM D G S B (p D S)

i 0 N_ZERO_33_MM D G S B " L 500e-9 W 2e-6 M 1.0 "

CDL Netlist

CDL Device Name = “N_ZERO_33_MM” MMN0 D G S B N_ZERO_33_MM W=2u L=500.0n M=1


UMC Confidential

Ver. B04_PB 108

Assura Netlist

Assura auLvs Device Name = “N_ZERO_33_MM”

C N_ZERO_33_MM MOS DRAIN B GATE B SOURCE B SUBSTRATE B ;;

* 4 pins

* 4 nets

* 0 instances i MN0 N_ZERO_33_MM D G S B ; W 2e-06 effW 2e-06 L 5e-07;


UMC Confidential

Ver. B04_PB 109

N_ZERO_33_MM (diagrammatic layout)


NPLUS

PO1

CONT

VT (VTNL)

TG

ME1

SYMBOL (MMSYMBOL)

Device Derivation

Device Layer Derivation Recognition DIFF AND NPLUS AND TG AND VTNL

CONTAINS PO1

G PO1

D DIFF AND NPLUS AND TG AND VTNL NOT PO1

S DIFF AND NPLUS AND TG AND VTNL NOT PO1

B Substrate

Width

Length


UMC Confidential

Ver. B04_PB 110

LVS Comparison




UMC Confidential

Ver. B04_PB 111

24.11 N_BPW_18_MM – 1.8 volt triple-well NMOS Transistor

Spectre Netlist Spectre Model Name = “n_bpw_18_mm” NM0 (D G S B) n_bpw_18_mm w=2u l=180.0n as=9.8e-13 ad=9.8e-13 ps=4.98u \

pd=4.98u m=(1)*(1)

HspiceS Netlist

HspiceS Model Name = “N_BPW_18_MM” MNM0 D G S B N_BPW_18_MM L=180E-9 W=2E-6 AD=980E-15 AS=980E-15

PD=4.98E-6 PS=4.98E-6 M=+1.00000000E+00

DIVA LVS Netlist

DIVA Device Name = “N_BPW_18_MM” ; N_BPW_18_MM Instance /NM0 = auLvs device M0

d N_BPW_18_MM D G S B (p D S)

i 0 N_BPW_18_MM D G S B " L 180e-9 W 2e-6 M 1.0 "

CDL Netlist

CDL Device Name = “N_BPW_18_MM” MMN0 D G S B N_BPW_18_MM W=2u L=180.0n M=1


UMC Confidential

Ver. B04_PB 112

Assura Netlist

Assura auLvs Device Name = “N_BPW_18_MM”

C N_BPW_18_MM MOS DRAIN B GATE B SOURCE B SUBSTRATE B ;;

* 4 pins

* 4 nets

* 0 instances i MN0 N_BPW_18_MM D G S B ; W 2e-06 effW 2e-06 L 1.8e-07;


UMC Confidential

Ver. B04_PB 113

N_BPW_18_MM (diagrammatic layout)


DIFF

NPLUS

PO1

CONT

TWEL

ME1

SYMBOL ( MMSYMBOL)

Device Derivation

Device Layer Derivation Recognition DIFF AND NPLUS AND TWEL CONTAINS PO1

G PO1

D DIFF AND NPLUS AND TWEL NOT PO1

S DIFF AND NPLUS AND TWEL NOT PO1

B TWEL

LVS Comparison



Width

Length


UMC Confidential

Ver. B04_PB 114



UMC Confidential

Ver. B04_PB 115

24.12 N_BPW_33_MM – 3.3 volt triple-well NMOS Transistor

Spectre Netlist Spectre Model Name = “n_bpw_33_mm” NM0 (D G S B) n_bpw_33_mm w=2u l=340.0n as=1.28e-12 ad=1.28e-12 ps=5.28u \

pd=5.28u m=(1)*(1)

HspiceS Netlist

HspiceS Model Name = “N_BPW_33_MM” MNM0 D G S B N_BPW_33_MM L=340E-9 W=2E-6 AD=1.28E-12 AS=1.28E-12

PD=5.28E-6 PS=5.28E-6 M=+1.00000000E+00

DIVA LVS Netlist

DIVA Device Name = “N_BPW_33_MM” ; N_BPW_33_MM Instance /NM0 = auLvs device M0

d N_BPW_33_MM D G S B (p D S)

i 0 N_BPW_33_MM D G S B " L 340e-9 W 2e-6 M 1.0 "

CDL Netlist

CDL Device Name = “N_BPW_33_MM” MMN0 D G S B N_BPW_33_MM W=2u L=340.0n M=1


UMC Confidential

Ver. B04_PB 116

Assura Netlist

Assura auLvs Device Name = “N_BPW_33_MM”

C N_BPW_33_MM MOS DRAIN B GATE B SOURCE B SUBSTRATE B ;;

* 4 pins

* 4 nets

* 0 instances i MN0 N_BPW_33_MM D G S B ; W 2e-06 effW 2e-06 L 3.4e-07;


UMC Confidential

Ver. B04_PB 117

N_BPW_33_MM (diagrammatic layout)


DIFF

NPLUS

PO1

CONT

TWEL

TG

ME1

SYMBOL (MMSYMBOL)

Device Derivation

Device Layer Derivation Recognition DIFF AND NPLUS AND TG AND TWEL

CONTAINS PO1

G PO1

D DIFF AND NPLUS AND TG AND TWEL NOT PO1

S DIFF AND NPLUS AND TG AND TWEL NOT PO1

B TWEL

Width

Length


UMC Confidential

Ver. B04_PB 118

LVS Comparison




UMC Confidential

Ver. B04_PB 119

24.13 RSPD_MM – P+ diffused resistor w/ salicide

NOTE: Dog-bone configurations are permitted. NOTE:

If: 0.24um <= width <= 0.43um then 0.48um <= length <=1000um Else if: 0.43um < width <=20um then 0.42um <= length <=1000um

Spectre Netlist Spectre Model Name = “rspd_mm” R0 (PLUS MINUS B) rspd_mm lr=9.32u wr=440.0n

HspiceS Netlist

HspiceS Model Name = “RSPD_MM” XR0 PLUS MINUS B RSPD_MM LR=9.32E-6 WR=440E-9

DIVA LVS Netlist

DIVA Device Name = “RSPD_MM” ; RSPD_MM Instance /R0 = auLvs device R0

d RSPD_MM PLUS MINUS B (p PLUS MINUS)


UMC Confidential

Ver. B04_PB 120

i 0 RSPD_MM PLUS MINUS B " R 169.455 L 9.32e-6 W 440e-9 "

CDL Netlist CDL Device Name = “RSPD_MM” RR0 PLUS MINUS 169.455 $SUB=B $[RSPD_MM] $W=440.0n $L=9.32u

Assura Netlist

Assura auLvs Device Name = “RSPD_MM”

c RSPD_MM RES IN B OUT B SUBSTRATE B ;;

* 3 pins

* 3 nets

* 0 instances i R0 RSPD_MM PLUS MINUS B; L 9.32e-06 lSim 9.32e-06 lTot 9.32e-06 W 4.4e-07 wSim 4.4e-07 R 169.455;


UMC Confidential

Ver. B04_PB 121

RSPD_MM (diagrammatic layout)


PPLUS

RSYMBOL

CONT

ME1

SYMBOL (MMSYMBOL)

NWEL

Device Derivation

Device Layer Derivation Recognition DIFF AND PPLUS AND RSYMBOL

PLUS DIFF NOT RSYMBOL

MINUS DIFF NOT RSYMBOL

B NWEL

LVS Comparison

Parameter Calculation Length CONT to CONT (illustrated above)

Width DIFF Width (illustrated above)


Length

Width


UMC Confidential

Ver. B04_PB 122

24.14 RSND_MM – N+ diffused resistor w/ salicide

NOTE: Dog-bone configurations are permitted. NOTE:

If: 0.24um <= width <= 0.43um then 0.48um <= length <=1000um Else if: 0.43um < width <=20um then 0.42um <= length <=1000um

Spectre Netlist

Spectre Model Name = “rsnd_mm” R0 (PLUS MINUS B) rsnd_mm lr=9.32u wr=440.0n

HspiceS Netlist

HspiceS Model Name = “RSND_MM” XR0 PLUS MINUS B RSND_MM LR=9.32E-6 WR=440E-9

DIVA LVS Netlist

DIVA Device Name = “RSND_MM” ; RSND_MM Instance /R0 = auLvs device R0

d RSND PLUS MINUS B (p PLUS MINUS)


UMC Confidential

Ver. B04_PB 123

i 0 RSND_MM PLUS MINUS B " R 169.455 L 9.32e-6 W 440e-9 "

CDL Netlist CDL Device Name = “RSND_MM” RR0 PLUS MINUS 169.455 $SUB=B $[RSND_MM] $W=440.0n $L=9.32u

Assura Netlist

Assura auLvs Device Name = “RSND_MM”

c RSND_MM RES IN B OUT B SUBSTRATE B ;;

* 3 pins

* 3 nets

* 0 instances i R0 RSND_MM PLUS MINUS B; R 169.455 L 9.32e-06 lSim 9.32e-06 lTot 9.32e-06 W 4.4e-07 wSim 4.4e-07 ;


UMC Confidential

Ver. B04_PB 124

RSND_MM (diagrammatic layout)


NPLUS

RSYMBOL

CONT

ME1

SYMBOL (MMSYMBOL)

Device Derivation

Device Layer Derivation Recognition DIFF AND NPLUS AND RSYMBOL



B Substrate

LVS Comparison

Parameter Calculation Length CONT to CONT (illustrated above)



Length

Width


UMC Confidential

Ver. B04_PB 125

24.15 RNPPO_MM – P+ Poly resistor w/o salicide

Spectre Netlist Spectre Model Name = “rnppo_mm” R0 (PLUS MINUS B) rnppo_mm lr=8.32u wr=440.0n

HspiceS Netlist

HspiceS Model Name = “RNPPO_MM” XR0 PLUS MINUS B RNPPO_MM LR=8.32E-6 WR=440E-9

DIVA LVS Netlist

DIVA Device Name = “RNPPO_MM” ; RNPPO_MM Instance /R0 = auLvs device R0

d RNPPO_MM PLUS MINUS B (p PLUS MINUS)

i 0 RNPPO_MM PLUS MINUS B " R 7.96609e3 L 8.32e-6 W 440e-9 "

CDL Netlist

CDL Device Name = “RNPPO_MM”


UMC Confidential

Ver. B04_PB 126

RR0 PLUS MINUS 7.96609K $SUB=B $[RNPPO_MM] $W=440.0n $L=8.32u

Assura Netlist

Assura auLvs Device Name = “RNPPO_MM”

c RNPPO_MM RES IN B OUT B SUBSTRATE B ;;

* 3 pins

* 3 nets

* 0 instances i R0 RNPPO_MM PLUS MINUS B; R 7.96609e3 L 8.32e-06 lSim 8.32e-06 lTot 8.32e-06 W 4.4e-07 wSim 4.4e-07 ;


UMC Confidential

Ver. B04_PB 127

RNPPO_MM (diagrammatic layout)

Device Layers Layer Color and Fill PO1

PPLUS

PSYMBOL

CONT

ME1

SYMBOL (MMSYMBOL)

NWEL

SAB

Device Derivation

Device Layer Derivation Recognition PO1 AND PPLUS AND PSYMBOL AND

SAB

PLUS PO1 NOT PSYMBOL

MINUS PO1 NOT PSYMBOL

B NWEL

LVS Comparison

Parameter Calculation Length SAB length (illustrated above)

Width PO1 Width (illustrated above)

Length

Width


UMC Confidential

Ver. B04_PB 128


24.16 RNNPO_MM – N+ Poly resistor w/o salicide

Spectre Netlist Spectre Model Name = “rnnpo_mm” R0 (PLUS MINUS B) rnnpo_mm lr=8.32u wr=440.0n

HspiceS Netlist

HspiceS Model Name = “RNNPO_MM” XR0 PLUS MINUS B RNNPO_MM LR=8.32E-6 WR=440E-9

DIVA LVS Netlist

DIVA Device Name = “RNNPO_MM” ; RNNPO_MM Instance /R0 = auLvs device R0

d RNNPO_MM PLUS MINUS B (p PLUS MINUS)

i 0 RNNPO_MM PLUS MINUS B " R 2.84012e3 L 8.32e-6 W 440e-9 "

CDL Netlist

CDL Device Name = “RNNPO_MM”


UMC Confidential

Ver. B04_PB 129

RR0 PLUS MINUS 2.84012K $SUB=B $[RNNPO_MM] $W=440.0n $L=8.32u

Assura Netlist

Assura auLvs Device Name = “RNNPO_MM”

c RNNPO_MM RES IN B OUT B SUBSTRATE B ;;

* 3 pins

* 3 nets

* 0 instances i R0 RNNPO_MM PLUS MINUS B; R 2.84012e3 L 8.32e-06 lSim 8.32e-06 lTot 8.32e-06 W 4.4e-07 wSim 4.4e-07 ;


UMC Confidential

Ver. B04_PB 130

RNNPO_MM (diagrammatic layout)

Device Layers Layer Color and Fill PO1

NPLUS

PSYMBOL

CONT

ME1

SYMBOL (MMSYMBOL)

SAB

Device Derivation

Device Layer Derivation Recognition PO1 AND NPLUS AND PSYMBOL AND

SAB



B Substrate

LVS Comparison


Width PO1 Width (illustrated above)


Length

Width


UMC Confidential

Ver. B04_PB 131

24.17 RSNWELL_MM – N-Well Resistor

Spectre Netlist Spectre Model Name = “rsnwell_mm” R0 (PLUS MINUS B) rsnwell_mm lr=8.64u wr=1.5u

HspiceS Netlist

HspiceS Model Name = “RSNWELL_MM” XR0 PLUS MINUS B RSNWELL_MM LR=8.64E-6 WR=1.5E-6

DIVA LVS Netlist

DIVA Device Name = “RSNWELL_MM” ; RSNWELL_MM Instance /R0 = auLvs device R0

d RSNWELL_MM PLUS MINUS B (p PLUS MINUS)

i 0 RSNWELL_MM PLUS MINUS B " R 3.03864e3 L 8.64e-6 W 1.5e-6 "

CDL Netlist

CDL Device Name = “RSNWELL_MM”


UMC Confidential

Ver. B04_PB 132

RR0 PLUS MINUS 3.03864K $SUB=B $[RSNWELL_MM] $W=1.5u $L=8.64u

Assura Netlist

Assura auLvs Device Name = “RSNWELL_MM”

c RSNWELL_MM RES IN B OUT B SUBSTRATE B ;;

* 3 pins

* 3 nets

* 0 instances i R0 RSNWELL_MM PLUS MINUS B; R 3.03864e3 L 8.64e-06 lSim 8.16e-06 lTot 8.64e-06 W 1.5e-06 wSim 1.5e-06 ;


UMC Confidential

Ver. B04_PB 133

RSNWELL_MM (diagrammatic layout)


NPLUS

NWR

CONT

ME1

SYMBOL (MMSYMBOL)

NWEL

Device Derivation

Device Layer Derivation Recognition NWEL AND NPLUS AND NWR

PLUS NWEL NOT NWR

MINUS NWEL NOT NWR

B Substrate

LVS Comparison

Parameter Calculation Length DIFF to DIFF (illustrated above)

Width NWEL Width (illustrated above)


Length

Width


UMC Confidential

Ver. B04_PB 134

24.18 RNHR1000_MM – High Resistive Poly Resistor

Spectre Netlist Spectre Model Name = “rnhr1000_mm” R0 (PLUS MINUS B) rnhr1000_mm lr=8.32u wr=440.0n

HspiceS Netlist

HspiceS Model Name = “RNHR1000_MM” XR0 PLUS MINUS B RNHR1000_MM LR=8.32E-6 WR=440E-9

DIVA LVS Netlist

DIVA Device Name = “RNHR1000_MM” ; RNHR1000_MM Instance /R0 = auLvs device R0

d RNHR1000_MM PLUS MINUS B (p PLUS MINUS)

i 0 RNHR1000_MM PLUS MINUS B " R 21.3322e3 L 8.32e-6 W 440e-9 "

CDL Netlist

CDL Device Name = “RNHR1000_MM” RR0 PLUS MINUS 21.3322K $SUB=B $[RNHR1000_MM] $W=440e-9 $L=8.32u


UMC Confidential

Ver. B04_PB 135

Assura Netlist

Assura auLvs Device Name = “RNHR1000_MM”

c RNHR1000_MM RES IN B OUT B SUBSTRATE B ;;

* 3 pins

* 3 nets

* 0 instances i R0 RNHR1000_MM PLUS MINUS B; R 21.3322e3 L 8.32e-06 lSim 8.32e-06 lTot 8.32e-06 W 4.4e-07 wSim 4.4e-09 ;


UMC Confidential

Ver. B04_PB 136

RNHR1000_MM (diagrammatic layout)

Device Layers Layer Color and Fill PPLUS

HR

PSYMBOL

CONT

ME1

SYMBOL (MMSYMBOL)

PO1

NWEL

SAB

Device Derivation

Device Layer Derivation Recognition PO1 AND HR AND PSYMBOL AND SAB



B NWEL

LVS Comparison


Width PO1 Width (illustrated above) * PLUS and MINUS are PERMUTABLE

Length

Width


UMC Confidential

Ver. B04_PB 137

24.19 RNND_MM – N+ diffused Resistor w/o salicide

Spectre Netlist Spectre Model Name = “rnnd_mm” R0 (PLUS MINUS B) rnnd_mm lr=8.56u wr=440.0n

HspiceS Netlist

HspiceS Model Name = “RNND_MM” XR0 PLUS MINUS B RNND_MM LR=8.56E-6 WR=440E-9

DIVA LVS Netlist

DIVA Device Name = “RNND_MM” ; RNND_MM Instance /R0 = auLvs device R0

d RNND_MM PLUS MINUS B (p PLUS MINUS)

i 0 RNND_MM PLUS MINUS B " R 1.34936e3 L 8.56e-6 W 440e-9 "

CDL Netlist

CDL Device Name = “RNND_MM” RR0 PLUS MINUS 1.34936K $SUB=B $[RNND_MM] $W=440e-9 $L=8.56u


UMC Confidential

Ver. B04_PB 138

Assura Netlist

Assura auLvs Device Name = “RNND_MM”

c RNND_MM RES IN B OUT B SUBSTRATE B ;;

* 3 pins

* 3 nets

* 0 instances i R0 RNND_MM PLUS MINUS B; R 1.34936e3 L 8.56e-06 lSim 8.56e-06 lTot 8.56e-06 W 4.4e-07 wSim 4.4e-09 ;


UMC Confidential

Ver. B04_PB 139

RNND_MM (diagrammatic layout)

Device Layers Layer Color and Fill SAB

NPLUS

DIFF

CONT

ME1

SYMBOL (MMSYMBOL)

RSYMBOL

Device Derivation

Device Layer Derivation Recognition NPLUS AND DIFF AND RSYMBOL AND

SAB



B Substrate

LVS Comparison




Length

Width


UMC Confidential

Ver. B04_PB 140

24.20 RNPD_MM – P+ diffused Resistor w/o salicide

Spectre Netlist Spectre Model Name = “rnpd_mm” R0 (PLUS MINUS B) rnpd_mm lr=8.56u wr=440.0n

HspiceS Netlist

HspiceS Model Name = “RNPD_MM” XR0 PLUS MINUS B RNPD_MM LR=8.56E-6 WR=440E-9

DIVA LVS Netlist

DIVA Device Name = “RNPD_MM” ; RNPD_MM Instance /R0 = auLvs device R0

d RNPD_MM PLUS MINUS B (p PLUS MINUS)

i 0 RNPD_MM PLUS MINUS B " R 2.5771e3 L 8.56e-6 W 440e-9 "

CDL Netlist

CDL Device Name = “RNPD_MM” RR0 PLUS MINUS 2.5771K $SUB=B $[RNPD_MM] $W=440e-9 $L=8.56u


UMC Confidential

Ver. B04_PB 141

Assura Netlist

Assura auLvs Device Name = “RNPD_MM”

c RNPD_MM RES IN B OUT B SUBSTRATE B ;;

* 3 pins

* 3 nets

* 0 instances i R0 RNPD_MM PLUS MINUS B; R 2.5771e3 L 8.56e-06 lSim 8.56e-06 lTot 8.56e-06 W 4.4e-07 wSim 4.4e-09 ;


UMC Confidential

Ver. B04_PB 142

RNPD_MM (diagrammatic layout)

Device Layers Layer Color and Fill SAB

PPLUS

DIFF

NWEL

CONT

ME1

SYMBOL (MMSYMBOL)

RSYMBOL

Device Derivation

Device Layer Derivation Recognition PPLUS AND DIFF AND RSYMBOL AND

SAB



B NWEL

LVS Comparison



Length

Width


UMC Confidential

Ver. B04_PB 143


24.21 RM1_MM – Metal 1 Resistor

Spectre Netlist

Spectre Model Name = “rm1_mm” R0 (PLUS MINUS) rm1_mm lr=740.0n wr=420.0n

HspiceS Netlist

HspiceS Model Name = “RM1_MM” XR0 PLUS MINUS RM1_MM LR=740E-9 WR=420E-9

DIVA LVS Netlist

DIVA Device Name = “RM1_MM” ; RM1_MM Instance /R0 = auLvs device R0

d RM1_MM PLUS MINUS (p PLUS MINUS)

i 0 RM1_MM PLUS MINUS " R 135.667e-3 L 740e-9 W 420e-9 "

CDL Netlist

CDL Device Name = “RM1_ MM” RR0 PLUS MINUS 135.667m $[RM1_MM] $W=420.0n $L=740.0n


UMC Confidential

Ver. B04_PB 144

Assura Netlist

Assura auLvs Device Name = “RM1_MM”

c RM1_MM RES IN B OUT B;;

* 2 pins

* 2 nets

* 0 instances i R0 RM1_ MM PLUS MINUS; L 7.40e-07 W 4.2e-07 R 0.135667;


UMC Confidential

Ver. B04_PB 145

RM1_MM (diagrammatic layout)

Device Layers Layer Color and Fill ME1

M1_CAD (Resistor_Mark)

Device Derivation

Device Layer Derivation Recognition ME1 AND M1_CAD (Resistor_Mark)

PLUS ME1

MINUS ME1

LVS Comparison

Parameter Calculation Length M1_CAD (Resistor_Mark) length

(illustrated above)

Width M1_CAD (Resistor_Mark) Width (illustrated above)


width

length


UMC Confidential

Ver. B04_PB 146


Spectre Netlist


HspiceS Netlist


DIVA LVS Netlist




CDL Netlist

CDL Device Name = “RM2_MM” RR0 PLUS MINUS 98.6363m $[RM2_MM] $W=440.0n $L=700.0n


UMC Confidential

Ver. B04_PB 147

Assura Netlist



* 2 pins

* 2 nets

* 0 instances i R0 RM2_MM PLUS MINUS; L 7.00e-07 W 4.4e-07 R 0.00986363;


UMC Confidential

Ver. B04_PB 148




Device Derivation


PLUS ME2

MINUS ME2

LVS Comparison


(illustrated above)



width

length


UMC Confidential

Ver. B04_PB 149


Spectre Netlist


HspiceS Netlist


DIVA LVS Netlist




CDL Netlist



UMC Confidential

Ver. B04_PB 150

Assura Netlist



* 2 pins

* 2 nets



UMC Confidential

Ver. B04_PB 151




Device Derivation


PLUS ME3

MINUS ME3

LVS Comparison


(illustrated above)



width

length


UMC Confidential

Ver. B04_PB 152


Spectre Netlist


HspiceS Netlist


DIVA LVS Netlist



i 0 RM4_MM PLUS MINUS " R 98.6363m L 700e-9 W 440e-9 "

CDL Netlist



UMC Confidential

Ver. B04_PB 153

Assura Netlist



* 2 pins

* 2 nets



UMC Confidential

Ver. B04_PB 154




Device Derivation


PLUS ME4

MINUS ME4

LVS Comparison


(illustrated above)



width

length


UMC Confidential

Ver. B04_PB 155


Spectre Netlist


HspiceS Netlist


DIVA LVS Netlist




CDL Netlist



UMC Confidential

Ver. B04_PB 156

Assura Netlist



* 2 pins

* 2 nets



UMC Confidential

Ver. B04_PB 157




Device Derivation


PLUS ME5

MINUS ME5

LVS Comparison


(illustrated above)

Width M5_CAD (Resistor_Mark) (illustrated above)


width

length


UMC Confidential

Ver. B04_PB 158

24.26 RM6_MM – Metal 6 Resistor (20KA)

Spectre Netlist

Spectre Model Name = “rm6_mm” R0 (PLUS MINUS) rm6_mm lr=7.5u wr=1.2u

HspiceS Netlist

HspiceS Model Name = “RM6_MM” XR0 PLUS MINUS RM6_MM LR=7.5E-6 WR=1.2E-6

DIVA LVS Netlist



i 0 RM6_MM PLUS MINUS " R 125.000e-3 L 7.5e-6 W 1.2e-6 "

CDL Netlist

CDL Device Name = “RM6_MM” RR0 PLUS MINUS 125.000m $[RM6_MM] $W=1.2u $L=7.5u


UMC Confidential

Ver. B04_PB 159

Assura Netlist



* 2 pins

* 2 nets



UMC Confidential

Ver. B04_PB 160




Device Derivation


PLUS ME6

MINUS ME6

LVS Comparison


(illustrated above)



width

length


UMC Confidential

Ver. B04_PB 161

24.27 NCAP_MM – NMOS Transistor configured as a

Capacitor

Spectre Netlist

Spectre Model Name = “n_18_mm” C0 (D G S B) n_18_mm w=10u l=10u as=4.9e-12 ad=4.9e-12 ps=20.98u pd=20.98u m=(1)*(1)

HspiceS Netlist

HspiceS Model Name = “N_18_MM” MC0 D G S B N_18_MM W=10E-6 L=10E-6 AS=4.9E-12 PD=20.98E-6

+PS=20.98E-6 M=+1.000000000E+00

DIVA LVS Netlist

DIVA Device Name = “NCAP_MM” ; NCAP_MM Instance /C0 = auLvs device C0

d N_18_MM D G S B

i 0 N_18_MM D G S B" M 1.0 L 10e-6 W 10e-6 "

CDL Netlist

CDL Device Name = “N_18_MM”


UMC Confidential

Ver. B04_PB 162

MC0 D G S B N_18_MM W=10u L=10u M=1

Assura Netlist

Assura auLvs Device Name = “NCAP_MM”

c NCAP_MM CAP DRAIN B GATE B SOURCE B SUBSTRATE B ;;

* 3 pins

* 3 nets

* 0 instances i C0 N_18_MM D G S B ; np 4e-05 W 1e-05 effW 1e-05 c 8.28336e-13 L 1e-05 na 1e-10;


UMC Confidential

Ver. B04_PB 163

NCAP_MM (diagrammatic layout)

Device Layers Layer Color and Fill SYMBOL (CSYMBOL)

DIFF

NPLUS

PO1

CONT

ME1

SYMBOL (MMSYMBOL)

Device Derivation

Device Layer Derivation Recognition CSYMBOL AND DIFF AND NPLUS CONTAINS

PO1

TOP PO1

BOT CSYMBOL AND DIFF AND NPLUS NOT PO1

B Substrate

LVS Comparison



Width

Length


UMC Confidential

Ver. B04_PB 164

24.28 PCAP_MM – PMOS Transistor configured as a Capacitor

Spectre Netlist Spectre Model Name = “p_18_mm” C0 (D G S B) p_18_mm w=10u l=10u as=4.9e-12 ad=4.9e-12 ps=20.98u pd=20.98u m=(1)*(1)

HspiceS Netlist

HspiceS Model Name = “P_18_MM” MC0 D G S B P_18_MM W=10E-6 L=10E-6 AS=4.9E-12 PD=20.98E-6

+PS=20.98E-6 M=+1.000000000E+00

DIVA LVS Netlist

DIVA Device Name = “PCAP_MM” ; PCAP_MM Instance /C0 = auLvs device C0

d P_18_MM D G S B

i 0 P_18_MM D G S B" M 1.0 L 10e-6 W 10e-6 "

CDL Netlist

CDL Device Name = “P_18_MM”


UMC Confidential

Ver. B04_PB 165

MC0 D G S B P_18_MM W=10u L=10u M=1

Assura Netlist

Assura auLvs Device Name = “PCAP_MM”

c PCAP_MM CAP DRAIN B GATE B SOURCE B SUBSTRATE B ;;

* 3 pins

* 3 nets

* 0 instances i C0 P_18_MM D G S B ; np 4e-05 W 1e-05 effW 1e-05 c 8.28336e-13 L 1e-05 na 1e-10;


UMC Confidential

Ver. B04_PB 166

PCAP_MM (diagrammatic layout)

Device Layers Layer Color and Fill SYMBOL (CSYMBOL)

DIFF

PPLUS

PO1

CONT

ME1

SYMBOL (MMSYMBOL)

NWEL

Device Derivation

Device Layer Derivation Recognition CSYMBOL AND DIFF AND PPLUS CONTAINS

PO1

TOP PO1

BOT CSYMBOL AND DIFF AND PPLUS NOT PO1

B NWEL

LVS Comparison



Width

Length


UMC Confidential

Ver. B04_PB 167

24.29 MIMCAPS_MM – Single-squared Mixed-Mode Metal

Capacitor

Spectre Netlist

Spectre Model Name = “mimcaps_mm” C0 (PLUS MINUS) mimcaps_mm w=10u l=10u m=1

HspiceS Netlist

HspiceS Model Name = “MIMCAPS_MM” XC0 PLUS MINUS MIMCAPS_MM W=10E-6 L=10E-6 M=1.0

DIVA LVS Netlist

DIVA Device Name = “MIMCAPS_MM” ; MIMCAPS_MM Instance /C0 = auLvs device C0

d MIMCAPS_MM PLUS MINUS

i 0 MIMCAPS_MM PLUS MINUS" l 10e-6 w 10e-6 M 1.0 C 103e-15 "

CDL Netlist

CDL Device Name = “MIMCAPS_MM” CC0 PLUS MINUS 103.00f $[MIMCAPS_MM]


UMC Confidential

Ver. B04_PB 168

Assura Netlist

Assura auLvs Device Name = “MIMCAPS_MM”

c MIMCAPS_MM CAP POS B MINUS B;;

* 2 pins

* 2 nets

* 0 instances i C0 MIMCAPS_MM PLUS MINUS ; w 1e-05 C 1.03e-13 l 1e-05;


UMC Confidential

Ver. B04_PB 169

MIMCAPS_MM (diagrammatic layout)

Device Layers Layer Color and Fill MMC

SYMBOL (CSYMBOL)

VI5

ME6

SYMBOL (MMSYMBOL)

ME5

Device Derivation

Device Layer Derivation Recognition CSYMBOL AND MMC

PLUS ME6 AND ME5 AND MMC

MINUS ME6 AND ME5 NOT MMC

LVS Comparison

Parameter Calculation Length MMC Length (illustrated above)

Width MMC Width (illustrated above)

Width

Length


UMC Confidential

Ver. B04_PB 170

24.30 PNP_V50X50_MM – CMOS vertical substrate PNP

(5x5)

Spectre Netlist Spectre Model Name = “pnp_v50x50_mm” Q0 (C B E) pnp_v50x50_mm m=1

HspiceS Netlist

HspiceS Model Name = “PNP_V50X50_MM” Q0 C B E PNP_V50X50_MM M=1.0

DIVA LVS Netlist

DIVA Device Name = “PNP_V50X50_MM” ; PNP_V50X50_MM Instance /Q0 = auLvs device Q0

d PNP_V50X50_MM C B E

i 0 PNP_V50X50_MM C B E" M 1.0 EA 25e-12"

CDL Netlist

CDL Device Name = “PNP_V50X50_MM” QQ0 C B E PNP_V50X50_MM M=1 $EA=2.5e-11


UMC Confidential

Ver. B04_PB 171

Assura Netlist

Assura auLvs Device Name = “PNP_V50X50_MM”

c PNP_V50X50_MM BJT COLLECTOR B BASE B EMITTER B ;;

* 3 pins

* 3 nets

* 0 instances i Q0 PNP_V50X50_MM C B E ; model “PNP_V50X50_MM” EA 2.5e-11;


UMC Confidential

Ver. B04_PB 172

PNP_V50X50_MM (diagrammatic layout)


ME1

CONT

NPLUS

PPLUS

NWEL

SYMBOL (MMSYMBOL)

SIZE (SIZE1)

SYMBOL (BJTSYMBOL)

Area

C

B

E


UMC Confidential

Ver. B04_PB 173

Device Derivation

Device Layer Derivation Recognition BJTSYMBOL AND SIZE1

C BJTSYMBOL AND PPLUS AND DIFF NOT NWEL

B BJTSYMBOL AND NPLUS AND DIFF AND NWEL

E BJTSYMBOL AND PPLUS AND DIFF AND NWEL

LVS Comparison

Parameter Calculation Area Area of DIFF emitter (illustrated above)


UMC Confidential

Ver. B04_PB 174

24.31 PNP_V100X100_MM – CMOS vertical substrate PNP (10x10)

Spectre Netlist

Spectre Model Name = “pnp_v100x100_mm” Q0 (C B E) pnp_v100x100_mm m=1

HspiceS Netlist

HspiceS Model Name = “PNP_V100X100_MM” Q0 C B E PNP_V100X100_MM M=1.0

DIVA LVS Netlist

DIVA Device Name = “PNP_V100X100_MM” ; PNP_V100X100_MM Instance /Q0 = auLvs device Q0

d PNP_V100X100_MM C B E

i 0 PNP_V100X100_MM C B E" M 1.0 EA 100e-12"

CDL Netlist

CDL Device Name = “PNP_V100X100_MM” QQ0 C B E PNP_V100X100_MM M=1 $EA=10e-11


UMC Confidential

Ver. B04_PB 175

Assura Netlist

Assura auLvs Device Name = “PNP_V100X100_MM”

c PNP_V100X100_MM BJT COLLECTOR B BASE B EMITTER B ;;

* 3 pins

* 3 nets

* 0 instances i Q0 PNP_V100X100_MM C B E ; model “PNP_V100X100_MM” EA 10e-11


UMC Confidential

Ver. B04_PB 176

PNP_V100X100_MM (diagrammatic layout)


ME1

CONT

NPLUS

PPLUS

NWEL

SYMBOL (MMSYMBOL)

SIZE (SIZE2)

SYMBOL (BJTSYMBOL)

Area

C

B

E


UMC Confidential

Ver. B04_PB 177

Device Derivation

Device Layer Derivation Recognition BJTSYMBOL AND SIZE2

C BJTSYMBOL AND PPLUS AND DIFF NOT NWEL

B BJTSYMBOL AND NPLUS AND DIFF AND NWEL

E BJTSYMBOL AND PPLUS AND DIFF AND NWEL

LVS Comparison

Parameter Calculation Area Area of DIFF emitter (illustrated above)


UMC Confidential

Ver. B04_PB 178

24.32 DION_MM – N+/psub diode

Spectre Netlist Spectre Model Name = “dion_mm” D0 (PLUS MINUS) dion_mm area=8e-09 pj=0.00036 m=1

HspiceS Netlist

HspiceS Model Name = “DION_MM” D0 PLUS MINUS DION_MM AREA=8E-9 PJ=360E-6 W=80E-6 L=100E-6 M=1.0

DIVA LVS Netlist

DIVA Device Name = “DION_MM” ; DION_MM Instance /D0 = auLvs device D0

d DION_MM PLUS MINUS

i 0 DION_MM PLUS MINUS" AREA 8e-9 PJ 360e-6 M 1.0"

CDL Netlist

CDL Device Name = “DION_MM” DD0 PLUS MINUS DION_MM 8e-09 0.00036


UMC Confidential

Ver. B04_PB 179

Assura Netlist

Assura auLvs Device Name = “DION_MM”

c DION_MM DIO POS B MINUS B ;;

* 2 pins

* 2 nets

* 0 instances i D0 DION_MM PLUS MINUS ; PJ 0.00036 AREA 8e-09;


UMC Confidential

Ver. B04_PB 180

DION_MM (diagrammatic layout)


ME1

CONT

NPLUS

PPLUS

SYMBOL (MMSYMBOL)

SYMBOL (DIOBLK)

Device Derivation

Device Layer Derivation Recognition (NPLUS AND DIFF) INTERACT MMSYMBOL

NOT INTERACT (PO1 OR RSYMBOL) NOT BJTSYMBOL

PLUS PPLUS AND DIFF

MINUS NPLUS AND DIFF

minus plus

Area


UMC Confidential

Ver. B04_PB 181

LVS Comparison

Parameter Calculation Area Area of DIFF MINUS (illustrated above)


UMC Confidential

Ver. B04_PB 182

24.33 DIONW_MM – Nwell/psub diode

Spectre Netlist Spectre Model Name = “dionw_mm” D0 (PLUS MINUS) dionw_mm area=9.72e-08 pj=0.00234 m=1

HspiceS Netlist

HspiceS Model Name = “DIONW_MM” D0 PLUS MINUS DIONW_MM AREA=9.72E-8 PJ=234E-5 W=90E-6 L=1080E-6 M=1.0

DIVA LVS Netlist

DIVA Device Name = “DIONW_MM” ; DIONW_MM Instance /D0 = auLvs device D0

d DIONW_MM PLUS MINUS

i 0 DIONW_MM PLUS MINUS" AREA 9.72e-8 PJ 234e-5 M 1.0"

CDL Netlist

CDL Device Name = “DIONW_MM” DD0 PLUS MINUS DIONW_MM 9.72e-08 0.00234


UMC Confidential

Ver. B04_PB 183

Assura Netlist

Assura auLvs Device Name = “DIONW_MM”

c DIONW_MM DIO POS B MINUS B ;;

* 2 pins

* 2 nets

* 0 instances i D0 DIONW_MM PLUS MINUS ; PJ 0.00234 AREA 9.72e-08;


UMC Confidential

Ver. B04_PB 184

DIONW_MM (diagrammatic layout)


ME1

CONT

NWELL

NPLUS

PPLUS

SYMBOL (MMSYMBOL)

SYMBOL (DIOBLK & DSYMBOL)

Device Derivation

Device Layer Derivation Recognition (NPLUS AND DIFF) INTERACT (NWELL AND

MMSYMBOL) NOT INTERACT (PO1 OR RSYMBOL) NOT BJTSYMBOL

PLUS PPLUS AND DIFF

minus plus

Area


UMC Confidential

Ver. B04_PB 185

MINUS NWELL AND NPLUS AND DIFF

LVS Comparison

Parameter Calculation Area Area of NWELL MINUS (illustrated above)


UMC Confidential

Ver. B04_PB 186

24.34 DIOP_MM – P+/nwell diode

Spectre Netlist Spectre Model Name = “diop_mm” D0 (PLUS MINUS) diop_mm area=8e-09 pj=0.00036 m=1

HspiceS Netlist

HspiceS Model Name = “DIOP_MM” D0 PLUS MINUS DIOP_MM AREA=8E-9 PJ=360E-6 W=80E-6 L=100E-6 M=1.0

DIVA LVS Netlist

DIVA Device Name = “DIOP_MM” ; DIOP_MM Instance /D0 = auLvs device D0

d DIOP_MM PLUS MINUS

i 0 DIOP_MM PLUS MINUS" AREA 8e-9 PJ 360e-6 M 1.0"

CDL Netlist

CDL Device Name = “DIOP_MM” DD0 PLUS MINUS DIOP_MM 8e-09 0.00036


UMC Confidential

Ver. B04_PB 187

Assura Netlist

Assura auLvs Device Name = “DIOP_MM”

c DIOP_MM DIO POS B MINUS B ;;

* 2 pins

* 2 nets

* 0 instances i D0 DIOP_MM PLUS MINUS ; PJ 0.00036 AREA 8e-09;


UMC Confidential

Ver. B04_PB 188

DIOP_MM (diagrammatic layout)

Device Layers

Layer Color and Fill DIFF

ME1

CONT

NPLUS

PPLUS

NWEL

SYMBOL (MMSYMBOL)

SYMBOL (DIOBLK)

Device Derivation

Device Layer Derivation Recognition (PPLUS AND DIFF AND NWEL) INTERACT

MMSYMBOL NOT INTERACT (PO1 OR RSYMBOL) NOT (BJTSYMBOL OR CSYMBOL)

PLUS PPLUS AND DIFF

MINUS NPLUS AND DIFF

minus plus

Area


UMC Confidential

Ver. B04_PB 189

LVS Comparison Parameter Calculation Area Area of DIFF PLUS (illustrated above)


UMC Confidential

Ver. B04_PB 190

24.35 N_L18W500_18_RF – 1.8 volt variable finger RF NMOS transistor

Spectre Netlist Spectre Model Name = “n_l18w500_18_rf” NM0 (D G S B) n_l18w500_18_rf nf=5

HspiceS Netlist

HspiceS Model Name = “N_L18W500_18_RF” XNM0 D G S B N_L18W500_18_RF NF=5.0

DIVA LVS Netlist

DIVA Device Name = “N_L18W500_18_RF” ; N_L18W500_18_RF Instance /NM0 = auLvs device M0

d N_L18W500_18_RF D G S B (p D S)

i 0 N_L18W500_18_RF D G S B " nf 5.0 L 180e-9 W 5e-6 M 5.0"

CDL Netlist

CDL Device Name = “N_L18W500_18_RF” MMN0 D G S B N_L18W500_18_RF W=5u L=180.0n M=5


UMC Confidential

Ver. B04_PB 191

Assura Netlist

Assura auLvs Device Name = “N_L18W500_18_RF”

C N_L18W500_18_RF MOS DRAIN B GATE B SOURCE B SUBSTRATE B ;;

* 4 pins

* 4 nets

* 0 instances i MN0 N_L18W500_18_RF D G S B ; L 1.8e-07 W 5e-06 Nf 5 ;


UMC Confidential

Ver. B04_PB 192

N_L18W500_18_RF (diagrammatic layout)


NPLUS

PPLUS, ME1, DIFF, CONT

PO1, ME4-ME5

CONT

ME1-ME2

ME3-ME4

ME4-ME5

ME5-ME6

ME6

SYMBOL (RFMOS_S)

Width

Length


UMC Confidential

Ver. B04_PB 193

SYMBOL (RFSYMBOL), SIZE(SIZE2)

Device Derivation

Device Layer Derivation Recognition DIFF AND NPLUS AND RFSYMBOL AND SIZE2

CONTAINS PO1

G PO1

D DIFF AND NPLUS NOT (PO1 OR RFMOS_S)

S DIFF AND NPLUS AND RFMOS_S NOT PO1

B Substrate

LVS Comparison




UMC Confidential

Ver. B04_PB 194

24.36 N_L34W500_33_RF – 3.3 volt variable finger RF NMOS transistor

Spectre Netlist Spectre Model Name = “n_l34w500_33_rf” NM0 (D G S B) n_l34w500_33_rf nf=5

HspiceS Netlist

HspiceS Model Name = “N_L34W500_33_RF” XNM0 D G S B N_L34W500_33_RF NF=5.0

DIVA LVS Netlist

DIVA Device Name = “N_L34W500_33_RF” ; N_L34W500_33_RF Instance /NM0 = auLvs device M0

d N_L34W500_33_RF D G S B (p D S)

i 0 N_L34W500_33_RF D G S B " nf 5.0 L 340e-9 W 5e-6 M 5.0"

CDL Netlist

CDL Device Name = “N_L34W500_33_RF” MMN0 D G S B N_L34W500_33_RF W=5u L=340.0n M=5


UMC Confidential

Ver. B04_PB 195

Assura Netlist

Assura auLvs Device Name = “N_L34W500_33_RF”

C N_L34W500_33_RF MOS DRAIN B GATE B SOURCE B SUBSTRATE B ;;

* 4 pins

* 4 nets

* 0 instances i MN0 N_L34W500_33_RF D G S B ; L 3.4e-07 W 5e-06 Nf 5 ;


UMC Confidential

Ver. B04_PB 196

N_L34W500_33_RF (diagrammatic layout)


NPLUS


PO1, ME4-ME5

CONT

ME1-ME2

ME3-ME4

ME4-ME5

ME5-ME6

ME6

Width

Length


UMC Confidential

Ver. B04_PB 197

TG

SYMBOL (RFMOS_S)


Device Derivation Device Layer Derivation Recognition DIFF AND NPLUS AND RFSYMBOL AND TG

AND SIZE2 CONTAINS PO1

G PO1



B Substrate

LVS Comparison




UMC Confidential

Ver. B04_PB 198

24.37 N_PO7W500_18_RF – 1.8 volt variable length RF NMOS transistor

Spectre Netlist

Spectre Model Name = “n_po7w500_18_rf” NM0 (D G S B) n_po7w500_18_rf l=200n

HspiceS Netlist

HspiceS Model Name = “N_PO7W500_18_RF” XNM0 D G S B N_PO7W500_18_RF L=200E-9

DIVA LVS Netlist

DIVA Device Name = “N_PO7W500_18_RF” ; N_PO7W500_18_RF Instance /NM0 = auLvs device M0

d N_PO7W500_18_RF D G S B (p D S)

i 0 N_PO7W500_18_RF D G S B " nf 5.0 L 200e-9 W 5e-6 M 7.0"

CDL Netlist

CDL Device Name = “N_PO7W500_18_RF” MMN0 D G S B N_PO7W500_18_RF W=5u L=200.0n M=7


UMC Confidential

Ver. B04_PB 199

Assura Netlist

Assura auLvs Device Name = “N_PO7W500_18_RF”

C N_PO7W500_18_RF MOS DRAIN B GATE B SOURCE B SUBSTRATE B ;;

* 4 pins

* 4 nets

* 0 instances i MN0 N_PO7W500_18_RF D G S B ; L 2.0e-07 W 5e-06 Nf 7 ;


UMC Confidential

Ver. B04_PB 200

N_PO7W500_18_RF (diagrammatic layout)


NPLUS


PO1, ME4-ME5

CONT

ME1-ME2

ME3-ME4

ME4-ME5

ME5-ME6

ME6

SYMBOL (RFMOS_S)

Width

Length


UMC Confidential

Ver. B04_PB 201


Device Derivation

Device Layer Derivation Recognition DIFF AND NPLUS AND RFSYMBOL AND SIZE1

CONTAINS PO1

G PO1



B Substrate

LVS Comparison




UMC Confidential

Ver. B04_PB 202

24.38 N_PO7W500_33_RF – 3.3 volt variable length RF NMOS transistor

Spectre Netlist

Spectre Model Name = “n_po7w500_33_rf” NM0 (D G S B) n_po7w500_33_rf l=340n

HspiceS Netlist

HspiceS Model Name = “N_PO7W500_33_RF” XNM0 D G S B N_PO7W500_33_RF L=340E-9

DIVA LVS Netlist

DIVA Device Name = “N_PO7W500_33_RF” ; N_PO7W500_33_RF Instance /NM0 = auLvs device M0

d N_PO7W500_33_RF D G S B (p D S)

i 0 N_PO7W500_33_RF D G S B " nf 5.0 L 340e-9 W 5e-6 M 7.0"

CDL Netlist CDL Device Name = “N_PO7W500_33_RF”


UMC Confidential

Ver. B04_PB 203

MMN0 D G S B N_PO7W500_33_RF W=5u L=340.0n M=7

Assura Netlist

Assura auLvs Device Name = “N_PO7W500_33_RF”

C N_PO7W500_33_RF MOS DRAIN B GATE B SOURCE B SUBSTRATE B ;;

* 4 pins

* 4 nets

* 0 instances i MN0 N_PO7W500_33_RF D G S B ; L 3.4e-07 W 5e-06 Nf 7 ;


UMC Confidential

Ver. B04_PB 204

N_PO7W500_33_RF (diagrammatic layout)


NPLUS


PO1, ME4-ME5

CONT

ME1-ME2

ME3-ME4

ME4-ME5

ME5-ME6

ME6

TG

Width

Length


UMC Confidential

Ver. B04_PB 205

SYMBOL (RFMOS_S)


Device Derivation

Device Layer Derivation Recognition DIFF AND NPLUS AND RFSYMBOL AND TG


G PO1



B Substrate

LVS Comparison




UMC Confidential

Ver. B04_PB 206

24.39 P_L18W500_18_RF – 1.8 volt variable finger RF PMOS transistor

Spectre Netlist Spectre Model Name = “p_l18w500_18_rf” PM0 (D G S B) p_l18w500_18_rf nf=5

HspiceS Netlist

HspiceS Model Name = “P_L18W500_18_RF” XPM0 D G S B P_L18W500_18_RF NF=5.0

DIVA LVS Netlist

DIVA Device Name = “P_L18W500_18_RF” ; P_L18W500_18_RF Instance /PM0 = auLvs device M0

d P_L18W500_18_RF D G S B (p D S)

i 0 P_L18W500_18_RF D G S B " nf 5.0 L 180e-9 W 5e-6 M 5.0"

CDL Netlist

CDL Device Name = “P_L18W500_18_RF”


UMC Confidential

Ver. B04_PB 207

MMP0 D G S B P_L18W500_18_RF W=5u L=180.0n M=5

Assura Netlist

Assura auLvs Device Name = “P_L18W500_18_RF”

C P_L18W500_18_RF MOS DRAIN B GATE B SOURCE B SUBSTRATE B ;;

* 4 pins

* 4 nets

* 0 instances i MP0 P_L18W500_18_RF D G S B ; L 1.8e-07 W 5e-06 Nf 5 ;


UMC Confidential

Ver. B04_PB 208

P_L18W500_18_RF (diagrammatic layout)


PPLUS

NPLUS, ME1, DIFF, CONT

PO1, ME4-ME5

CONT

ME1-ME2

ME3-ME4

ME4-ME5

ME5-ME6

Width

Length


UMC Confidential

Ver. B04_PB 209

ME6

SYMBOL(RFMOS_S)

SYMBOL(RFSYMBOL), SIZE(SIZE2), NWEL

Device Derivation

Device Layer Derivation Recognition DIFF AND PPLUS AND RFSYMBOL AND SIZE2

CONTAINS PO1

G PO1

D DIFF AND PPLUS NOT (PO1 OR RFMOS_S)

S DIFF AND PPLUS AND RFMOS_S NOT PO1

B NWEL

LVS Comparison




UMC Confidential

Ver. B04_PB 210

24.40 P_L34W500_33_RF – 3.3 volt variable finger RF PMOS transistor

Spectre Netlist

Spectre Model Name = “p_l34w500_33_rf” PM0 (D G S B) p_l34w500_33_rf nf=5

HspiceS Netlist

HspiceS Model Name = “P_L34W500_33_RF” XPM0 D G S B P_L34W500_33_RF NF=5.0

DIVA LVS Netlist

DIVA Device Name = “P_L34W500_33_RF” ; P_L34W500_33_RF Instance /PM0 = auLvs device M0

d P_L34W500_33_RF D G S B (p D S)

i 0 P_L34W500_33_RF D G S B " nf 5.0 L 340e-9 W 5e-6 M 5.0"

CDL Netlist

CDL Device Name = “P_L34W500_33_RF” MMP0 D G S B P_L34W500_33_RF W=5u L=340.0n M=5


UMC Confidential

Ver. B04_PB 211

Assura Netlist

Assura auLvs Device Name = “P_L34W500_33_RF”

C P_L34W500_33_RF MOS DRAIN B GATE B SOURCE B SUBSTRATE B ;;

* 4 pins

* 4 nets

* 0 instances i MN0 P_L34W500_33_RF D G S B ; L 3.4e-07 W 5e-06 Nf 5 ;


UMC Confidential

Ver. B04_PB 212

P_L34W500_33_RF (diagrammatic layout)


PPLUS


PO1, ME4-ME5

CONT

ME1-ME2

ME3-ME4

ME4-ME5

ME5-ME6

ME6

Width

Length


UMC Confidential

Ver. B04_PB 213

TG

SYMBOL(RFMOS_S)

SYMBOL(RFSYMBOL), SIZE(SIZE2), NWEL

Device Derivation

Device Layer Derivation Recognition DIFF AND PPLUS AND RFSYMBOL AND TG


G PO1



B NWEL

LVS Comparison




UMC Confidential

Ver. B04_PB 214

24.41 P_PO7W500_18_RF – 1.8 volt variable length RF PMOS transistor

Spectre Netlist

Spectre Model Name = “p_po7w500_18_rf” PM0 (D G S B) p_po7w500_18_rf l=200n

HspiceS Netlist

HspiceS Model Name = “P_PO7W500_18_RF” XPM0 D G S B P_PO7W500_18_RF L=200E-9

DIVA LVS Netlist

DIVA Device Name = “P_PO7W500_18_RF” ; P_PO7W500_18_RF Instance /PM0 = auLvs device M0

d P_PO7W500_18_RF D G S B (p D S)

i 0 P_PO7W500_18_RF D G S B " nf 5.0 L 200e-9 W 5e-6 M 7.0"

CDL Netlist

CDL Device Name = “P_PO7W500_18_RF” MMP0 D G S B P_PO7W500_18_RF W=5u L=200.0n M=7


UMC Confidential

Ver. B04_PB 215

Assura Netlist

Assura auLvs Device Name = “P_PO7W500_18_RF”

C P_PO7W500_18_RF MOS DRAIN B GATE B SOURCE B SUBSTRATE B ;;

* 4 pins

* 4 nets

* 0 instances i MP0 P_PO7W500_18_RF D G S B ; L 2.0e-07 W 5e-06 Nf 7 ;


UMC Confidential

Ver. B04_PB 216

P_PO7W500_18_RF (diagrammatic layout)


PPLUS

NPLUS, ME1, DIFF,CONT

PO1, ME4-ME5

CONT

ME1-ME2

ME3-ME4

ME4-ME5

ME5-ME6

ME6

Width

Length


UMC Confidential

Ver. B04_PB 217

SYMBOL(RFMOS_S)

SYMBOL (RFSYMBOL), SIZE(SIZE1), NWEL

Device Derivation



G PO1



B NWEL

LVS Comparison




UMC Confidential

Ver. B04_PB 218

24.42 P_PO7W500_33_RF – 3.3 volt variable length RF PMOS transistor

Spectre Netlist

Spectre Model Name = “p_po7w500_33_rf” PM0 (D G S B) p_po7w500_33_rf l=340n

HspiceS Netlist

HspiceS Model Name = “P_PO7W500_33_RF” XPM0 D G S B P_PO7W500_33_RF L=340E-9

DIVA LVS Netlist

DIVA Device Name = “P_PO7W500_33_RF” ; P_PO7W500_33_RF Instance /PM0 = auLvs device M0

d P_PO7W500_33_RF D G S B (p D S)

i 0 P_PO7W500_33_RF D G S B " nf 5.0 L 340e-9 W 5e-6 M 7.0"

CDL Netlist

CDL Device Name = “P_PO7W500_33_RF” MMP0 D G S B P_PO7W500_33_RF W=5u L=340.0n M=7


UMC Confidential

Ver. B04_PB 219

Assura Netlist

Assura auLvs Device Name = “P_PO7W500_33_RF”

C P_PO7W500_33_RF MOS DRAIN B GATE B SOURCE B SUBSTRATE B ;;

* 4 pins

* 4 nets

* 0 instances i MP0 P_PO7W500_33_RF D G S B ; L 3.4e-07 W 5e-06 Nf 7 ;


UMC Confidential

Ver. B04_PB 220

P_PO7W500_33_RF (diagrammatic layout)


PPLUS


PO1, ME4-ME5

CONT

ME1-ME2

ME3-ME4

ME4-ME5

ME5-ME6

ME6

Width

Length


UMC Confidential

Ver. B04_PB 221

TG

SYMBOL (RFMOS_S)

SYMBOL (RFSYMBOL), SIZE (SIZE1), NWEL

Device Derivation



G PO1

D DIFF AND PPLUS NOT (PO1 OR CONT)


B NWEL

LVS Comparison




UMC Confidential

Ver. B04_PB 222

24.43 MIMCAPM_RF – RF Metal Capacitor

Spectre Netlist Spectre Model Name = “mimcapm_rf” C0 (PLUS MINUS B) mimcapm_rf nx=1 ny=1 l=10.0u w=10.0u

HspiceS Netlist

HspiceS Model Name = “MIMCAPM_RF” XC0 PLUS MINUS B MIMCAPM_RF NX=1.0 NY=1.0 L=10E-6 W=10E-6

DIVA LVS Netlist

DIVA Device Name = “MIMCAPM_RF” ; MIMCAPM_RF Instance /C0 = auLvs device C0

d MIMCAPM_RF PLUS MINUS B

i 0 MIMCAPM_RF PLUS MINUS B " nx 1.0 ny 1.0 l 10e-6 w 10e-6 C 103e-15"

CDL Netlist

CDL Device Name = “MIMCAPM_RF” CC0 PLUS MINUS 103f $[MIMCAPM_RF] $SUB=B


UMC Confidential

Ver. B04_PB 223

Assura Netlist

Assura auLvs Device Name = “MIMCAPM_RF”

c MIMCAPM_RF CAP POS B MINUS B SUBSTRATE B;;

* 3 pins

* 3 nets

* 0 instances i C0 MIMCAPM_RF PLUS MINUS B; w 1e-05 C 1.03e-13 l 1e-05 nx 1.0 ny 1.0;


UMC Confidential

Ver. B04_PB 224

MIMCAPM_RF (diagrammatic layout)

Device Layers Layer Color and Fill MMC

DIFF

PPLUS

CONT

ME1, M1_CAD (Slot_Mark)

ME6

ME5

VI5

SYMBOL (CSYMBOL)

SYMBOL (RFSYMBOL)

Device Derivation


UMC Confidential

Ver. B04_PB 225

Device Layer Derivation Recognition MMC AND CSYMBOL AND RFSYMBOL

PLUS MMC

MINUS ME5 NOT MMC

B Substrate

LVS Comparison

Parameter Calculation Length MMC Area / Width

Width MMC coincident CSYMBOL

Nx Number of MMC enclosed by CSYMBOL

Ny Fingers/nx


UMC Confidential

Ver. B04_PB 226

24.44 L_SLCR20K_RF – Circular spiral Inductor

Spectre Netlist

Spectre Model Name = “l_slcr20k_rf” L0 (PLUS MINUS B) l_slcr20k_rf d=126u w=6u n=1.5

HspiceS Netlist

HspiceS Model Name = “P_PO7W500_33_RF” XL0 PLUS MINUS B L_SLCR20K_RF D=126E-6 W=6E-6 N=1.5

DIVA LVS Netlist

DIVA Device Name = “L_SLCR20K_RF” ; L_SLCR20K_RF Instance /L0 = auLvs device L0

d L_SLCR20K_RF PLUS MINUS B

i 0 L_SLCR20K_RF PLUS MINUS B " d 126e-6 w 6e-6 n 1.5 L 585.824e-12"

CDL Netlist

CDL Device Name = “L_SLCR20K_RF” LL0 PLUS MINUS 585.824p $[L_SLCR20K_RF] $SUB=B


UMC Confidential

Ver. B04_PB 227

Assura Netlist

Assura auLvs Device Name = “L_SLCR20K_RF”

c L_SLCR20K_RF IND POS B MINUS B SUBSTRATE B;;

* 3 pins

* 3 nets

* 0 instances i C0 L_SLCR20K_RF PLUS MINUS B; w 6e-06 d 126e-6 n 1.5;


UMC Confidential

Ver. B04_PB 228

L_SLCR20K_RF (diagrammatic layout)

Device Layers

Layer Color and Fill ME6

ME5

VI5

DIFF

PPLUS

CONT

ME1


UMC Confidential

Ver. B04_PB 229

SYMBOL (RFSYMBOL), SYMBOL (LSYMBOL)

Device Derivation

Device Layer Derivation Recognition LSYMBOL AND ME6 AND RFSYMBOL

PLUS ME6

MINUS ME6

B Substrate

LVS Comparison

Parameter Calculation Width ME6 Width


UMC Confidential

Ver. B04_PB 230

24.45 PAD_RF – Bond Pad

Spectre Netlist Spectre Model Name = “pad_rf” C0 (PLUS MINUS) pad_rf index=1

HspiceS Netlist

HspiceS Model Name = “PAD_RF” XC0 PLUS MINUS PAD_RF INDEX=1.0

DIVA LVS Netlist

DIVA Device Name = “PAD_RF” ; PAD_RF Instance /C0 = auLvs device C0

d PAD_RF PLUS MINUS

i 0 PAD_RF PLUS MINUS " index 1.0"

CDL Netlist

CDL Device Name = “PAD_RF” CC0 PLUS MINUS $[PAD_RF]


UMC Confidential

Ver. B04_PB 231

Assura Netlist

Assura auLvs Device Name = “PAD_RF”

c PAD_RF CAP POS B MINUS B ;;

* 2 pins

* 2 nets

* 0 instances i C0 PAD_RF PLUS MINUS ; index 1.0;


UMC Confidential

Ver. B04_PB 232

PAD_RF (diagrammatic layout)

Device Layers Layer Color and Fill PAD

ME6

ME1

SYMBOL (RFSYMBOL)

Device Derivation

Device Layer Derivation Recognition RFSYMBOL AND ME6 AND PAD AND ME1

PLUS ME6

MINUS ME1

LVS Comparison

Parameter Calculation Index RFSYMBOL AND ME6 AND PAD AND ME1

Overlapping particular metal layer.


UMC Confidential

Ver. B04_PB 233

24.46 RNHR_RF – RF High resistive poly resistor

Spectre Netlist

Spectre Model Name = “rnhr_rf”

R0 (PLUS MINUS B) rnhr_rf w=2u l=2u

HspiceS Netlist

HspiceS Model Name = “RNHR_RF” XR0 PLUS MINUS B RNHR_RF L=2E-6 W=2E-6

DIVA LVS Netlist

DIVA Device Name = “RNHR_RF” ; RNHR_RF Instance /R0 = auLvs device R0

d RNHR_RF PLUS MINUS B (p PLUS MINUS)

i 0 RNHR_RF PLUS MINUS B" R 972.1 L 2e-6 W 2e-6"

CDL Netlist

CDL Device Name = “RNHR_RF” RR0 PLUS MINUS 972.1 $SUB=B $[RNHR_RF] $W=2u $L=2u


UMC Confidential

Ver. B04_PB 234

Assura Netlist

Assura auLvs Device Name = “RNHR_RF”

c RNHR_RF RES IN B OUT B SUBSTRATE B ;;

* 3 pins

* 3 nets

* 0 instances i R0 RNHR_RF PLUS MINUS B; L 2e-06 W 2e-06 R 972.1;


UMC Confidential

Ver. B04_PB 235

RNHR_RF (diagrammatic layout)


PO1

SAB

PSYMBOL

ME1-ME6

ME1

CONT

SYMBOL (RFSYMBOL)

HR

NWEL

Device Derivation


UMC Confidential

Ver. B04_PB 236

Device Layer Derivation Recognition PO1 AND HR AND SAB AND PSYMBOL AND

RFSYMBOL AND NWEL

PLUS PO1

MINUS PO1

B NWEL

LVS Comparison

Parameter Calculation Length SAB length

Width PO1 width



UMC Confidential

Ver. B04_PB 237

24.47 RNNPO_RF – RF N+ poly resistor w/o salicide

Spectre Netlist

Spectre Model Name = “rnnpo_rf” R0 (PLUS MINUS B) rnnpo_rf w=2u l=2u

HspiceS Netlist

HspiceS Model Name = “RNNPO_RF” XR0 PLUS MINUS B RNNPO_RF L=2E-6 W=2E-6

DIVA LVS Netlist

DIVA Device Name = “RNNPO_RF” ; RNNPO_RF Instance /R0 = auLvs device R0

d RNNPO_RF PLUS MINUS B (p PLUS MINUS)

i 0 RNNPO_RF PLUS MINUS B" R 136.626 L 2e-6 W 2e-6"

CDL Netlist

CDL Device Name = “RNNPO_RF” RR0 PLUS MINUS 136.626 $SUB=B $[RNNPO_RF] $W=2u $L=2u


UMC Confidential

Ver. B04_PB 238

Assura Netlist

Assura auLvs Device Name = “RNNPO_RF”

c RNNPO_RF RES IN B OUT B SUBSTRATE B ;;

* 3 pins

* 3 nets

* 0 instances i R0 RNNPO_RF PLUS MINUS B; L 2e-06 W 2e-06 R 136.626;


UMC Confidential

Ver. B04_PB 239

RNNPO_RF (diagrammatic layout)

Device Layers Layer Color and Fill NPLUS

PO1

SAB

PSYMBOL

ME1-ME6

ME1

CONT

SYMBOL (RFSYMBOL)

SUBSTRATE

Device Derivation


UMC Confidential

Ver. B04_PB 240

Device Layer Derivation Recognition PO1 AND SAB AND PSYMBOL AND NPLUS

AND RFSYMBOL

PLUS PO1

MINUS PO1

B Substrate

LVS Comparison


Width PO1 width



UMC Confidential

Ver. B04_PB 241

24.48 RNPPO_RF – RF P+ poly resistor w/o salicide

Spectre Netlist

Spectre Model Name = “rnppo_rf” R0 (PLUS MINUS B) rnppo_rf w=2u l=2u

HspiceS Netlist

HspiceS Model Name = “RNPPO_RF” XR0 PLUS MINUS B RNPPO_RF L=2E-6 W=2E-6

DIVA LVS Netlist

DIVA Device Name = “RNPPO_RF” ; RNPPO_RF Instance /R0 = auLvs device R0

d RNPPO_RF PLUS MINUS B (p PLUS MINUS)

i 0 RNPPO_RF PLUS MINUS B" R 467.758 L 2e-6 W 2e-6"

CDL Netlist

CDL Device Name = “RNPPO_RF” RR0 PLUS MINUS 467.758 $SUB=B $[RNPPO_RF] $W=2u $L=2u


UMC Confidential

Ver. B04_PB 242

Assura Netlist

Assura auLvs Device Name = “RNPPO_RF”

c RNPPO_RF RES IN B OUT B SUBSTRATE B ;;

* 3 pins

* 3 nets

* 0 instances i R0 RNPPO_RF PLUS MINUS B; L 2e-06 W 2e-06 R 467.758;


UMC Confidential

Ver. B04_PB 243

RNPPO_RF (diagrammatic layout)


PO1

SAB

PSYMBOL

ME1-ME6

ME1

CONT

SYMBOL (RFSYMBOL)

NWEL

Device Derivation


UMC Confidential

Ver. B04_PB 244

Device Layer Derivation Recognition PO1 AND SAB AND PSYMBOL AND PPLUS AND

RFSYMBOL

PLUS PO1

MINUS PO1

B Substrate

LVS Comparison


Width PO1 width



UMC Confidential

Ver. B04_PB 245

24.49 VARMIS_18_RF– 1.8V N+/Nwell RF MIS varactor

Spectre Netlist

Spectre Model Name = “varmis_18_rf” C0 (PLUS MINUS B) varmis_18_rf nf=24

HspiceS Netlist

HspiceS Model Name = “VARMIS_18_RF” XC0 PLUS MINUS B VARMIS_18_RF NF=24.0

DIVA LVS Netlist

DIVA Device Name = “VARMIS_18_RF” ; VARMIS_18_RF Instance /C0 = auLvs device C0

d VARMIS_18_RF PLUS MINUS B

i 0 VARMIS_18_RF PLUS MINUS B" nf 24.0 C 1.03082e-12"

CDL Netlist

CDL Device Name = “VARMIS_18_RF” CC0 PLUS MINUS 1.03082p $[VARMIS_18_RF] $SUB=B


UMC Confidential

Ver. B04_PB 246

Assura Netlist

Assura auLvs Device Name = “VARMIS_18_RF”

c VARMIS_18_RF CAP POS B MINUS B SUBSTRATE B;;

* 3 pins

* 3 nets

* 0 instances i C0 VARMIS_18_RF PLUS MINUS B; nf 24.0 c 1.030828e-12;


UMC Confidential

Ver. B04_PB 247

VARMIS_18_RF (diagrammatic layout)


NWEL

NPLUS


PO1, ME4-ME5

CONT

ME1-ME2

ME3-ME6

ME4-ME5

Width

Length


UMC Confidential

Ver. B04_PB 248

ME5-ME6

ME6

SYMBOL (RFSYMBOL)

Device Derivation

Device Layer Derivation Recognition DIFF AND NWEL AND RFSYMBOL CONTAINS

PO1

PLUS PO1

MINUS DIFF AND NPLUS NOT PO1

B Substrate

LVS Comparison

Parameter Calculation Nf PO1 intersecting DIFF


UMC Confidential

Ver. B04_PB 249

24.50 VARDIOP_RF– P+/Nwell RF diode varactor

Spectre Netlist

Spectre Model Name = “vardiop_rf” C0 (PLUS MINUS) vardiop_rf nf=30

HspiceS Netlist

HspiceS Model Name = “VARDIOP_RF” XC0 PLUS MINUS VARDIOP_RF NF=30.0

DIVA LVS Netlist

DIVA Device Name = “VARDIOP_RF” ; VARDIOP_RF Instance /C0 = auLvs device C0

d VARDIOP_RF PLUS MINUS

i 0 VARDIOP_RF PLUS MINUS " nf 30.0 C 406.32e-15"

CDL Netlist

CDL Device Name = “VARDIOP_RF” CC0 PLUS MINUS 406.32f $[VARDIOP_RF]


UMC Confidential

Ver. B04_PB 250

Assura Netlist

Assura auLvs Device Name = “VARDIOP_RF”

c VARDIOP_RF CAP POS B MINUS B;;

* 2 pins

* 2 nets

* 0 instances i C0 VARDIOP_RF PLUS MINUS; nf 30.0 c 406.32e-15;


UMC Confidential

Ver. B04_PB 251

VARDIOP_RF (diagrammatic layout)


PPLUS


CONT

ME1

ME1-ME6

NWEL

SYMBOL (RFSYMBOL), SYMBOL (CSYMBOL)

Device Derivation

Device Layer Derivation Recognition DIFF AND CSYMBOL AND RFSYMBOL AND

NWEL

PLUS DIFF AND PPLUS


UMC Confidential

Ver. B04_PB 252

MINUS DIFF AND NPLUS

LVS Comparison

Parameter Calculation Nf DIFF AND PPLUS


UMC Confidential

Ver. B04_PB 253

25 Known Problems and Solutions Metal Resistors violate minimum area DRC Issue: The metal resistors ( RM1_MM – RM6_MM ) when set to their minimum length and width violate the minimum area Design rule. Solution: When the metal resistors are set to minimum, the designer needs to hook up the rest of the circuit to the metal resistors. When the minimum metal area metal resistors are hooked up, and DRC is run, this error will go away.

Assura LVS reports parameter mismatches when using a CDL netlist Issue: Assura LVS reports parameter mismatches when comparing a CDL netlist against the layout. The SKILL routines may have problems dealing with CDL netlists that include “ *.SCALE METER “ in the file. Solution: The user needs to manually edit the ASCII CDL netlist to change the SCALE being used. Currently, the CDL netlist outputs the following as the SCALE: *.SCALE METER The user needs to edit this line, so it reads: *.SCALE MICRON A solution will be created so that the user does not have to manually edit the ASCII CDL netlist, which will be provided in a future release. Parasitic devices in Pcells maybe double counted during Assura RCX Issue: Currently, parasitic devices in the Pcell maybe double counted during the Assura RCX process. Solution: A solution will be created so that this issue is avoided, which will be provided in a future release. Assura aborts when run on a GDS stream file Issue: When streaming out a GDS file, and then running Assura on it, Assura aborts prematurely. Solution: This is a GDS problem with regards to device name and model names. This problem can be avoided when streaming out a layout. In the Stream Out form, when selecting the Options button, a Stream Out Options form will appear. One needs to


UMC Confidential

Ver. B04_PB 254

ensure that the Case Sensitivity radio button is set to upper. An example of the Stream Out Options form is given below:

Assura DRC does not check for off grid errors Issue: Assura DRC does not check for off grid errors in layouts. Solution: To check for off grid errors in Assura DRC, the user needs to specify the grid size in the Assura Run DRC form. To do this, the user needs to select Assura -> Run DRC…This will bring up the Assura Run DRC form. In this form, the user needs to select the Modify avParameters… button in the bottom left-hand corner of the form. This will bring up the DRC Options form illustrated below. The user then needs to select the ?flagOffGrid option, and then enter the desired Grid Size. The user then needs to select the Use in Run option so that this change in avParameters is applied.


UMC Confidential

Ver. B04_PB 255

Metal Resistors may not route properly using VCR Issue: The metal resistors ( RM1_MM – RM6_MM ) may not route properly when using VCR. Solution: Manual adjustment may be necessary to fix routing problems encountered with metal resistors using VCR.

Devices fail to redraw in layout view, when Properties are edited Issue: Some devices fail to redraw in the layout view, when properties are edited in the “Edit Object Properties” form. Solution: The user may see these problems, if using Cadence ICFB 4.4.6.100.99 software. If this is the case, the user should use Cadence 4.4.6.100.70 instead, and this problem will be resolved.


UMC Confidential

Ver. B04_PB 256

The entire purpose name can not be read in the LSW window. Issue: Only the first and last letters of the purpose name can be viewed in the LSW window. Solution: The user can edit their "~/.Xdefaults" file and add the following lines to it; ! *********************************************************** ! * These resources allow you to set the LSW size * ! *********************************************************** Opus.LSWGeometry:300x760+770+0 Once these lines have been entered and saved in the "~/.Xdefaults" file, the user then needs to type the following command in their terminal window so that their LSW window will be resized during their next ICFB session: xrdb ~/.Xdefaults Once this has been done, and a new ICFB session is executed, the LSW window will be large enough so that the entire purpose name will be visible. L_SLCR20K_RF flags DRC error 4.31H

Issue: When DRC is run on the L_SLCR20K_RF pcell layout, the following error is flagged: 4.31H: The minimum overlap of IND to inductor layer is 10um Solution: The designer must connect to the PLUS and MINUS terminal with ME6. The width of the ME6 layer needs to be coincident with the width of the PLUS and MINUS terminals ( 6um, for example ). Please refer to the diagram below:


UMC Confidential

Ver. B04_PB 257

NCAP_MM and PCAP_MM will not route in VCR

Issue: NCAP_MM and PCAP_MM will not completely route in VCR. Solution: The user may need to manually route the NCAP_MM and PCAP_MM devices.

6um

6um


UMC Confidential

Ver. B04_PB 258

Appendix A.1 Revision History

Version Approved

Date

Author/

Reviser Event

Remark

(Purpose)

B03_PA

May/2005 Yueh Guey Chiou

UIP official release Doc No: G-9FD-MIXED_MODE/RFCMOS18-1.8V/3.3V-1P6M-MMC/UM180FDKMFC000000A-FDK-8C

B04_PB Dec/9/2005 Yueh Guey Chiou

1. Included SPICE model files for Spectre and Hspice

2. Included rule decks for Calibre

3. Updated Virtuoso techfile in FDK

4. Added RFMMCMK layer to MIMCAPM_RF Pcell

5. Modified RM1_MM ~RM6_MM mark layers to be MxRESMK layers

6. Removed VARACT layer from VARMIS_18_RF Pcell

7. Additional CDL parameters were added to the following devices

NF -> VARMIS_18_RF

NF -> VARDIOP_RF

NX,NY,W,L->MIMCAPM_RF

W,D,N -> L_SLCR20K_RF

INDEX -> PAD_RF

8. Added DIONW_MM cell views

9. Changed MIMCAPS_MM minimum width / length from 1.5um to 1.84um

10. Replaced two BJT layouts

1. One-single packaged FDK

2. One-single packaged FDK

3. By G-DF-GENERATION18-VIRTUOSO-TF 2.3_P1

4. By TLR 4.29M and Calibre DRC rule deck 2.7_P1

5. By Calibre LVS rule deck 1.3_P1

6. Null layer

7. By Calibre LVS deck 1.3_P1

8. Requested by Q&RA/DSQA

9. To form 2x2 VIA5 array at least inside Metal_CAP layer

10. By officially released SPICE twinwell 1.5_P1

A.2. UMC Utilities

Below utilities are provided in this design kit, and can be accessed from the “UMC Utils” pull-down menu, A.2.1. Callback Re-trigger Utility


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Ver. B04_PB 259

A.2.2. Alphabet Generator

Fig. The Alphabet Generator Usage- Generate alphabetical logo by physical layers in a layout view Text Input – Text content

Coordinate – Location of the logo (X:Y) Text Layer Name – Physical layer used Text Magnification Ratio – Text logo size


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Ver. B04_PB 260

Note: DRC errors might happen with small text magnification ratio.