Ultrasonic Atomizer Flash MCU - holtek.com.tw · PTP CTRL3 ST CMOS PTM output PA2/ ICPCK/ OCDSCK PA2 PAPU PAWU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. ICPCK

Ultrasonic Atomizer Flash MCU

HT45F3820

Revision: V1.11 Date: April 11, 2017

Rev. 1.11 2 April 11, 2017 Rev. 1.11 3 April 11, 2017

HT45F3820Ultrasonic Atomizer Flash MCU


Table of Contents

Features ............................................................................................................ 6CPU Features ......................................................................................................................... 6Peripheral Features ................................................................................................................. 6

General Description ........................................................................................ 7Block Diagram .................................................................................................. 8Pin Assignment ................................................................................................ 8Pin Descriptions .............................................................................................. 9Absolute Maximum Ratings .......................................................................... 10D.C. Characteristics ....................................................................................... 10A.C. Characteristics ....................................................................................... 12LVD & LVR Electrical Characteristics .......................................................... 13Over Current / Voltage Protection Electrical Characteristics .................... 14Power on Reset Electrical Characteristics .................................................. 15System Architecture ...................................................................................... 15

Clocking and Pipelining ......................................................................................................... 15Program Counter ................................................................................................................... 16Stack ..................................................................................................................................... 17Arithmetic and Logic Unit – ALU ........................................................................................... 17

Flash Program Memory ................................................................................. 18Structure ................................................................................................................................ 18Special Vectors ..................................................................................................................... 18Look-up Table ........................................................................................................................ 18Table Program Example ........................................................................................................ 19In Circuit Programming ......................................................................................................... 20On-Chip Debug Support – OCDS ......................................................................................... 20

RAM Data Memory ......................................................................................... 21Structure ................................................................................................................................ 21General Purpose Data Memory ............................................................................................ 21Special Purpose Data Memory ............................................................................................. 22

Special Function Register Description ........................................................ 23Indirect Addressing Registers – IAR0, IAR1 ......................................................................... 23Memory Pointers – MP0, MP1 .............................................................................................. 23Bank Pointer – BP ................................................................................................................. 24Accumulator – ACC ............................................................................................................... 24Program Counter Low Register – PCL .................................................................................. 24Look-up Table Registers – TBLP, TBHP, TBLH ..................................................................... 25Status Register – STATUS .................................................................................................... 25




EEPROM Data Memory .................................................................................. 27EEPROM Data Memory Structure ........................................................................................ 27EEPROM Registers .............................................................................................................. 27Reading Data from the EEPROM ........................................................................................ 29Writing Data to the EEPROM ................................................................................................ 29Write Protection ..................................................................................................................... 29EEPROM Interrupt ................................................................................................................ 29Programming Considerations ................................................................................................ 30

Oscillators ...................................................................................................... 31Oscillator Overview ............................................................................................................... 31System Clock Configurations ................................................................................................ 31Internal RC Oscillator – HIRC ............................................................................................... 32Internal 32kHz Oscillator – LIRC ........................................................................................... 32

Operating Modes and System Clocks ......................................................... 33System Clocks ...................................................................................................................... 33System Operating Modes ...................................................................................................... 34Control Registers .................................................................................................................. 35Operating Mode Switching ................................................................................................... 37Standby Current Considerations ........................................................................................... 41Wake-up ................................................................................................................................ 41

Watchdog Timer ............................................................................................. 42Watchdog Timer Clock Source .............................................................................................. 42Watchdog Timer Control Register ......................................................................................... 42Watchdog Timer Operation ................................................................................................... 43

Reset and Initialisation .................................................................................. 45Reset Functions .................................................................................................................... 45Reset Initial Conditions ......................................................................................................... 47

Input/Output Ports ......................................................................................... 49Pull-high Resistors ................................................................................................................ 50Port A Wake-up ..................................................................................................................... 50I/O Port Control Registers ..................................................................................................... 51I/O Port Source Current Control ............................................................................................ 51I/O Port Output Slew Rate Control ........................................................................................ 52Pin-shared Function .............................................................................................................. 52I/O Pin Structures .................................................................................................................. 54Programming Considerations ................................................................................................ 54

Timer Modules – TM ...................................................................................... 55Introduction ........................................................................................................................... 55TM Operation ........................................................................................................................ 55TM Clock Source ................................................................................................................... 55TM Interrupts ......................................................................................................................... 56TM External Pins ................................................................................................................... 56TM Input/Output Pin Control Register ................................................................................... 56Programming Considerations ................................................................................................ 57




Standard Type TM – STM .............................................................................. 58Standard TM Operation ......................................................................................................... 58Standard Type TM Register Description ............................................................................... 58Standard Type TM Operating Modes .................................................................................... 62

Periodic Type TM – PTM ................................................................................ 71Periodic TM Operation ......................................................................................................... 71Periodic Type TM Register Description ................................................................................ 71Periodic Type TM Operating Modes ..................................................................................... 76

Nebuliser Resonance Detector ..................................................................... 85Water Shortage Protection ............................................................................ 85Over Current/Voltage Protection .................................................................. 85

OCVP Operation ................................................................................................................... 85OCVP Control Registers ....................................................................................................... 86Input Voltage Range .............................................................................................................. 90Offset Calibration .................................................................................................................. 90

Interrupts ........................................................................................................ 91Interrupt Registers ................................................................................................................. 91Interrupt Operation ................................................................................................................ 96External Interrupts ................................................................................................................. 97OCVP Interrupt ...................................................................................................................... 98Multi-function Interrupts ......................................................................................................... 98Time Base Interrupts ............................................................................................................. 98EEPROM Interrupt .............................................................................................................. 100LVD Interrupt ....................................................................................................................... 100TM Interrupts ....................................................................................................................... 100Interrupt Wake-up Function ................................................................................................. 101Programming Considerations .............................................................................................. 101

Low Voltage Detector – LVD ....................................................................... 102LVD Register ....................................................................................................................... 102LVD Operation ..................................................................................................................... 103

Configuration Options ................................................................................. 103Application Circuits ..................................................................................... 104Instruction Set .............................................................................................. 105

Introduction ......................................................................................................................... 105Instruction Timing ................................................................................................................ 105Moving and Transferring Data ............................................................................................. 105Arithmetic Operations .......................................................................................................... 105Logical and Rotate Operation ............................................................................................. 106Branches and Control Transfer ........................................................................................... 106Bit Operations ..................................................................................................................... 106Table Read Operations ....................................................................................................... 106Other Operations ................................................................................................................. 106




Instruction Set Summary ............................................................................ 107Table Conventions ............................................................................................................... 107

Instruction Definition ................................................................................... 109Package Information ....................................................................................118

8-pin SOP (150mil) Outline Dimensions ..............................................................................11910-pin SOP (150mil) Outline Dimensions ........................................................................... 120




Features

CPU Features• OperatingVoltage:

♦ fSYS=12MHz:2.7V~5.5V♦ fSYS=32kHz:2.2V~5.5V

• Upto0.33μsinstructioncyclewith12MHzsystemclockatVDD=5V

• Powerdownandwake-upfunctionstoreducepowerconsumption

• Oscillators:♦ InternalHighSpeedRC–HIRC♦ InternalLowSpeed32kHzRC–LIRC

• Multi-modeoperation:NORMAL,SLOW,IDLEandSLEEP

• Allinstructionsexecutedinoneortwoinstructioncycles

• Tablereadinstructions

• 63powerfulinstructions

• 4-levelsubroutinenesting

• Bitmanipulationinstruction

Peripheral Features• FlashProgramMemory:1K×16

• RAMDataMemory:64×8

• TrueEEPROMMemory:32×8

• WatchdogTimerfunction

• 8bidirectionalI/Olines

• Twopin-sharedexternalinterrupts

• MultipleTimerModulesfortimemeasure,inputcapture,comparematchoutput,PWMoutputfunctionorsinglepulseoutputfunction♦ 10-bitPTM×1♦ 10-bitSTM×1

• OverCurrent/VoltageProtection(OCVP)Functionwithinterrupt

• DualTime-Basefunctionsforgenerationoffixedtimeinterruptsignals

• Lowvoltageresetfunction

• Lowvoltagedetectfunction

• Flashprogrammemorycanbere-programmedupto100,000times

• Flashprogrammemorydataretention>10years

• TrueEEPROMdatamemorycanbere-programmedupto1,000,000times

• TrueEEPROMdatamemorydataretention>10years

• PackageTypes:8-pinSOP/10-pinSOP




General Description TheHT45F3820isadevicededicatedforuseinultrasonicnebuliserapplications.Theapplicationprinciple forultrasonicnebulisers is touseelectronichigh-frequencyoscillationandceramicnebulisingchiphigh-frequencyresonancetobreakuptheliquidwatermoleculesthusgeneratinga finemistwithout requiringheatingoranychemicalsubstances.Comparedwith theheatingnebulisationmethod,theultrasonicmethodcanresultin90%energysavings.Additionally,duringthenebulisationprocess,itcanreleasealargenumberofnegativeionswhichcanprecipitatesmokeanddustparticles inairbyelectrostaticreactionandalsocaneffectivelyremoveformaldehyde,carbonmonoxide,bacteriaandotherharmfulsubstancesthusgeneratingcleanerairandreducingthepossibilityofdiseasetransmission.

Thedevice is aFlashMemory type8-bit highperformanceRISCarchitecturemicrocontrollercontainingspecialinternalcircuitryforultrasonicnebuliserapplications.OfferinguserstheconvenienceofFlashMemorymulti-programmingfeatures,thisdevicealsoincludesawiderangeoffunctionsandfeatures.OthermemoryincludesanareaofRAMDataMemoryaswellasanareaoftrueEEPROMmemoryforstorageofnon-volatiledatasuchasserialnumbers,calibrationdataetc.Analogfeatureincludesanovercurrent/voltageprotectionfunction.MultipleandextremelyflexibleTimerModulesprovidetiming,pulsegenerationandPWMgenerationfunctions.ProtectivefeaturessuchasaninternalWatchdogTimer,LowVoltageResetandLowVoltageDetectorcoupledwithexcellentnoiseimmunityandESDprotectionensurethatreliableoperationismaintainedinhostileelectricalenvironments.

Thedevicealso includes fully integrated lowandhighspeedoscillatorswhichcanbeflexiblyusedfordifferentapplications.Theabilitytooperateandswitchdynamicallybetweenarangeofoperatingmodesusingdifferentclocksourcesgivesusers theabilitytooptimisemicrocontrolleroperationandminimisepowerconsumption.

While the inclusionof flexible I/Oprogrammingfeatures,Time-Base functionsalongwithanadjustableultrasonicnebuliserresonantfrequencygeneratorandmanyotherfeaturesensurethatthedevicewillfindexcellentuseindifferentultrasonicnebuliserapplications.

Thisdevicecanuse thenebuliserresonancedetector todetect thenebuliserresonantfrequency,andusethenebuliserresonantfrequencyselectiontooutputPFMresonantfrequencyfornebulisercontrol, it canalsouse thewater shortageprotectionandOCVPfunctions forwater shortagedetection.




Block Diagram

8-bitRISCMCUCore

Timer Modules

Flash Program Memory

EEPROMData

Memory

Flash/EEPROM Programming Circuitry

RAMData

Memory

TimeBase

I/O

Low Voltage Detect

Watchdog Timer

InterruptController

ResetCircuit

Internal RCOscillators

Over Current/VoltageProtection

Low Voltage Reset

Nebuliser ResonantFrequency Selection

Slew RateController

Nebuliser Resonance Detector & Water Shortage

Protection

OCVPS[1:0]

Pin Assignment

1234

8765

109876

12345

HT45F38208 SOP-A

PTP/PA1VSSVDD

OCVPAI0/INT0/PTCK/PA3

PA0/ICPDA/OCDSDAPA2/ICPCK/OCDSCKOCVPAI0/STP/PA4/VREFOCVPCI/INT1/STCK/PA5

HT45F382010 SOP-A

PTP/PA1VSSVDD

OCVPAI0/PA7

OCVPAI0/PA6PA0/ICPDA/OCDSDAPA2/ICPCK/OCDSCKOCVPAI0/STP/PA4/VREF

OCVPAI0/INT0/PTCK/PA3 OCVPCI/INT1/STCK/PA5

HT45V382016 SOP-A

OCDSCKNCNC

OCVPAI0/INT0/PTCK/PA3OCVPAI0/PA7

OCDSDA

NCOCVPCI/INT1/STCK/PA5

NC

OCVPAI0/STP/PA4/VREF

PTP/PA1VSSVDD

OCVP0AI0/PA6PA0/ICPDAPA2/ICPCK

161514131211109

12345678

Note:1.Ifthepin-sharedpinfunctionshavemultipleoutputfunctions,thedesiredpin-sharedfunctionisdeterminedusingcorrespondingsoftwarecontrolbits.

2.TheactualdeviceanditsequivalentOCDSEVdevicesharethesamepackagetype,howevertheOCDSEVdevicepartnumberisHT45V3820.PinsOCDSCKandOCDSDAwhicharepin-sharedwithPA2andPA0areonlyusedfortheOCDSEVdevice.




Pin DescriptionsWiththeexceptionofthepowerpins,allpinsonthisdevicecanbereferencedtobytheirPortname,e.g.PA0,PA1etc,whichrefertothedigitalI/Ofunctionofthepins.HoweverthesePortpinsarealsosharedwithotherfunctionsuchasTimerModulepinsetc.Thefunctionofeachpinislistedinthefollowingtable,howeverthedetailsbehindhoweachpinisconfigurediscontainedinothersectionsofthedatasheet.

Pin Name Function OPT I/T O/T Description

PA0/ ICPDA/OCDSDA

PA0 PAPUPAWU ST CMOS General purpose I/O. Register enabled pull-up and

wake-up.ICPDA — ST CMOS In-circuit programming data/address pin

OCDSDA — ST CMOS On-chip debug support data/address pin, for EV chip only

PTP/PA1 PA1

PAPUPAWUCTRL3

ST CMOS General purpose I/O. Register enabled pull-up and wake-up.

PTP CTRL3 ST CMOS PTM output

PA2/ ICPCK/OCDSCK

PA2 PAPUPAWU ST CMOS General purpose I/O. Register enabled pull-up and

wake-up.ICPCK — ST — In-circuit programming clock pin

OCDSCK — ST — On-chip debug support clock pin, for EV chip only


PA3PAPUPAWUCTRL3


OCVPAI0 CTRL2CTRL3 ST — OCVPAI0 input path 0

INT0 CTRL3INTEG ST — External interrupt 0

PTCK CTRL3PTMC0 ST — PTM clock input

OCVPAI0/STP/VREF/PA4

PA4PAPUPAWUCTRL3


STP CTRL3 ST CMOS STM output or capture inputVREF CTRL3 AN — DAC Voltage reference

OCVPAI0 CTRL2CTRL3 ST — OCVPAI0 input path 0, nebuliser resonance detector

& water shortage protection

OCVPCI/INT1/STCK/PA5

PA5PAPUPAWUCTRL3


OCVPCI CTRL3 AN — Comparator non-inverted signal input

INT1 CTRL3INTEG ST — External interrupt 1

STCK CTRL3STMC0 ST — STM clock input

OCVPAI0/PA6PA6 PAPU

PAWU ST CMOS General purpose I/O. Register enabled pull-up and wake-up.


OCVPAI0/PA7PA7 PAPU

PAWU ST CMOS General purpose I/O. Register enabled pull-up and wake-up.





Pin Name Function OPT I/T O/T DescriptionVDD VDD — PWR — Positive power supplyVSS VSS — PWR — Negative Power Supply

Legend:I/T:Inputtype O/T:Outputtype OPT:Optionalbyregisteroption PWR:Power ST:SchmittTriggerinput CMOS:CMOSoutput

Absolute Maximum RatingsSupplyVoltage................................................................................................VSS−0.3VtoVSS+6.0VInputVoltage..................................................................................................VSS−0.3VtoVDD+0.3VStorageTemperature....................................................................................................-50˚Cto125˚COperatingTemperature..................................................................................................-40˚Cto85˚CIOLTotal..................................................................................................................................... 80mAIOHTotal....................................................................................................................................-80mATotalPowerDissipation......................................................................................................... 500mW

Note:Thesearestressratingsonly.Stressesexceeding therangespecifiedunder"AbsoluteMaximumRatings"maycausesubstantialdamagetothesedevices.Functionaloperationofthesedevicesatotherconditionsbeyondthoselistedinthespecificationisnotimpliedandprolongedexposuretoextremeconditionsmayaffectdevicesreliability.

D.C. CharacteristicsTa=25°C

Symbol ParameterTest Conditions

Min. Typ. Max. UnitVDD Conditions

VDDOperating Voltage (HIRC) — fSYS=fHIRC=12MHz 2.7 — 5.5 VOperating Voltage (LIRC) — fSYS=fLIRC=32kHz 2.2 — 5.5 V

IDD

Operating Current (HIRC)3V No load, all peripherals off,

fSYS=fHIRC=12MHz— 2.2 3.3 mA

5V — 5 7.5 mA

Operating Current (LIRC)3V No load, all peripherals off,

fSYS=fLIRC=32kHz— 10 20 μA

5V — 30 50 μA

ISTB

Standby Current (SLEEP0 Mode)

3V No load, all peripherals off, WDT off

— 0.2 0.8 μA5V — 0.5 1 μA

Standby Current (SLEEP1 Mode)

3V No load, all peripherals off, WDT on

— 1.3 5 μA5V — 2.2 10 μA

Standby Current (IDLE0 Mode)3V No load, all peripherals off,

fSUB on— 1.3 3 μA

5V — 2.2 5 μA

Standby Current (IDLE1 Mode, HIRC)

3V No load, all peripherals off, fSUB on, fSYS=fHIRC=12MHz

— 0.6 1.2 mA5V — 1.2 2.4 mA

VIL Input Low Voltage for I/O Ports5V — 0 — 1.5 V

— — 0 — 0.2VDD

V

VIH Input High Voltage for I/O Ports5V — 3.5 — 5 V

— — 0.8VDD

— VDD V






IOL

Sink Current for I/O Ports (PA7~PA2, PA0)

3V VOL=0.1VDD 16 32 — mA5V VOL=0.1VDD 32 65 — mA

Sink current for PA1 With Slew Rate Control

3V VOL=0.2VDD 24 60 — mA5V VOL=0.2VDD 60 150 — mA

IOH

Source Current for I/O Ports(PA7~PA2, PA0)

3V VOH=0.9VDD, SLEDC[m+1, m]=00B(m=0 or 2 or 4 or 6) -0.7 -1.5 — mA






3V VOH=0.9VDD, SLEDC[m+1, m]=11B(m=0 or 2 or 4 or 6) -4 -8 — mA

5V VOH=0.9VDD, SLEDC[m+1, m]=11B(m=0 or 2 or 4 or 6) -8 -16 — mA

Source current for PA1 With Slew Rate Control

3V VOH=0.8VDD -24 -60 — mA5V VOH=0.8VDD -60 -150 — mA

SRRISEOutput Rising Edge Slew Rate for PA1

5VSLEWC[m+1, m]=00B(m=0 or 2 or 4 or 6), 0.5V ~ 4.5V,CLOAD=1000pF

200 — — V/μs


— 60 — V/μs


— 30 — V/μs


— 15 — V/μs

SRFALLOutput Falling Edge Slew Rate for PA1


200 — — V/μs


— 60 — V/μs


— 30 — V/μs


— 15 — V/μs

RPHPull-high Resistance for I/O Ports

3V — 20 60 100 kΩ5V — 10 30 50 kΩ




A.C. CharacteristicsTa=25°C



fSYSSystem Clock (HIRC) 2.7V ~ 5.5V fSYS=fHIRC=12MHz — 12 — MHzSystem Clock (LIRC) 2.2V ~ 5.5V fSYS=fLIRC=32kHz — 32 — kHz

fHIRCHigh Speed Internal RC Oscillator (HIRC)

3V Ta=25°C -2% 12 +2% MHz5V Ta=25°C -2% 12 +2% MHz

2.7V ~ 5.5V Ta=25°C -5% 12 +5% MHz3V Ta=0°C ~ 70°C - 7% 12 +7% MHz5V Ta=0°C ~ 70°C - 7% 12 +7% MHz3V Ta= -40°C ~ 85°C -10% 12 +10% MHz5V Ta= -40°C ~ 85°C -7% 12 +7% MHz

2.7V ~ 5.5V Ta=0°C ~ 70°C -7% 12 +7% MHz2.7V ~ 5.5V Ta= -40°C ~ 85°C -10% 12 +10% MHz

fLIRCLow Speed Internal RC Oscillator (LIRC)

3V Ta=25°C -10% 32 +10% kHz3V ± 0.3V Ta= -40°C ~ 85°C -40% 32 +40% kHz

2.2V ~ 5.5V Ta= -40°C ~ 85°C -50% 32 +60% kHz5V Ta=25°C -10% 32 +10% kHz

5V ± 0.5V Ta= -40°C ~ 85°C -40% 32 +40% kHz2.2V ~ 5.5V Ta= -40°C ~ 85°C -50% 32 +50% kHz

tINTExternal Interrupt Minimum Pulse Width — — 1 3.3 5 μs

tEERD EEPROM Read Time — — — 2 4 tSYS

tEEWR EEPROM Write Time — — — 2 4 ms

tRSTD

System Reset Delay Time (Power-on Reset, LVR Hardware Reset, LVR Software Reset, WDT Software Reset)

— — 25 50 100 ms

System reset delay time (WDT Time-out Hardware Cold Reset)

— — 8.3 16.7 33.3 ms

tSST

System Start-up Timer Period (Wake-up from Power Down Mode and fSYS off)

— fSYS=fH ~ fH / 64, fH=fHIRC 16 — — tHIRC

— fSYS=fSUB=fLIRC 2 — — tLIRC

System Start-up Timer Period (Slow Mode ↔ Normal Mode) — fHIRC off → on (HTO=1) 16 — — tHIRC

System Start-up Timer Period(Wake-up from Power Down Mode and fSYS on)

— fSYS=fHIRC ~ fHIRC /64 2 — — tH

— fSYS=fLIRC 2 — — tSUB

System Start-up Timer Period(WDT Time-out Hardware Cold Reset)

— — 0 — — tH

Note:1.tSYS=1/fSYS;tSUB=1/fSUB;tHIRC=1/fHIRC2.TomaintaintheaccuracyoftheinternalHIRCoscillatorfrequency,a0.1μFdecouplingcapacitorshouldbeconnectedbetweenVDDandVSSandlocatedasclosetothedeviceaspossible.

3.Frequencyaccuracy(trimatVDD=3V/5V,FADJH=01H,FADJL=00H).




LVD & LVR Electrical CharacteristicsTa=25°C



VLVR Low Voltage Reset Voltage —

LVR enable, 2.1V

-5%

2.1

+5%

VLVR enable, 2.55V 2.55 VLVR enable, 3.15V 3.15 VLVR enable, 3.8V 3.8 V

VLVD Low Voltage Detector Voltage

— LVDEN=1, VLVD=2.0V

-5%

2.0

+5%

V— LVDEN=1, VLVD=2.2V 2.2 V— LVDEN=1, VLVD=2.4V 2.4 V— LVDEN=1, VLVD=2.7V 2.7 V— LVDEN=1, VLVD=3.0V 3.0 V— LVDEN=1, VLVD=3.3V 3.3 V— LVDEN=1, VLVD=3.6V 3.6 V— LVDEN=1, VLVD=4.0V 4.0 V

ILVRAdditional PowerConsumption if LVR is used 5V±3% LVR disable → LVR enable — 60 90 μA

ILVDAdditional PowerConsumption if LVD is used 5V±3%

LVD disable → LVD enable (LVR disable) — 75 115 μA

LVD disable → LVD enable (LVR enable) — 60 90 μA

tLVRLVR Minimum Low Voltage Width to Reset — — 120 240 480 μs

tLVDLVD Minimum Low Voltage Width to Interrupt — — 60 120 240 μs

tLVDS LVDO Stable Time— For LVR enable, LVD off → on — — 15 μs— For LVR disable, LVD off → on — — 150 μs

tSRESET Software Reset Width to Reset — — 45 90 120 μs

Note:VLVRorVLVDistheMCUoperatingvoltagelevelunderwhichaLVRresetorLVDinterruptoccurs.




Over Current / Voltage Protection Electrical CharacteristicsTa=25°C



IOCVP Operating Current3V

DAC VREF=2.5V— — 1250 μA

5V — 730 1250 μA

VOS_CMPComparator Input Offset Voltage

3V Without calibration(OCVPCOF[4:0]=10000B) -15 — 15 mV

5V Without calibration(OCVPCOF[4:0]=10000B) -15 — 15 mV

3V With calibration -4 — 4 mV5V With calibration -4 — 4 mV

VHYS Hysteresis3V — 20 40 60 mV5V — 20 40 60 mV

VCM_CMPComparator Common Mode Voltage Range

3V — VSS — VDD

- 1.4 V

5V — VSS — VDD

- 1.4 V

VOS_OPA OPA Input Offset Voltage

3V Without calibration(OCVPOOF[5:0]=100000B) -15 — 15 mV

5V Without calibration(OCVPOOF[5:0]=100000B) -15 — 15 mV

3V With calibration -4 — 4 mV5V With calibration -4 — 4 mV

VCM_OPAOPA Common Mode Voltage Range

3V — VSS — VDD

- 1.4 V

5V — VSS — VDD

- 1.4 V

VOROPA Maximum Output Voltage Range

3V — VSS

+ 0.1 — VDD

- 0.1 V

5V — VSS

+ 0.1 — VDD

- 0.1 V

Ga PGA Gain Accuracy 3V/5V

In non-inverting mode, R2/R1≤50, using internal resistor, and input voltage > 80mV

-5 — 5 %

In non-inverting mode, R2/R1=65 or 80 , using internal resistor, and input voltage > 50mV

-8 — 8 %

In non-inverting mode, R2/R1=130, using internal resistor, and input voltage > 35mV

-10 — 10 %

In inverting mode, R2/R1≤50, using internal resistor, and input voltage < -80mV

-5 — 5 %

In inverting mode, R2/R1=65 or 80, using internal resistor, and input voltage < -50mV

-8 — 8 %

In inverting mode, R2/R1=130, using internal resistor, and input voltage < -35mV

-10 — 10 %

DNL Differential Non-linearity3V DAC VREF=VDD — — ±2 LSB5V DAC VREF=VDD — — ±1 LSB

INL Integral Non-linearity3V DAC VREF=VDD — — ±2 LSB5V DAC VREF=VDD — — ±1.5 LSB




Power on Reset Electrical CharacteristicsTa=25°C



VPOR VDD Start Voltage to Ensure Power-on Reset — — — — 100 mVRRPOR VDD Rising Rate to Ensure Power-on Reset — — 0.035 — — V/ms

tPORMinimum Time for VDD Stays at VPOR to Ensure Power-on Reset — — 1 — — ms

VDD

tPOR RRPOR

VPOR

Time

System ArchitectureAkeyfactorinthehigh-performancefeaturesoftheHoltekrangeofmicrocontrollersisattributedtotheirinternalsystemarchitecture.ThedevicetakesadvantageoftheusualfeaturesfoundwithinRISCmicrocontrollersproviding increasedspeedofoperationandPeriodicperformance.Thepipeliningschemeisimplementedinsuchawaythatinstructionfetchingandinstructionexecutionareoverlapped,henceinstructionsareeffectivelyexecutedinonecycle,withtheexceptionofbranchorcall instructions.An8-bitwideALUisusedinpracticallyall instructionsetoperations,whichcarriesoutarithmeticoperations,logicoperations,rotation,increment,decrement,branchdecisions,etc.The internaldatapath issimplifiedbymovingdata throughtheAccumulatorandtheALU.Certain internalregistersare implemented in theDataMemoryandcanbedirectlyor indirectlyaddressed.Thesimpleaddressingmethodsof theseregistersalongwithadditionalarchitecturalfeaturesensure thataminimumofexternalcomponents is required toprovideafunctional I/Ocontrolsystemwithmaximumreliabilityandflexibility.Thismakesthedevicesuitableforlow-cost,high-volumeproductionforcontrollerapplications.

Clocking and PipeliningThemainsystemclock,derivedfromeitheranHIRCorLIRCoscillator issubdividedintofourinternallygeneratednon-overlappingclocks,T1~T4.TheProgramCounter is incrementedat thebeginningoftheT1clockduringwhichtimeanewinstructionisfetched.TheremainingT2~T4clockscarryoutthedecodingandexecutionfunctions.Inthisway,oneT1~T4clockcycleformsoneinstructioncycle.Althoughthefetchingandexecutionofinstructionstakesplaceinconsecutiveinstructioncycles, thepipeliningstructureof themicrocontrollerensures that instructionsareeffectivelyexecuted inone instructioncycle.Theexception to thisare instructionswhere thecontentsoftheProgramCounterarechanged,suchassubroutinecallsorjumps,inwhichcasetheinstructionwilltakeonemoreinstructioncycletoexecute.




Fetch Inst. (PC)

(System Clock)fSYS

Phase Clock T1

Phase Clock T2

Phase Clock T3

Phase Clock T4

Program Counter PC PC+1 PC+2

PipeliningExecute Inst. (PC-1) Fetch Inst. (PC+1)

Execute Inst. (PC) Fetch Inst. (PC+2)

Execute Inst. (PC+1)

System Clock and Pipelining

For instructions involvingbranches,suchas jumporcall instructions, twomachinecyclesarerequired tocomplete instructionexecution.Anextracycle is requiredas theprogramtakesonecycletofirstobtaintheactualjumporcalladdressandthenanothercycletoactuallyexecutethebranch.Therequirementforthisextracycleshouldbetakenintoaccountbyprogrammersintimingsensitiveapplications.

Fetch Inst. 11 MOV A,[12H]2 CALL DELAY3 CPL [12H]4 :5 :6 DELAY: NOP

Execute Inst. 1 Fetch Inst. 2 Execute Inst. 2

Fetch Inst. 3 Flush PipelineFetch Inst. 6 Execute Inst. 6

Fetch Inst. 7

Instruction Fetching

Program CounterDuringprogramexecution, theProgramCounter isused tokeep trackof theaddressof thenext instruction tobeexecuted. It isautomatically incrementedbyoneeach timean instructionisexecutedexcept for instructions, suchas"JMP"or"CALL" thatdemanda jump toanon-consecutiveProgramMemoryaddress.Onlythelower8bits,knownastheProgramCounterLowRegister,aredirectlyaddressablebytheapplicationprogram.

Whenexecutinginstructionsrequiringjumpstonon-consecutiveaddressessuchasajumpinstruction,asubroutinecall, interruptorreset,etc., themicrocontrollermanagesprogramcontrolby loadingtherequiredaddressintotheProgramCounter.Forconditionalskipinstructions,oncetheconditionhasbeenmet, thenext instruction,whichhasalreadybeenfetchedduring thepresent instructionexecution,isdiscardedandadummycycletakesitsplacewhilethecorrectinstructionisobtained.

Program CounterProgram Counter High byte PCL Register

PC9~PC8 PCL7~PCL0

Thelowerbyteof theProgramCounter,knownastheProgramCounterLowregisterorPCL,isavailableforprogramcontrolandisareadableandwriteableregister.Bytransferringdatadirectlyintothisregister,ashortprogramjumpcanbeexecuteddirectly,however,asonlythis lowbyteisavailable formanipulation, the jumpsare limited to thepresentpageofmemory that is256locations.Whensuchprogramjumpsareexecuted itshouldalsobenoted thatadummycyclewillbeinserted.ManipulatingthePCLregistermaycauseprogrambranching,soanextracycleisneededtopre-fetch.




StackThis isaspecialpartof thememorywhichisusedtosavethecontentsof theProgramCounteronly.Thestackisneitherpartofthedatanorpartoftheprogramspace,andisneitherreadablenorwriteable.TheactivatedlevelisindexedbytheStackPointer,andisneitherreadablenorwriteable.Atasubroutinecallorinterruptacknowledgesignal,thecontentsoftheProgramCounterarepushedontothestack.Attheendofasubroutineoraninterruptroutine,signaledbyareturninstruction,RETorRETI,theProgramCounterisrestoredtoitspreviousvaluefromthestack.Afteradevicereset,theStackPointerwillpointtothetopofthestack.

Ifthestackisfullandanenabledinterrupttakesplace,theinterruptrequestflagwillberecordedbuttheacknowledgesignalwillbeinhibited.WhentheStackPointer isdecremented,byRETorRETI,theinterruptwillbeserviced.Thisfeaturepreventsstackoverflowallowingtheprogrammertousethestructuremoreeasily.However,whenthestackisfull,aCALLsubroutineinstructioncanstillbeexecutedwhichwillresult inastackoverflow.Precautionsshouldbetakentoavoidsuchcaseswhichmightcauseunpredictableprogrambranching.Ifthestackisoverflow,thefirstProgramCountersaveinthestackwillbelost.

StackPointer

Stack Level 2

Stack Level 1

Stack Level 3

Stack Level 4

Program Memory

Program Counter

Bottom of Stack

Top of Stack

Arithmetic and Logic Unit – ALUThearithmetic-logicunitorALUisacriticalareaofthemicrocontrollerthatcarriesoutarithmeticandlogicoperationsoftheinstructionset.Connectedtothemainmicrocontrollerdatabus,theALUreceivesrelatedinstructioncodesandperformstherequiredarithmeticor logicaloperationsafterwhichtheresultwillbeplacedinthespecifiedregister.AstheseALUcalculationoroperationsmayresultincarry,borroworotherstatuschanges,thestatusregisterwillbecorrespondinglyupdatedtoreflectthesechanges.TheALUsupportsthefollowingfunctions:

• Arithmeticoperations:ADD,ADDM,ADC,ADCM,SUB,SUBM,SBC,SBCM,DAA

• Logicoperations:AND,OR,XOR,ANDM,ORM,XORM,CPL,CPLA

• Rotation:RRA,RR,RRCA,RRC,RLA,RL,RLCA,RLC

• IncrementandDecrement:INCA,INC,DECA,DEC

• Branchdecision:JMP,SZ,SZA,SNZ,SIZ,SDZ,SIZA,SDZA,CALL,RET,RETI




Flash Program MemoryTheProgramMemoryisthelocationwheretheusercodeorprogramisstored.ForthisdevicetheProgramMemoryisFlashtype,whichmeansitcanbeprogrammedandre-programmeda largenumberof times,allowing theuser theconvenienceofcodemodificationon thesamedevice.Byusing theappropriateprogramming tools, thisFlashdeviceoffersusers the flexibility toconvenientlydebuganddeveloptheirapplicationswhilealsoofferingameansoffieldprogrammingandupdating.

StructureTheProgramMemoryhasacapacityof1K×16bits.TheProgramMemoryisaddressedby theProgramCounterandalsocontainsdata,tableinformationandinterruptentries.Tabledata,whichcanbesetupinanylocationwithintheProgramMemory,isaddressedbyaseparatetablepointerregister.

Special VectorsWithintheProgramMemory,certainlocationsarereservedfortheresetandinterrupts.Thelocation000His reserved foruseby thedevice reset forprograminitialisation.Afteradevice reset isinitiated,theprogramwilljumptothislocationandbeginexecution.

000H004H

024H

Reset

Interrupt Vector

16 bits3FFH

Program Memory Structure

Look-up TableAnylocationwithintheProgramMemorycanbedefinedasalook-uptablewhereprogrammerscanstorefixeddata.Tousethelook-uptable,thetablepointermustfirstbesetupbyplacingtheaddressof thelookupdatatoberetrievedinthetablepointerregister,TBLPandTBHP.Theseregistersdefinethetotaladdressofthelook-uptable.

Aftersettingupthetablepointer,thetabledatacanberetrievedfromtheProgramMemoryusingthe"TABRD[m]"or"TABRDL[m]"instructions,respectively.Whentheinstructionisexecuted,the lowerorder tablebyte from theProgramMemorywillbe transferred to theuserdefinedDataMemoryregister[m]asspecified in the instruction.Thehigherorder tabledatabytefromtheProgramMemorywillbe transferred to theTBLHspecial register.Anyunusedbits in thistransferredhigherorderbytewillbereadas"0".

Theaccompanyingdiagramillustratestheaddressingdataflowofthelook-uptable.




Last Page or TBHP Register

TBLP Register

Program Memory

Register TBLH User Selected Register

Address

Data16 bits

High Byte Low Byte

Table Program ExampleThefollowingexampleshowshowthetablepointerandtabledataisdefinedandretrievedfromthemicrocontroller.ThisexampleusesrawtabledatalocatedintheProgramMemorywhichisstoredthereusingtheORGstatement.ThevalueatthisORGstatementis"300H"whichreferstothestartaddressofthelastpagewithinthe1KwordsProgramMemoryofthedevice.Thetablepointerissetupheretohaveaninitialvalueof"06H".Thiswillensurethatthefirstdatareadfromthedatatablewillbeat theProgramMemoryaddress"306H"or6 locationsafter thestartof theTBHPspecifiedpage.NotethatthevalueforthetablepointerisreferencedtothefirstaddressspecifiedbytheTBHPandTBLPregistersifthe"TABRD[m]"instructionisbeingused.ThehighbyteofthetabledatawhichinthiscaseisequaltozerowillbetransferredtotheTBLHregisterautomaticallywhenthe"TABRD[m]"instructionisexecuted.

Because theTBLHregister isaread-onlyregisterandcannotberestored,careshouldbe takentoensure itsprotection ifboth themain routineand InterruptServiceRoutineuse table readinstructions. Ifusing the tableread instructions, theInterruptServiceRoutinesmaychange thevalueoftheTBLHandsubsequentlycauseerrorsifusedagainbythemainroutine.Asaruleitisrecommendedthatsimultaneoususeofthetablereadinstructionsshouldbeavoided.However, insituationswheresimultaneoususecannotbeavoided,theinterruptsshouldbedisabledpriortotheexecutionofanymainroutinetable-readinstructions.Notethatalltablerelatedinstructionsrequiretwoinstructioncyclestocompletetheiroperation.

Table Read Program Exampletempreg1 db ? ; temporary register #1tempreg2 db ? ; temporary register #2:mov a,06h ; initialise low table pointer-note that this address is referencedmov tblp,a ; to the last page or specific pagemov a,03h ; initialise high table pointermov tbhp,a:tabrd tempreg1 ; transfers value in table referenced by table pointer ; data at program memory address "306H" transferred to tempreg1 and TBLHdec tblp ; reduce value of table pointer by onetabrd tempreg2 ; transfers value in table referenced by table pointer ; data at program memory address "305H" transferred to tempreg2 and TBLH ; in this example the data "1AH" is transferred to tempreg1 and data "0FH" to ; register tempreg2, the value 00H will be transferred to the high byte ; register TBLH:org 300h ; sets initial address of program memorydc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh:




In Circuit ProgrammingTheprovisionofFlashtypeProgramMemoryprovidestheuserwithameansofconvenientandeasyupgradesandmodificationstotheirprogramsonthesamedevice.Asanadditionalconvenience,Holtekhasprovidedameansofprogrammingthemicrocontrollerin-circuitusinga4-pininterface.Thisprovidesmanufacturerswiththepossibilityofmanufacturingtheircircuitboardscompletewithaprogrammedorun-programmedmicrocontroller,andthenprogrammingorupgradingtheprogramata laterstage.Thisenablesproductmanufacturers toeasilykeep theirmanufacturedproductssuppliedwiththelatestprogramreleaseswithoutremovalandre-insertionofthedevice.

TheHoltekFlashMCUtoWriterProgrammingPincorrespondencetableisasfollows:

Holtek Write Pins MCU Programming Pins FunctionICPDA PA0 Programming Serial Data/AddressICPCK PA2 Programming ClockVDD VDD Power SupplyVSS VSS Ground

TheProgramMemoryandEEPROMdatamemorycanbothbeprogrammedseriallyin-circuitusingthis4-wireinterface.Dataisdownloadedanduploadedseriallyonasinglepinwithanadditionallinefor theclock.Twoadditional linesarerequiredfor thepowersupply.The technicaldetailsregardingthein-circuitprogrammingofthedevicearebeyondthescopeofthisdocumentandwillbesuppliedinsupplementaryliterature.

Duringtheprogrammingprocess,theusermusttakecareoftheICPDAandICPCKpinsfordataandclockprogrammingpurposetoensurethatnootheroutputsareconnectedtothesetwopins.

* *

Writer_VDD

ICPDA

ICPCK

Writer_VSS

To other Circuit

VDD

PA0

PA2

VSS

Writer Connector Signals

MCU ProgrammingPins

Note:*mayberesistororcapacitor.Theresistanceof*mustbegreaterthan1kΩorthecapacitanceof*mustbelessthan1nF.

On-Chip Debug Support – OCDSThedevicehasanEVchipnamedHT45V3820whichisusedtoemulatetheHT45F3820device.ThisEVchipdevicealsoprovidesan"On-ChipDebug"functiontodebugtherealMCUdeviceduring thedevelopmentprocess.TheEVchipandtherealMCUdevicearealmostfunctionallycompatibleexceptforthe"On-ChipDebug"function.UserscanusetheEVchipdevicetoemulatetherealchipdevicebehaviorbyconnectingtheOCDSDAandOCDSCKpinstotheHoltekHT-IDEdevelopmenttools.TheOCDSDApinis theOCDSData/Addressinput/outputpinwhiletheOCDSCKpin is theOCDSclock inputpin.Whenusersuse theEVchipfordebugging,otherfunctionswhicharesharedwiththeOCDSDAandOCDSCKpinsinthedevicewillhavenoeffectintheEVchip.However,thetwoOCDSpinswhicharepin-sharedwiththeICPprogrammingpinsarestillusedastheFlashMemoryprogrammingpinsforICP.FormoredetailedOCDSinformation,refertothecorrespondingdocumentnamed"Holteke-Linkfor8-bitMCUOCDSUser’sGuide".




Holtek e-Link Pins EV Chip Pins Pin DescriptionOCDSDA OCDSDA On-chip Debug Support Data/Address input/outputOCDSCK OCDSCK On-chip Debug Support Clock input

VDD VDD Power SupplyGND VSS Ground

RAM Data MemoryTheDataMemoryisavolatileareaof8-bitwideRAMinternalmemoryandisthelocationwheretemporaryinformationisstored.

StructureDividedintotwosections,thefirstoftheseisanareaofRAM,knownastheSpecialPurposeDataMemory.Herearelocatedregisterswhicharenecessaryforcorrectoperationofthedevice.Manyoftheseregisterscanbereadfromandwrittentodirectlyunderprogramcontrol,however,someremainprotectedfromusermanipulation.ThesecondareaofDataMemoryisknownastheGeneralPurposeDataMemory,whichisreservedforgeneralpurposeuse.Alllocationswithinthisareaarereadandwriteaccessibleunderprogramcontrol.

TheoverallDataMemoryissubdividedintotwobanks.TheSpecialPurposeDataMemoryregistersareaccessibleinallbanks,withtheexceptionoftheEECregisterataddress40H,whichisonlyaccessibleinBank1.SwitchingbetweenthedifferentDataMemorybanksisachievedbysettingtheBankPointertothecorrectvalue.ThestartaddressoftheDataMemoryforthedeviceistheaddress00H.

Special Purpose Data Memory General Purpose Data MemoryAddress Capacity Address

Bank 0: 00H~7FHBank 1: 00H~7FH 64×8 Bank 0: 80H~BFH

Special PurposeData Memory

General PurposeData Memory

000H

07FH080H

0BFH

Bank 1

Bank 0

EEC

Data Memory Structure

General Purpose Data MemoryAllmicrocontrollerprogramsrequireanareaofread/writememorywheretemporarydatacanbestoredandretrievedforuselater.ItisthisareaofRAMmemorythatisknownasGeneralPurposeDataMemory.ThisareaofDataMemoryisfullyaccessiblebytheuserprogramingforbothreadingandwritingoperations.ByusingthebitoperationinstructionsindividualbitscanbesetorresetunderprogramcontrolgivingtheuseralargerangeofflexibilityforbitmanipulationintheDataMemory.




Special Purpose Data MemoryThis area ofDataMemory iswhere registers, necessary for the correct operation of themicrocontroller,arestored.Mostof theregistersarebothreadableandwriteablebutsomeareprotectedandarereadableonly,thedetailsofwhicharelocatedundertherelevantSpecialFunctionRegistersection.Notethatforlocationsthatareunused,anyreadinstructiontotheseaddresseswillreturnthevalue"00H".

00H IAR0

01H MP0

02H IAR1

03H MP1

04H

05H ACC

06H PCL

07H TBLP

08H TBLH

09H TBHP

0AH STATUS

0BH

0CH

0DH

0EH

0FH

10H

STMC1

11H

STMDL

12H

19H

18H

INTC2

1BH

1AH

1DH

1CH

1FH

MFI0

MFI1

1EH

SMOD

13H

14H

STMAH

15H

16H

17H

Bank 0, 1

MFI2

PAC

PAPU

PAWU

WDTC

TBC

EEA

EED

FADJH

CTRL

LVRC

STMC0

20H

21H

22H

29H

28H

2BH

2AH

2DH

2CH

2FH

2EH

23H

24H

25H

26H

27H

30H

31H

32H

39H

38H

3BH

3AH

3DH

3CH

3FH

3EH

33H

34H

35H

36H

37H

40H EEC

41H

42H

43H

47H

48H

PTMAL

49H

4AH

4BH

4CH

4DH

4EH

4FH

50H

51H

52H

58H

53H

54H

55H

56H

57H

Bank 0

Unused

PTMDL

PTMDH

PTMAH

PTMRPL

PTMRPH

60H

61H

BP

LVDC

INTEG

INTC0

INTC1

PA

Unused

FADJL

Unused

Unused

STMDH

44H

45H

46H

59H

5AH

5BH

5CH

5DH

5EH

5FH

OCVPC0

OCVPC1

7FH

: Unused, read as 00H

SLEWC

SLEDC

Unused

Unused

Unused

Unused

Unused

STMAL

Unused

Unused

Unused

PTMC0

PTMC1

OCVPC2

OCVPDA

OCVPOCAL

OCVPCCAL

Unused

Unused

Unused

Unused

CTRL2

CTRL3

Bank 1

Unused

Unused

Unused

Unused

Unused

Unused

Unused

Unused

Unused

Unused

Special Purpose Data Memory Structure




Special Function Register DescriptionMostoftheSpecialFunctionRegisterdetailswillbedescribedintherelevantfunctionalsection.However,severalregistersrequireaseparatedescriptioninthissection.

Indirect Addressing Registers – IAR0, IAR1TheIndirectAddressingRegisters,IAR0andIAR1,althoughhavingtheirlocationsinnormalRAMregisterspace,donotactuallyphysicallyexistasnormalregisters.ThemethodofindirectaddressingforRAMdatamanipulationuses theseIndirectAddressingRegistersandMemoryPointers, incontrasttodirectmemoryaddressing,wheretheactualmemoryaddressisspecified.ActionsontheIAR0andIAR1registerswillresultinnoactualreadorwriteoperationtotheseregistersbutrathertothememorylocationspecifiedbytheircorrespondingMemoryPointers,MP0orMP1.Actingasapair,IAR0andMP0cantogetheraccessdatafromBank0whiletheIAR1andMP1registerpaircanaccessdatafromanybank.AstheIndirectAddressingRegistersarenotphysicallyimplemented,readingtheIndirectAddressingRegistersindirectlywillreturnaresultof"00H"andwritingtotheregistersindirectlywillresultinnooperation.

Memory Pointers – MP0, MP1TwoMemoryPointers, knownasMP0andMP1areprovided.TheseMemoryPointers arephysicallyimplementedintheDataMemoryandcanbemanipulatedinthesamewayasnormalregistersprovidingaconvenientwaywithwhichtoaddressandtrackdata.WhenanyoperationtotherelevantIndirectAddressingRegistersiscarriedout,theactualaddressthatthemicrocontrollerisdirectedtoistheaddressspecifiedbytherelatedMemoryPointer.MP0,togetherwithIndirectAddressingRegister,IAR0,areusedtoaccessdatafromBank0,whileMP1andIAR1areusedtoaccessdatafromallbanksaccordingtoBPregister.DirectAddressingcanonlybeusedwithinBank0,allotherBanksmustbeaddressedindirectlyusingMP1andIAR1.

ThefollowingexampleshowshowtoclearasectionoffourDataMemorylocationsalreadydefinedaslocationsadres1toadres4.

Indirect Addressing Program Exampledata .section ´data´adres1 db ?adres2 db ?adres3 db ?adres4 db ?block db ? code .section at 0 code´org 00hstart: mov a,04h ; setup size of block mov block,a mov a,offset adres1 ; Accumulator loaded with first RAM address mov mp0,a ; setup memory pointer with first RAM addressloop: clr IAR0 ; clear the data at address defined by mp0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loopcontinue:

Theimportantpointtonotehereisthatintheexampleshownabove,noreferenceismadetospecificDataMemoryaddresses.




Bank Pointer – BPFor thisdevice, theDataMemory isdivided into twobanks,Bank0andBank1.Selecting therequiredDataMemoryareaisachievedusingtheBankPointer.Bit0oftheBankPointerisusedtoselectDataMemoryBank0or1.

TheDataMemoryisinitialisedtoBank0afterareset,exceptforaWDTtime-outresetinthePowerdownMode,inwhichcase,theDataMemorybankremainsunaffected.ItshouldbenotedthattheSpecialPurposeDataMemoryisnotaffectedbythebankselection,whichmeansthattheSpecialFunctionRegisterscanbeaccessedfromwithinanybank.DirectlyaddressingtheDataMemorywillalwaysresultinBank0beingaccessedirrespectiveofthevalueoftheBankPointer.AccessingdatafromBank1mustbeimplementedusingIndirectAddressing.

BP Register Bit 7 6 5 4 3 2 1 0

Name — — — — — — — DMBP0R/W — — — — — — — R/WPOR — — — — — — — 0

Bit7~1 Unimplemented,readas"0"Bit0 DMBP0:SelectDataMemoryBanks

0:Bank01:Bank1

Accumulator – ACCTheAccumulator iscentral to theoperationofanymicrocontrollerand isclosely relatedwithoperationscarriedoutby theALU.TheAccumulator is theplacewhereall intermediateresultsfromtheALUarestored.Without theAccumulator itwouldbenecessary towrite theresultofeachcalculationorlogicaloperationsuchasaddition,subtraction,shift,etc., totheDataMemoryresultinginhigherprogrammingandtimingoverheads.Data transferoperationsusually involvethetemporarystoragefunctionoftheAccumulator;forexample,whentransferringdatabetweenoneuser-definedregisterandanother, it isnecessary todo thisbypassing thedata throughtheAccumulatorasnodirecttransferbetweentworegistersispermitted.

Program Counter Low Register – PCLToprovideadditionalprogramcontrolfunctions, the lowbyteof theProgramCounter ismadeaccessibletoprogrammersbylocatingitwithintheSpecialPurposeareaoftheDataMemory.Bymanipulatingthisregister,directjumpstootherprogramlocationsareeasilyimplemented.LoadingavaluedirectlyintothisPCLregisterwillcauseajumptothespecifiedProgramMemorylocation,however,astheregisterisonly8-bitwide,onlyjumpswithinthecurrentProgramMemorypagearepermitted.Whensuchoperationsareused,notethatadummycyclewillbeinserted.




Look-up Table Registers – TBLP, TBHP, TBLHThesethreespecialfunctionregistersareusedtocontroloperationof thelook-uptablewhichisstoredintheProgramMemory.TBLPandTBHParethetablepointersandindicate thelocationwhere the tabledata is located.Theirvaluemustbesetupbeforeany tablereadcommandsareexecuted.Theirvaluecanbechanged,forexampleusingthe"INC"or"DEC"instruction,allowingforeasytabledatapointingandreading.TBLHisthelocationwherethehighorderbyteofthetabledataisstoredafteratablereaddatainstructionhasbeenexecuted.Notethatthelowerordertabledatabyteistransferredtoauserdefinedlocation.

Status Register – STATUSThis8-bitregistercontainsthezeroflag(Z),carryflag(C),auxiliarycarryflag(AC),overflowflag(OV),powerdownflag(PDF),andwatchdogtime-outflag(TO).Thesearithmetic/logicaloperationandsystemmanagementflagsareusedtorecordthestatusandoperationofthemicrocontroller.

WiththeexceptionoftheTOandPDFflags,bitsinthestatusregistercanbealteredbyinstructionslikemostotherregisters.AnydatawrittenintothestatusregisterwillnotchangetheTOorPDFflag.Inaddition,operationsrelatedtothestatusregistermaygivedifferentresultsduetothedifferentinstructionoperations.TheTOflagcanbeaffectedonlybyasystempower-up,aWDTtime-outorbyexecutingthe"CLRWDT"or"HALT"instruction.ThePDFflagisaffectedonlybyexecutingthe"HALT"or"CLRWDT"instructionorduringasystempower-up.

TheZ,OV,ACandCflagsgenerallyreflectthestatusofthelatestoperations.

• Cissetifanoperationresultsinacarryduringanadditionoperationorifaborrowdoesnottakeplaceduringasubtractionoperation;otherwiseCiscleared.Cisalsoaffectedbyarotatethroughcarryinstruction.

• ACissetifanoperationresultsinacarryoutofthelownibblesinaddition,ornoborrowfromthehighnibbleintothelownibbleinsubtraction;otherwiseACiscleared.

• Zissetiftheresultofanarithmeticorlogicaloperationiszero;otherwiseZiscleared.

• OVissetifanoperationresultsinacarryintothehighest-orderbitbutnotacarryoutofthehighest-orderbit,orviceversa;otherwiseOViscleared.

• PDFisclearedbyasystempower-uporexecutingthe"CLRWDT"instruction.PDFissetbyexecutingthe"HALT"instruction.

• TOisclearedbyasystempower-uporexecutingthe"CLRWDT"or"HALT"instruction.TOissetbyaWDTtime-out.

Inaddition,onenteringaninterruptsequenceorexecutingasubroutinecall,thestatusregisterwillnotbepushedontothestackautomatically.Ifthecontentsofthestatusregistersareimportantandifthesubroutinecancorruptthestatusregister,precautionsmustbetakentocorrectlysaveit.




STATUS RegisterBit 7 6 5 4 3 2 1 0

Name — — TO PDF OV Z AC CR/W — — R R R/W R/W R/W R/WPOR — — 0 0 x x x x

"x" unknownBit7~6 Unimplemented,readas"0"Bit5 TO:WatchdogTime-outflag

0:Afterpoweruporexecutingthe"CLRWDT"or"HALT"instruction1:Awatchdogtime-outoccurred.

Bit4 PDF:Powerdownflag0:Afterpoweruporexecutingthe"CLRWDT"instruction1:Byexecutingthe"HALT"instruction

Bit3 OV:Overflowflag0:Nooverflow1:Anoperationresultsinacarryintothehighest-orderbitbutnotacarryoutofthehighest-orderbitorviceversa.

Bit2 Z:Zeroflag0:Theresultofanarithmeticorlogicaloperationisnotzero1:Theresultofanarithmeticorlogicaloperationiszero

Bit1 AC:Auxiliaryflag0:Noauxiliarycarry1:Anoperationresultsinacarryoutofthelownibblesinaddition,ornoborrowfromthehighnibbleintothelownibbleinsubtraction

Bit0 C:Carryflag0:Nocarry-out1:Anoperationresultsinacarryduringanadditionoperationorifaborrowdoesnottakeplaceduringasubtractionoperation

Cisalsoaffectedbyarotatethroughcarryinstruction.




EEPROM Data MemoryOneofthespecialfeaturesinthedeviceisitsinternalEEPROMDataMemory.EEPROM,whichstandsforElectricallyErasableProgrammableReadOnlyMemory,isbyitsnatureanon-volatileformofmemory,withdataretentionevenwhenitspowersupply is removed.Byincorporatingthiskindofdatamemory,awholenewhostofapplicationpossibilitiesaremadeavailabletothedesigner.TheavailabilityofEEPROMstorageallowsinformationsuchasproduct identificationnumbers,calibrationvalues,specificuserdata,systemsetupdataorotherproductinformationtobestoreddirectlywithintheproductmicrocontroller.TheprocessofreadingandwritingdatatotheEEPROMmemoryhasbeenreducedtoaverytrivialaffair.

EEPROM Data Memory StructureTheEEPROMDataMemorycapacityisupto32×8bits.UnliketheProgramMemoryandRAMDataMemory, theEEPROMDataMemoryisnotdirectlymappedandis thereforenotdirectlyaccessible in the samewayas theother typesofmemory.ReadandWriteoperations to theEEPROMarecarriedoutinsinglebyteoperationsusinganaddressanddataregisterinBank0andasinglecontrolregisterinBank1.

EEPROM RegistersThreeregisterscontroltheoveralloperationoftheinternalEEPROMDataMemory.Thesearetheaddressregister,EEA,thedataregister,EEDandasinglecontrolregister,EEC.AsboththeEEAandEEDregistersarelocatedinBank0,theycanbedirectlyaccessedinthesamewayasanyotherSpecialFunctionRegister.TheEECregisterhowever,beinglocatedinBank1,cannotbedirectlyaddresseddirectlyandcanonlybereadfromorwrittentoindirectlyusingtheMP1MemoryPointerandIndirectAddressingRegister,IAR1.BecausetheEECcontrolregisterislocatedataddress40HinBank1,theMP1MemoryPointermustfirstbesettothevalue40HandtheBankPointerregister,BP,settothevalue,01H,beforeanyoperationsontheEECregisterareexecuted.

RegisterName

Bit7 6 5 4 3 2 1 0

EEA — — — D4 D3 D2 D1 D0EED D7 D6 D5 D4 D3 D2 D1 D0EEC — — — — WREN WR RDEN RD

EEPROM Control Register List

EEA RegisterBit 7 6 5 4 3 2 1 0

Name — — — D4 D3 D2 D1 D0R/W — — — R/W R/W R/W R/W R/WPOR — — — 0 0 0 0 0

Bit7~5 Unimplemented,readas"0"Bit4~0 DataEEPROMaddress

DataEEPROMaddressbit4~bit0




EED RegisterBit 7 6 5 4 3 2 1 0

Name D7 D6 D5 D4 D3 D2 D1 D0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~0 DataEEPROMdataDataEEPROMdatabit7~bit0

EEC RegisterBit 7 6 5 4 3 2 1 0

Name — — — — WREN WR RDEN RDR/W — — — — R/W R/W R/W R/WPOR — — — — 0 0 0 0

Bit7~4 Unimplemented,readas"0"Bit3 WREN:DataEEPROMWriteEnable

0:Disable1:Enable

This is theDataEEPROMWriteEnableBitwhichmustbesethighbeforeDataEEPROMwriteoperationsarecarriedout.Clearingthisbit tozerowill inhibitDataEEPROMwriteoperations.

Bit2 WR:EEPROMWriteControl0:Writecyclehasfinished1:Activateawritecycle

This is theDataEEPROMWriteControlBitandwhensethighbytheapplicationprogramwillactivateawritecycle.Thisbitwillbeautomaticallyresettozerobythehardwareafterthewritecyclehasfinished.SettingthisbithighwillhavenoeffectiftheWRENhasnotfirstbeensethigh.

Bit1 RDEN:DataEEPROMReadEnable0:Disable1:Enable

This is theDataEEPROMReadEnableBitwhichmustbesethighbeforeDataEEPROMreadoperationsarecarriedout.Clearingthisbit tozerowill inhibitDataEEPROMreadoperations.

Bit0 RD:EEPROMReadControl0:Readcyclehasfinished1:Activateareadcycle

This is theDataEEPROMReadControlBitandwhensethighbytheapplicationprogramwillactivateareadcycle.Thisbitwillbeautomaticallyresettozerobythehardwareafterthereadcyclehasfinished.SettingthisbithighwillhavenoeffectiftheRDENhasnotfirstbeensethigh.

Note:TheWREN,WR,RDENandRDcannotbesetto"1"atthesametimeinoneinstruction.TheWRandRDcannotbesetto"1"atthesametime.




Reading Data from the EEPROM ToreaddatafromtheEEPROM,thereadenablebit,RDEN,intheEECregistermustfirstbesethightoenablethereadfunction.TheEEPROMaddressofthedatatobereadmustthenbeplacedintheEEAregister.IftheRDbitintheEECregisterisnowsethigh,areadcyclewillbeinitiated.SettingtheRDbithighwillnotinitiateareadoperationif theRDENbithasnotbeenset.Whenthereadcycleterminates,theRDbitwillbeautomaticallyclearedtozero,afterwhichthedatacanbereadfromtheEEDregister.ThedatawillremainintheEEDregisteruntilanotherreadorwriteoperationisexecuted.Theapplicationprogramcanpoll theRDbit todeterminewhenthedataisvalidforreading.

Writing Data to the EEPROMTheEEPROMaddressofthedatatobewrittenmustfirstbeplacedintheEEAregisterandthedataplacedintheEEDregister.TowritedatatotheEEPROM,thewriteenablebit,WREN,intheEECregistermustfirstbesethightoenablethewritefunction.Afterthis,theWRbitintheEECregistermustbe immediatelysethighto initiateawritecycle.These twoinstructionsmustbeexecutedconsecutively.Theglobal interruptbitEMIshouldalsofirstbeclearedbefore implementinganywriteoperations,andthensetagainafterthewritecyclehasstarted.NotethatsettingtheWRbithighwillnotinitiateawritecycleiftheWRENbithasnotbeenset.AstheEEPROMwritecycleiscontrolledusinganinternaltimerwhoseoperationisasynchronoustomicrocontrollersystemclock,acertaintimewillelapsebeforethedatawillhavebeenwrittenintotheEEPROM.DetectingwhenthewritecyclehasfinishedcanbeimplementedeitherbypollingtheWRbitintheEECregisterorbyusingtheEEPROMinterrupt.Whenthewritecycleterminates,theWRbitwillbeautomaticallycleared tozeroby themicrocontroller, informing theuser that thedatahasbeenwritten to theEEPROM.TheapplicationprogramcanthereforepolltheWRbittodeterminewhenthewritecyclehasended.

Write ProtectionProtectionagainst inadvertentwriteoperation isprovided inseveralways.After thedevice ispoweredon, theWriteenablebit in thecontrol registerwillbeclearedpreventinganywriteoperations.Alsoatpower-ontheBankPointer,BP,willbereset tozero,whichmeansthatDataMemoryBank0willbeselected.AstheEEPROMcontrolregisterislocatedinBank1,thisaddsafurthermeasureofprotectionagainstspuriouswriteoperations.Duringnormalprogramoperation,ensuringthattheWriteEnablebitinthecontrolregisterisclearedwillsafeguardagainstincorrectwriteoperations.

EEPROM InterruptTheEEPROMwriteinterruptisgeneratedwhenanEEPROMwritecyclehasended.TheEEPROMinterruptmustfirstbeenabledbysettingtheDEEbitintherelevantinterruptregister.HoweverastheEEPROMiscontainedwithinaMulti-functionInterrupt,theassociatedmulti-functioninterruptenablebitmustalsobeset.WhenanEEPROMwritecycleends, theDEFrequest flagand itsassociatedmulti-functioninterruptrequestflagwillbothbeset.Iftheglobal,EEPROMandMulti-function interruptsareenabledandthestackisnotfull,a jumpto theassociatedMulti-functionInterruptvectorwilltakeplace.WhentheinterruptisservicedonlytheMulti-functioninterruptflagwillbeautomaticallyreset, theEEPROMinterruptflagmustbemanuallyresetbytheapplicationprogram.MoredetailscanbeobtainedintheInterruptsection.




Programming ConsiderationsCaremustbe taken thatdata isnot inadvertentlywritten to theEEPROM.ProtectioncanbePeriodicbyensuringthattheWriteEnablebit isnormallyclearedtozerowhennotwriting.AlsotheBankPointercouldbenormallyclearedtozeroasthiswouldinhibitaccesstoBank1wheretheEEPROMcontrolregisterexist.Althoughcertainlynotnecessary,considerationmightbegivenintheapplicationprogramtothecheckingofthevalidityofnewwritedatabyasimplereadbackprocess.WhenwritingdatatheWRbitmustbesethighimmediatelyaftertheWRENbithasbeensethigh,toensurethewritecycleexecutescorrectly.TheglobalinterruptbitEMIshouldalsobeclearedbeforeawritecycleisexecutedandthenre-enabledafterthewritecyclestarts.NotethatthedeviceshouldnotentertheIDLEorSLEEPmodeuntiltheEEPROMreadorwriteoperationistotallycompleted,otherwise,theEEPROMreadorwriteoperationwillfail.

Programming Examples• Reading data from the EEPROM – polling methodMOV A, EEPROM_ADRES ; user defined addressMOV EEA, AMOV A, 040H ; setup memory pointer MP1MOV MP1, A ; MP1 points to EEC registerMOV A, 01H ; setup Bank PointerMOV BP, ASET IAR1.1 ; set RDEN bit, enable read operationsSET IAR1.0 ; start Read Cycle-set RD bitBACK:SZ IAR1.0 ; check for read cycle endJMP BACKCLR IAR1 ; disable EEPROM writeCLR BPMOV A, EED ; move read data to registerMOV READ_DATA, A

• Writing Data to the EEPROM – polling methodMOV A, EEPROM_ADRES ; user defined addressMOV EEA, AMOV A, EEPROM_DATA ; user defined dataMOV EED, AMOV A, 040H ; setup memory pointer MP1MOV MP1, A ; MP1 points to EEC registerMOV A, 01H ; setup Bank PointerMOV BP, A ; BP points to data memory bank 1CLR EMISET IAR1.3 ; set WREN bit, enable write operationsSET IAR1.2 ; start Write Cycle-set WR bit – executed immediately after ; set WREN bitSET EMIBACK:SZ IAR1.2 ; check for write cycle endJMP BACKCLR IAR1 ; disable EEPROM writeCLR BP




OscillatorsVariousoscillatoroptionsoffer theuserawide rangeof functionsaccording to theirvariousapplication requirements.The flexible featuresof theoscillator functionsensure that thebestoptimisationcanbeachievedintermsofspeedandpowersaving.Oscillatorselectionsandoperationareselectedthroughregisters.

Oscillator OverviewInadditiontobeingthesourceofthemainsystemclocktheoscillatorsalsoprovideclocksourcesfor theWatchdogTimerandTimeBaseInterrupts.Fullyintegratedinternaloscillators,requiringnoexternalcomponents,areprovidedtoformarangeofbothfastandslowsystemoscillators.Thehigherfrequencyoscillatorsprovidehigherperformancebutcarrywithitthedisadvantageofhigherpowerrequirements,whiletheoppositeisofcoursetrueforthelowerfrequencyoscillators.Withthecapabilityofdynamicallyswitchingbetweenfastandslowsystemclock, thedevicehas theflexibilitytooptimizetheperformance/powerratio,afeatureespeciallyimportantinpowersensitiveportableapplications.

Type Name Freq.Internal High Speed RC HIRC 12MHz (adjustable)Internal Low Speed RC LIRC 32kHz

Oscillator Types

System Clock ConfigurationsTherearetwomethodsofgeneratingthesystemclock,ahighspeedinternalRCoscillatorandalowspeedinternalRCoscillator.SelectingwhethertheloworhighspeedoscillatorisusedasthesystemoscillatorisimplementedusingtheHLCLKbitandCKS2~CKS0bitsintheSMODregisterandasthesystemclockcanbedynamicallyselected.

Theactualsourceclockusedforthehighspeedandthelowspeedoscillatorsischosenviaregisters.ThefrequencyoftheslowspeedorhighspeedsystemclockisalsodeterminedusingtheHLCLKbitandCKS2~CKS0bitsintheSMODregister.Notethattwooscillatorselectionsmustbemadenamelyonehighspeedandone lowspeedsystemoscillators. It isnotpossible tochooseano-oscillatorselectionforeitherthehighorlowspeedoscillator.

FrequencyAdjusting

CircuitHIRC Prescaler

fH

LIRC

Low Speed Oscillator

fH/2

fH/16

fH/64

fH/8fH/4

fH/32

HLCLK, CKS[2:0] bits

fSYS

High Speed Oscillator

fSUB

ADJ[8:0] bits

System Clock Configurations




Internal RC Oscillator – HIRCTheinternalhighspeedRCoscillator isafullyintegratedsystemoscillatorrequiringnoexternalcomponents.The internalRCoscillatorhasa frequencyof12MHzwhichcanbeadjustedbychanging theADJ[8:0]bits fieldvalue.Device trimmingduring themanufacturingprocessandthe inclusionof internal frequencycompensationcircuitsareused toensure that the influenceof thepowersupplyvoltage, temperatureandprocessvariationsontheoscillationfrequencyareminimised.Notethatifthisinternalsystemclockoptionisselected,itrequiresnoexternalpinsforitsoperation.

TheADJ[8:0]bitfieldintheFADJHandFADJLregisters isusedtoadjust theHIRCoscillationfrequency.TheHIRCoscillator is supposed tohavea frequencyof12MHzwith thedefaultADJ[8:0] fieldvalue,100000000B.Thegreatervalue theADJ[8:0] field iswritten, the lowerfrequencytheHIRCoscillatorhas.TheHIRCoscillatorwillhaveamaximumadjustedfrequencywhentheADJ[8:0]fieldissetto000000000B.NotethatacertaintimedelayfortheHIRCoscillatorstabilizationshouldbeallowedwhentheHIRCoscillationfrequencyischangedbyconfiguringtheADJ[8:0]field.ThenewHIRCfrequencycannotbeuseduntiltheupdatedfrequencyisstable.

FADJL RegisterBit 7 6 5 4 3 2 1 0

Name ADJ7 ADJ6 ADJ5 ADJ4 ADJ3 ADJ2 ADJ1 ADJ0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~0 ADJ7~ADJ0:HIRCfrequencyadjustmentcontrolbit7~bit0

FADJH RegisterBit 7 6 5 4 3 2 1 0

Name — — — — — — — ADJ8R/W — — — — — — — R/WPOR — — — — — — — 1

Bit7~1 Unimplemented,readas"0"Bit0 ADJ8:HIRCfrequencyadjustmentcontrolbit8

Internal 32kHz Oscillator – LIRCTheInternal32kHzsystemoscillator is the lowfrequencyoscillator. It isafully integratedRCoscillatorwitha typical frequencyof32kHzat5V, requiringnoexternalcomponents for itsimplementation.Devicetrimmingduringthemanufacturingprocessandtheinclusionof internalfrequencycompensationcircuitsareusedtoensurethattheinfluenceofthepowersupplyvoltage,temperatureandprocessvariationsontheoscillationfrequencyareminimised.




Operating Modes and System ClocksPresentdayapplicationsrequirethat theirmicrocontrollershavehighperformancebutoftenstilldemandthattheyconsumeaslittlepoweraspossible,conflictingrequirementsthatareespeciallytrueinbatterypoweredportableapplications.Thefastclocksrequiredforhighperformancewillbytheirnatureincreasecurrentconsumptionandofcoursevice-versa, lowerspeedclocksreducecurrentconsumption.AsHoltekhasprovided thisdevicewithbothhighand lowspeedclocksourcesandthemeanstoswitchbetweenthemdynamically,theusercanoptimisetheoperationoftheirmicrocontrollertoachievethebestperformance/powerratio.

System ClocksThedevicehasmanydifferentclocksourcesforboththeCPUandperipheralfunctionoperation.Byprovidingtheuserwithawiderangeofclockoptionsusingregisterprogramming,aclocksystemcanbeconfiguredtoobtainmaximumapplicationperformance.

Themainsystemclock,cancomefromeitherahighfrequencyfHor lowfrequencyfSUBsource,andisselectedusingtheHLCLKbitandCKS2~CKS0bitsintheSMODregister.ThehighspeedsystemclockcanbesourcedfromtheHIRCoscillator.ThelowspeedsystemclocksourcecanbesourcedfromtheLIRCoscillator.Theotherchoice,whichisadividedversionofthehighspeedsystemoscillatorhasarangeoffH/2~fH/64.

FrequencyAdjusting

CircuitHIRC Prescaler

fH

LIRC

Low Speed Oscillator

fH/2

fH/16

fH/64

fH/8fH/4

fH/32

HLCLK, CKS[2:0] bits

fSYS

High Speed Oscillator

fSUB

ADJ[8:0] bits

WDT

TimeBase

TBCK

fSYS/4

To peripherals

fS

fTB

fSUB

fTBC

Device Clock Configurations

Note:WhenthesystemclocksourcefSYSisswitchedtofSUBfromfH,thehighspeedoscillatorwillstoptoconservethepower.ThusthereisnofH~fH/64forperipheralcircuittouse.




System Operating ModesThere are six differentmodesof operation for themicrocontroller, eachonewith its ownspecial characteristics andwhichcanbe chosenaccording to the specificperformanceandpowerrequirementsof theapplication.Thereare twomodesallowingnormaloperationof themicrocontroller, theNORMALModeandSLOWMode.Theremainingfourmodes,theSLEEP0,SLEEP1, IDLE0andIDLE1Modeareusedwhen themicrocontrollerCPUisswitchedoff toconservepower.

OperatingMode

DescriptionCPU fSYS fH fSUB

NORMAL Mode On fH~fH/64 On OnSLOW Mode On fSUB Off OnILDE0 Mode Off Off Off OnIDLE1 Mode Off On On/Off OnSLEEP0 Mode (Note) Off Off Off OffSLEEP1 Mode Off Off Off On

Note:IftheWatchdogTimerconfigurationoptionis"Alwaysenabled"whichmeansthefSUBclockmustalwaysbeon,thereisnotSLEEP0mode.

NORMAL ModeAsthenamesuggeststhisisoneofthemainoperatingmodeswherethemicrocontrollerhasallofitsfunctionsoperationalandwherethesystemclockisprovidedbythehighspeedoscillator.Thismodeoperatesallowingthemicrocontrollertooperatenormallywithaclocksourcewillcomefromthehighspeedoscillator,HIRC.Thehighspeedoscillatorwillhoweverfirstbedividedbyaratiorangingfrom1to64,theactualratiobeingselectedbytheCKS2~CKS0andHLCLKbitsintheSMODregister.Althoughahighspeedoscillatorisused,runningthemicrocontrolleratadividedclockratioreducestheoperatingcurrent.

SLOW ModeThisisalsoamodewherethemicrocontrolleroperatesnormallyalthoughnowwithaslowerspeedclocksource.TheclocksourceusedwillbefromfSUB.Runningthemicrocontroller inthismodeallowsittorunwithmuchloweroperatingcurrents.IntheSLOWMode,thefHisoff.

SLEEP0 ModeIf theWDTconfigurationoption is"Alwaysenabled", there isnotSLEEP0mode.If theWDTconfigurationoptionis"controlledbyWDTCregister"theMCUcanentertheSLEEP0mode.TheSLEEPModeisenteredwhenanHALTinstruction isexecutedandwhentheIDLENbit in theSMODregister is low.IntheSLEEP0modetheCPUwillbestopped,andthefSUBandfSclockswillbestoppedtoo,andtheWatchdogTimerfunctionisdisabled.Inthismode,theLVDENismustclearedtozero.IftheLVDENissethigh,itwon’tentertheSLEEP0Mode.

SLEEP1 ModeTheSLEEPModeisenteredwhenanHALTinstruction isexecutedandwhentheIDLENbit intheSMODregisterislow.IntheSLEEP1modetheCPUwillbestopped.HoweverthefSUBandfSclockswillcontinuetooperateiftheLVDENis"1"ortheWatchdogTimerfunctionisenabled.

IDLE0 ModeTheIDLE0ModeisenteredwhenaHALTinstructionisexecutedandwhentheIDLENbitintheSMODregisterishighandtheFSYSONbitintheCTRLregisterislow.IntheIDLE0ModethesystemoscillatorwillbeinhibitedfromdrivingtheCPU,thesystemoscillatorwillbestopped,thelowfrequencyclockfSUBwillbeontodrivesomeperipheralfunctions.




IDLE1 ModeTheIDLE1ModeisenteredwhenaHALTinstructionisexecutedandwhentheIDLENbitintheSMODregisterishighandtheFSYSONbitintheCTRLregisterishigh.IntheIDLE1ModethesystemoscillatorwillbeinhibitedfromdrivingtheCPU,thesystemoscillatorwillcontinuetorun,andthissystemoscillatormaybehighspeedorlowspeedsystemoscillator.IntheIDLE1ModethelowfrequencyclockfSUBwillbeontodrivesomeperipheralfunctions.

Note:IfLVDEN=1andtheSLEEPorIDLEmodeisentered,theLVDandbandgapfunctionswillnotbedisabled,andthefSUBclockwillbeforcedtobeenabled.

Control RegistersTheSMODandCTRLregistersareusedtocontroltheinternalclockswithinthedevice.

SMOD RegisterBit 7 6 5 4 3 2 1 0

Name CKS2 CKS1 CKS0 — LTO HTO IDLEN HLCLKR/W R/W R/W R/W — R R R/W R/WPOR 1 1 0 — 0 0 1 0

Bit7~5 CKS2 ~ CKS0:ThesystemclockselectionwhenHLCLKis"0"000:fSUB001:fSUB010:fH/64011:fH/32100:fH/16101:fH/8110:fH/4111:fH/2

Thesethreebitsareusedtoselectwhichclockisusedasthesystemclocksource.Inadditiontothesystemclocksource,whichcanbeLIRC,adividedversionofthehighspeedsystemoscillatorcanalsobechosenasthesystemclocksource.

Bit4 Unimplemented,readas"0"Bit3 LTO:LIRCSystemOSCSSTreadyflag

0:Notready1:Ready

ThisisthelowspeedsystemoscillatorSSTreadyflagwhichindicateswhenthelowspeedsystemoscillatorisstableafterpoweronresetorawake-uphasoccurred.Theflagwillchangetoahighlevelafter1~2cycles.

Bit2 HTO:HIRCSystemOSCSSTreadyflag0:Notready1:Ready

ThisisthehighspeedsystemoscillatorSSTreadyflagwhichindicateswhenthehighspeedsystemoscillatorisstableafterawake-uphasoccurred.Thisflagisclearedto"0"byhardwarewhenthedeviceispoweredonandthenchangestoahighlevelafterthehighspeedsystemoscillatorisstable.Thereforethisflagwillalwaysbereadas"1"bytheapplicationprogramafterdevicepower-on.TheflagwillbelowwhenintheSLEEPorIDLE0Modebutafterpoweronresetorawake-uphasoccurred,theflagwillchangetoahighlevelafter15~16clockcyclesiftheHIRCoscillatorisused.




Bit1 IDLEN:IDLEModeControl0:Disable1:Enable

This is theIDLEModeControlbitanddetermineswhathappenswhentheHALTinstructionisexecuted.If thisbit ishigh,whenaHALTinstructionisexecutedthedevicewillenter theIDLEMode. In theIDLE1Mode theCPUwillstoprunningbut thesystemclockwillcontinue tokeep theperipheral functionsoperational, ifFSYSONbitishigh.IfFSYSONbitislow,theCPUandthesystemclockwillallstopinIDLE0mode.IfthebitislowthedevicewillentertheSLEEPModewhenaHALTinstructionisexecuted.

Bit0 HLCLK:SystemClockSelection0:fH/2~fH/64orfSUB

1:fH

ThisbitisusedtoselectifthefHclockorthefH/2~fH/64orfSUBclockisusedasthesystemclock.WhenthebitishighthefHclockwillbeselectedandiflowthefH/2~fH/64orfSUBclockwillbeselected.WhensystemclockswitchesfromthefHclocktothefSUBclockandthefHclockwillbeautomaticallyswitchedofftoconservepower.

CTRL Register Bit 7 6 5 4 3 2 1 0

Name FSYSON — — — — LVRF LRF WRFR/W R/W — — — — R/W R/W R/WPOR 0 — — — — x 0 0

"x" unknownBit7 FSYSON:fSYSControlinIDLEMode

0:Disable1:Enable

Bit6~3 Unimplemented,readas"0"Bit2 LVRF:LVRfunctionresetflag

DescribedelsewhereBit1 LRF:LVRCcontrolregistersoftwareresetflag

DescribedelsewhereBit0 WRF:WDTCcontrolregistersoftwareresetflag

Describedelsewhere




Operating Mode Switching Thedevicecanswitchbetweenoperatingmodesdynamicallyallowingtheusertoselect thebestperformance/powerratiofor thepresent taskinhand.Inthiswaymicrocontrolleroperationsthatdonotrequirehighperformancecanbeexecutedusingslowerclocksthusrequiringlessoperatingcurrentandprolongingbatterylifeinportableapplications.

Insimple terms,ModeSwitchingbetween theNORMALModeandSLOWMode isexecutedusingtheHLCLKbitandCKS2~CKS0bitsintheSMODregisterwhileModeSwitchingfromtheNORMAL/SLOWModestotheSLEEP/IDLEModesisexecutedviatheHALTinstruction.WhenaHALTinstructionisexecuted,whetherthedeviceenterstheIDLEModeortheSLEEPModeisdeterminedbytheconditionof theIDLENbit in theSMODregisterandFSYSONintheCTRLregister.

WhentheHLCLKbitswitchestoalowlevel,whichimpliesthatclocksourceisswitchedfromthehighspeedclocksource,fH,totheclocksource,fH/2~fH/64orfSUB.IftheclockisfromthefSUB,thehighspeedclocksourcewillstoprunningtoconservepower.WhenthishappensitmustbenotedthatthefH/16andfH/64internalclocksourceswillalsostoprunning,whichmayaffecttheoperationofotherinternalfunctionssuchastheTMs.Theaccompanyingflowchartshowswhathappenswhenthedevicemovesbetweenthevariousoperatingmodes.

NORMALfSYS=fH~fH/64

fH onCPU runfSYS onfSUB on

IDLE1HALT instruction executed

CPU stopIDLEN=1

FSYSON=1fSYS onfSUB on

IDLE0HALT instruction executed

CPU stopIDLEN=1

FSYSON=0fSYS offfSUB on

SLOWfSYS=fSUBfSUB on

CPU runfSYS onfSUB onfH off

SLEEP1HALT instruction executed

fSYS offCPU stopIDLEN=0fSUB on

WDT or LVD on

SLEEP0HALT instruction executed

fSYS offCPU stopIDLEN=0fSUB off

WDT & LVD off

Note:IftheWatchdogTimerconfigurationoptionis"Alwaysenabled"whichmeansthefSUBclockmustalwaysbeon,thereisnotSLEEP0mode.




NORMAL Mode to SLOW Mode SwitchingWhenrunningintheNORMALMode,whichusesthehighspeedsystemoscillator,andthereforeconsumesmorepower, thesystemclockcanswitch to run in theSLOWModebysetting theHLCLKbitto"0"andsettingtheCKS2~CKS0bitsto"000"or"001"intheSMODregister.Thiswillthenusethelowspeedsystemoscillatorwhichwillconsumelesspower.Usersmaydecidetodothisforcertainoperationswhichdonotrequirehighperformanceandcansubsequentlyreducepowerconsumption.

TheSLOWModeissourcedfromtheLIRCoscillatorandthereforerequiresthisoscillator tobestablebeforefullmodeswitchingoccurs.ThisismonitoredusingtheLTObitintheSMODregister.

NORMAL Mode

SLOW Mode

CKS2~CKS0 = 00xB &HLCLK = 0

SLEEP0 Mode

IDLEN=0HALT instruction is executed

SLEEP1 Mode

IDLE0 Mode

IDLE1 Mode

WDT and LVD are all off


WDT or LVD is on

IDLEN=1, FSYSON=0HALT instruction is executed





SLOW Mode to NORMAL Mode Switching InSLOWModethesystemusesLIRClowspeedsystemoscillator.ToswitchbacktotheNORMALMode,where thehighspeedsystemoscillator isused, theHLCLKbit shouldbeset to"1"orHLCLKbitis"0",butCKS2~CKS0issetto"010","011","100","101","110"or"111".Asacertainamountoftimewillberequiredforthehighfrequencyclocktostabilise,thestatusoftheHTObitischecked.Theamountoftimerequiredforhighspeedsystemoscillatorstabilizationdependsuponwhichhighspeedsystemoscillatortypeisused.

NORMAL Mode

SLOW Mode

CKS2~CKS0 ≠ 000B or 001B as HLCLK = 0 or HLCLK = 1

SLEEP0 Mode


SLEEP1 Mode

IDLE0 Mode

IDLE1 Mode

WDT and LVD are all off


WDT or LVD is on



Entering the SLEEP0 ModeThereisonlyonewayforthedevicetoentertheSLEEP0Modeandthatistoexecutethe"HALT"instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto"0"andtheWDTandLVDarebothoff.Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:

• ThesystemclockandthefSUBclockwillbestoppedandtheapplicationprogramwillstopatthe"HALT"instruction.

• TheDataMemorycontentsandregisterswillmaintaintheirpresentcondition.

• TheWDTwillbeclearedandstopped.

• TheI/Oportswillmaintaintheirpresentconditions.

• Inthestatusregister,thePowerDownflag,PDF,willbesetandtheWatchdogtime-outflag,TO,willbecleared.




Entering the SLEEP1 ModeThereisonlyonewayforthedevicetoentertheSLEEP1Modeandthatistoexecutethe"HALT"instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto"0"andtheWDTorLVDison.Whenthis instructionisexecutedundertheconditionsdescribedabove, thefollowingwilloccur:

• Thesystemclockwillbestoppedandtheapplicationprogramwillstopatthe"HALT"instructionbuttheWDTorLVDwillremainwiththeclocksourcecomingwiththefSUBclock.


• TheWDTwillbeclearedandresumecountingastheWDTisenabled.



Entering the IDLE0 ModeThereisonlyonewayforthedevicetoentertheIDLE0Modeandthatistoexecutethe"HALT"instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto"1"andtheFSYSONbitinCTRLregisterequalto"0".Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:

• Thesystemclockwillbestoppedandtheapplicationprogramwillstopatthe"HALT"instruction,butthelowfrequencyfSUBclockwillbeon.


• TheWDTwillbeclearedandresumecounting.

• TheI/Oportswillmaintaintheirpresentconditionsasitisenabled.


Entering the IDLE1 ModeThereisonlyonewayforthedevicetoentertheIDLE1Modeandthatistoexecutethe"HALT"instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto"1"andtheFSYSONbitinCTRLregisterequalto"1".Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:

• ThesystemclockandthelowfrequencyfSUBwillbeonandtheapplicationprogramwillstopatthe"HALT"instruction.


• TheWDTwillbeclearedandresumecountingasitisenabled.






Standby Current ConsiderationsAsthemainreasonforenteringtheSLEEPorIDLEModeistokeepthecurrentconsumptionofthedevicetoaslowavalueaspossible,perhapsonlyintheorderofseveralmicro-ampsexceptintheIDLE1Mode,thereareotherconsiderationswhichmustalsobetakenintoaccountbythecircuitdesignerifthepowerconsumptionistobeminimised.SpecialattentionmustbemadetotheI/Opinsonthedevice.Allhigh-impedanceinputpinsmustbeconnectedtoeitherafixedhighorlowlevelasanyfloatinginputpinscouldcreateinternaloscillationsandresultinincreasedcurrentconsumption.Thisalsoappliestodeviceswhichhavedifferentpackagetypes,astheremaybeunbonbedpins.Thesemusteitherbesetupasoutputsorifsetupasinputsmusthavepull-highresistorsconnected.

Caremustalsobe takenwith the loads,whichareconnected to I/Opins,whichare setupasoutputs.Theseshouldbeplacedinaconditioninwhichminimumcurrent isdrawnorconnectedonlytoexternalcircuitsthatdonotdrawcurrent,suchasotherCMOSinputs.IntheIDLE1Modethesystemoscillator ison, if thesystemoscillator is fromthehighspeedsystemoscillator, theadditionalstandbycurrentwillalsobeperhapsintheorderofseveralhundredmicro-amps.

Wake-upAfterthesystementerstheSLEEPorIDLEMode,itcanbewokenupfromoneofvarioussourceslistedasfollows:

• AnexternalfallingedgeonPortA

• Asysteminterrupt

• AWDToverflow

IfthedeviceiswokenupbyaWDToverflow,aWatchdogTimerresetwillbeinitiated.Theactualsourceof thewake-upcanbedeterminedbyexaminingtheTOandPDFflags.ThePDFflagisclearedbyasystempower-uporexecutingtheclearWatchdogTimerinstructionsandissetwhenexecutingthe"HALT"instruction.TheTOflagissetifaWDTtime-outoccurs,andcausesawake-upthatonlyresetstheProgramCounterandStackPointer,theotherflagsremainintheiroriginalstatus.

EachpinonPortAcanbesetupusingthePAWUregistertopermitanegativetransitiononthepintowake-upthesystem.WhenaPortApinwake-upoccurs,theprogramwillresumeexecutionattheinstructionfollowingthe"HALT"instruction.If thesystemiswokenupbyaninterrupt, thentwopossiblesituationsmayoccur.Thefirstiswheretherelatedinterruptisdisabledortheinterruptisenabledbutthestackisfull,inwhichcasetheprogramwillresumeexecutionattheinstructionfollowingthe"HALT"instruction.Inthissituation,theinterruptwhichwoke-upthedevicewillnotbeimmediatelyserviced,butwillratherbeservicedlaterwhentherelatedinterruptisfinallyenabledorwhenastacklevelbecomesfree.Theothersituationiswheretherelatedinterruptisenabledandthestackisnotfull,inwhichcasetheregularinterruptresponsetakesplace.Ifaninterruptrequestflag issethighbeforeentering theSLEEPorIDLEMode, thewake-upfunctionof therelatedinterruptwillbedisabled.




Watchdog TimerTheWatchdogTimerisprovidedtopreventprogrammalfunctionsorsequencesfromjumpingtounknownlocations,duetocertainuncontrollableexternaleventssuchaselectricalnoise.

Watchdog Timer Clock SourceTheWatchdogTimerclocksource isprovidedbythe internalfSclockwhichis in turnsuppliedbytheLIRCoscillator.TheWatchdogTimersourceclockis thensubdividedbyaratioof28 to218 togivelongertimeouts,theactualvaluebeingchosenusingtheWS2~WS0bitsintheWDTCregister.TheLIRCinternaloscillatorhasanapproximateperiodof32kHzatasupplyvoltageof5V.However,itshouldbenotedthatthisspecifiedinternalclockperiodcanvarywithVDD,temperatureandprocessvariations.

Watchdog Timer Control RegisterAsingle register,WDTC,controls the required timeoutperiodaswell as theenable/disableoperation.ThisregistertogetherwiththeconfigurationoptioncontroltheoveralloperationoftheWatchdogTimer.

WDTC RegisterBit 7 6 5 4 3 2 1 0

Name WE4 WE3 WE2 WE1 WE0 WS2 WS1 WS0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 1 0 1 0 0 1 1

Bit7~3 WE4~WE0:WDTfunctionenable/disablecontrolIftheWDTconfigurationoptionis"Alwaysenabled":10101or01010:EnableOthers:ResetMCU

IftheWDTconfigurationoptionis"ControlledbyWDTCregister":10101:Disable01010:EnableOthers:ResetMCU

Whenthesebitsarechangedbytheenvironmentalnoiseorsoftwaresettingtoresetthemicrocontroller,theresetoperationwillbeactivatedafteradelaytime,tSRESETandtheWRFbitintheCTRLregisterwillbesethigh.

Bit2~0 WS2~WS0:WDTtime-outperiodselection000:28/fS

001:210/fS

010:212/fS

011:214/fS

100:215/fS

101:216/fS

110:217/fS

111:218/fS

These threebitsdetermine thedivisionratioof theWatchdogTimersourceclock,whichinturndeterminesthetimeoutperiod.




CTRL RegisterBit 7 6 5 4 3 2 1 0

Name FSYSON — — — — LVRF LRF WRFR/W R/W — — — — R/W R/W R/WPOR 0 — — — — x 0 0


Describedelsewhere.Bit6~3 Unimplemented,readas"0"Bit2 LVRF:LVRfunctionresetflag

Describedelsewhere.Bit1 LRF:LVRCControlregistersoftwareresetflag

Describedelsewhere.Bit0 WRF:WDTCControlregistersoftwareresetflag

0:Notoccur1:Occurred

Thisbit issethighbytheWDTControlregistersoftwareresetandclearedbytheapplicationprogram.Notethatthisbitcanonlybeclearedtozerobytheapplicationprogram.

Watchdog Timer OperationTheWatchdogTimeroperatesbyprovidingadeviceresetwhenits timeroverflows.ThismeansthatintheapplicationprogramandduringnormaloperationtheuserhastostrategicallycleartheWatchdogTimerbeforeitoverflowstopreventtheWatchdogTimerfromexecutingareset.Thisisdoneusingtheclearwatchdoginstructions.Iftheprogrammalfunctionsforwhateverreason,jumpstoanunknownlocation,orentersanendlessloop,theseclearinstructionswillnotbeexecutedinthecorrectmanner,inwhichcasetheWatchdogTimerwilloverflowandresetthedevice.WithregardtotheWatchdogTimerenable/disablefunction,therearealsofivebits,WE4~WE0,intheWDTCregister toofferadditionalenable/disableandresetcontrolof theWatchdogTimer. If theWDTconfigurationoption is that theWDTfunction isalwaysenabled, theWE4~WE0bitsstillhaveeffectsontheWDTfunction.WhentheWE4~WE0bitsvalueisequalto01010Bor10101B,theWDTfunctionisenabled.However,iftheWE4~WE0bitsarechangedtoanyothervaluesexcept01010Band10101B,whichiscausedbytheenvironmentalnoiseorsoftwaresetting,itwillresetthemicrocontrollerafter2~3fSUBclockcycles.If theWDTconfigurationoptionis that theWDTfunctioniscontrolledbytheWDTCregister,theWE4~WE0valuescandeterminewhichmodetheWDToperatesin.TheWDTfunctionwillbedisabledwhentheWE4~WE0bitsaresettoavalueof10101B.TheWDTfunctionwillbeenablediftheWE4~WE0bitsvalueisequalto01010B.IftheWE4~WE0bitsaresettoanyothervaluesexcept01010Band10101Bbytheenvironmentalnoiseorsoftwaresetting,itwillresetthedeviceafter2~3fSUBclockcycles.Afterpoweronthesebitswillhavethevalueof01010B.

WDT Configuration Option WE4 ~ WE0 Bits WDT Function

Always Enabled01010B or 10101B EnableAny other values Reset MCU

Controlled by WDTC Register10101B Disable01010B Enable

Any other values Reset MCU

Watchdog Timer Enable/Disable Control




Undernormalprogramoperation,aWatchdogTimertime-outwill initialiseadeviceresetandsetthestatusbitTO.However,ifthesystemisintheSLEEPorIDLEMode,whenaWatchdogTimertime-outoccurs,theTObitinthestatusregisterwillbesetandonlytheProgramCounterandStackPointerwillbereset.ThreemethodscanbeadoptedtoclearthecontentsoftheWatchdogTimer.ThefirstisaWDTreset,whichmeansacertainvalueexcept01010Band10101BwrittenintotheWE4~WE0bitfiled, thesecondisusingtheWatchdogTimersoftwareclear instructionsandthethirdisviaaHALTinstruction.

ThereisonlyonemethodofusingsoftwareinstructiontocleartheWatchdogTimer.Thatistousethesingle"CLRWDT"instructiontocleartheWDT.

Themaximumtimeoutperiod iswhenthe218divisionratio isselected.Asanexample,witha32kHzLIRCoscillatorasitssourceclock,thiswillgiveamaximumwatchdogperiodofaround8secondforthe218divisionratio,andaminimumtimeoutof7.8msforthe28divisionration.

“CLR WDT” Instruction

WE4~WE0 bitsWDTC Register Reset MCU

CLR

“HALT” Instruction

fSLIRC 8-stage Divider WDT PrescalerfS/28

8-to-1 MUXWS2~WS0

WDT Time-out

Watchdog Timer




Reset and InitialisationAresetfunctionisafundamentalpartofanymicrocontrollerensuringthat thedevicecanbesettosomepredeterminedcondition irrespectiveofoutsideparameters.Themost important resetconditionisafterpowerisfirstappliedtothemicrocontroller.Inthiscase, internalcircuitrywillensure that themicrocontroller,afterashortdelay,willbe inawelldefinedstateandready toexecutethefirstprograminstruction.Afterthispower-onreset,certainimportantinternalregisterswillbesettodefinedstatesbeforetheprogramcommences.OneoftheseregistersistheProgramCounter,whichwillberesettozeroforcingthemicrocontrollertobeginprogramexecutionfromthelowestProgramMemoryaddress.

Another typeofreset iswhentheWatchdogTimeroverflowsandresets themicrocontroller.Alltypesofresetoperationsresultindifferentregisterconditionsbeingsetup.AnotherresetexistsintheformofaLowVoltageReset,LVR,whereafullresetisimplementedinsituationswherethepowersupplyvoltagefallsbelowacertainthreshold.

Reset FunctionsThereare severalways inwhichamicrocontroller resetcanoccur, througheventsoccurringinternally:

Power-on ResetThemostfundamentalandunavoidablereset is theonethatoccursafterpowerisfirstappliedtothemicrocontroller.AswellasensuringthattheProgramMemorybeginsexecutionfromthefirstmemoryaddress,apower-onresetalsoensures thatcertainother registersarepreset toknownconditions.AlltheI/Oportandportcontrolregisterswillpowerupinahighconditionensuringthatallpinswillbefirstsettoinputs.

VDD

Power-on Reset

SST Time-out

tRSTD

Power-On Reset Timing Chart

Low Voltage Reset – LVRThemicrocontrollercontainsalowvoltageresetcircuitinordertomonitorthesupplyvoltageofthedevice.TheLVRfunctionisalwaysenabledwithaspecificLVRvoltage,VLVR.Ifthesupplyvoltageofthedevicedropstowithinarangeof0.9V~VLVRsuchasmightoccurwhenchangingthebattery,theLVRwillautomaticallyresetthedeviceinternallyandtheLVRFbitintheCTRLregisterwillalsobesethigh.ForavalidLVRsignal,alowvoltage,i.e.,avoltageintherangebetween0.9V~VLVRmustexistforgreaterthanthevaluetLVRspecifiedintheLVD&LVRcharacteristicstable.Ifthelowvoltagestatedoesnotexceedthisvalue,theLVRwill ignorethelowsupplyvoltageandwillnotperformaresetfunction.

TheactualVLVRisdefinedbytheLVS7~LVS0bits intheLVRCregister.If theLVS7~LVS0bitsarechangedtoanyothervalueexceptsomecertainvaluesdefinedin theLVRCregisterby theenvironmentalnoise,theLVRwillresetthedeviceafter2~3LIRCclockcycles.Whenthishappens,theLRFbitintheCTRLregisterwillbesethigh.Afterpowerontheregisterwillhavethevalueof01010101B.NotethattheLVRfunctionwillbeautomaticallydisabledwhenthedeviceentersthepowerdownmode.




LVR

Internal ResettRSTD + tSST

Note:tRSTDispower-ondelay,typicaltime=50msLow Voltage Reset Timing Chart

• LVRC Register

Bit 7 6 5 4 3 2 1 0Name LVS7 LVS6 LVS5 LVS4 LVS3 LVS2 LVS1 LVS0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 1 0 1 0 1 0 1

Bit7~0 LVS7 ~ LVS0:LVRVoltageSelectcontrol01010101:2.1V00110011:2.55V10011001:3.15V10101010:3.8VOthervalues:MCUreset–registerisresettoPORvalue

Whenanactuallowvoltageconditionoccurs,anMCUresetwillbegenerated.Theresetoperationwillbeactivatedafter the lowvoltageconditionkeepsmorethanatLVRtime.Inthissituationthisregistercontentswillremainthesameaftersucharesetoccurs.Any registervalue,other than thedefinedvalues above,will also result in thegenerationofanMCUreset.Theresetoperationwillbeactivatedafteradelaytime,tSRESET.HoweverinthissituationthisregistercontentswillberesettothePORvalue.

• CTRL Register

Bit 7 6 5 4 3 2 1 0Name FSYSON — — — — LVRF LRF WRFR/W R/W — — — — R/W R/W R/WPOR 0 — — — — x 0 0


DescribedelsewhereBit6~3 Unimplemented,readas"0"Bit2 LVRF:LVRfunctionresetflag

0:Notoccurred1:Occurred

Thisbitissethighwhenaspecificlowvoltageresetsituationconditionoccurs.Thisbitcanonlybeclearedtozerobyapplicationprogram.

Bit1 LRF:LVRCcontrolregistersoftwareresetflag0:Notoccurred1:Occurred

Thisbit issethighwhen theLVRCregistercontainsanyundefinedLVRvoltageregistervalue.Thisineffectactslikeasoftwareresetfunction.Thisbitcanonlybeclearedtozerobyapplicationprogram.

Bit0 WRF:WDTCcontrolregistersoftwareresetflagDescribedelsewhere




Watchdog Time-out Reset during Normal OperationTheWatchdogtime-outResetduringnormaloperationisthesameasaLVRresetexceptthattheWatchdogtime-outflagTOwillbesethigh.

WDT Time-out

Internal Reset

tRSTD + tSST

WDT Time-out Reset during Normal Operation Timing Chart

Watchdog Time-out Reset during SLEEP or IDLE ModeTheWatchdogtime-outResetduringSLEEPorIDLEModeisa littledifferentfromotherkindsofreset.MostoftheconditionsremainunchangedexceptthattheProgramCounterandtheStackPointerwillbeclearedtozeroandtheTOflagwillbesethigh.RefertotheA.C.CharacteristicsfortSSTdetails.

WDT Time-out

Internal ResettSST

WDT Time-out Reset during SLEEP or IDLE Timing Chart

Reset Initial ConditionsThedifferent typesofresetdescribedaffect theresetflagsindifferentways.Theseflags,knownasPDFandTOare located in thestatus registerandarecontrolledbyvariousmicrocontrolleroperations,suchas theSLEEPorIDLEModefunctionorWatchdogTimer.Thereset flagsareshowninthetable:

TO PDF RESET Conditions0 0 Power-on resetu u LVR reset during NORMAL or SLOW Mode operation1 u WDT time-out reset during NORMAL or SLOW Mode operation1 1 WDT time-out reset during IDLE or SLEEP Mode operation

Note:"u"standsforunchanged

Thefollowingtableindicatesthewayinwhichthevariouscomponentsofthemicrocontrollerareaffectedafterapower-onresetoccurs.

Item Condition After RESETProgram Counter Reset to zeroInterrupts All interrupts will be disabledWDT Clear after reset, WDT begins countingTimer Modules Timer Modules will be turned offInput/Output Ports I/O ports will be setup as inputs Stack Pointer Stack Pointer will point to the top of the stack




Thedifferentkindsofresetsallaffecttheinternalregistersofthemicrocontrollerindifferentways.Toensurereliablecontinuationofnormalprogramexecutionafteraresetoccurs,itisimportanttoknowwhatconditionthemicrocontrolleris inafteraparticularresetoccurs.Thefollowingtabledescribeshoweachtypeofresetaffectseachofthemicrocontrollerinternalregisters.

Register Reset(Power On)

WDT Time-out(Normal Operation)

WDT Time-out(SLEEP/IDLE)

MP0 x x x x x x x x u u u u u u u u u u u u u u u uMP1 x x x x x x x x u u u u u u u u u u u u u u u uBP - - - - - - - 0 - - - - - - - 0 - - - - - - - uACC x x x x x x x x u u u u u u u u u u u u u u u uPCL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TBLP x x x x x x x x u u u u u u u u u u u u u u u uTBLH x x x x x x x x u u u u u u u u u u u u u u u uTBHP - - - - - x x x - - - - - u u u - - - - - u u uSTATUS - - 0 0 x x x x - - 1 u u u u u - - 1 1 u u u uSMOD 11 0 - 0 0 1 0 11 0 - 0 0 1 0 u u u - u u u uLVDC - - 0 0 - 0 0 0 - - 0 0 - 0 0 0 - - u u - u u uINTEG - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - u u u uINTC0 - - 0 0 - 0 0 0 - - 0 0 - 0 0 0 - - u u - u u uINTC1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uINTC2 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - u u - - u uMFI0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - u u - - u uMFI1 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - u u - - u uPA 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u uPAC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u uPAPU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uPAWU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uMFI2 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - u u - - u uWDTC 0 1 0 1 0 0 11 0 1 0 1 0 0 11 u u u u u u u uTBC 0 0 1 1 - 1 1 1 0 0 1 1 - 1 1 1 u u u u - u u uEEA - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - u u u u u uEED 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uEEC - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - u u u uFADJL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uFADJH - - - - - - - 1 - - - - - - - 1 - - - - - - - uCTRL 0 - - - - x 0 0 0 - - - - 0 0 0 u - - - - u u uLVRC 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 u u u u u u u uSTMC0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uSTMC1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uSTMDL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uSTMDH - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uSTMAL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uSTMAH - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uCTRL2 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uCTRL3 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - u u u u u u uSLEWC - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uSLEDC - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - u u u uPTMC0 0 0 0 0 0 - - - 0 0 0 0 0 - - - u u u u u - - -PTMC1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u




Register Reset(Power On)

WDT Time-out(Normal Operation)

WDT Time-out(SLEEP/IDLE)

PTMDL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uPTMDH - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uPTMAL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uPTMAH - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uPTMRPL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uPTMRPH - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uOCVPC0 11 0 0 1 0 0 0 11 0 0 1 0 0 0 u u u u u u u uOCVPC1 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 u u u u - - u uOCVPC2 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - u u u u u u uOCVPDA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uOCVPOCAL 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 u u u u u u u uOCVPCCAL 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 u u u u u u u u

Note:"-"standsforunimplemented"u"standsforunchanged

"x"standsforunknown

Input/Output PortsHoltekmicrocontrollersofferconsiderableflexibilityontheirI/Oports.Withtheinputoroutputdesignationofeverypinfullyunderuserprogramcontrol,pull-highselectionsforallportsandwake-upselectionsoncertainpins,theuserisprovidedwithanI/Ostructuretomeettheneedsofawiderangeofapplicationpossibilities.

Thedeviceprovidesbidirectional input/output lines labeledwithportnamePA.TheseI/Oportsaremappedto theRAMDataMemorywithspecificaddressesasshownin theSpecialPurposeDataMemorytable.Allof theseI/Oportscanbeusedforinputandoutputoperations.Forinputoperation,theseportsarenon-latching,whichmeanstheinputsmustbereadyattheT2risingedgeofinstruction"MOVA,[m]",wheremdenotestheportaddress.Foroutputoperation,allthedataislatchedandremainsunchangeduntiltheoutputlatchisrewritten.

RegisterName

Bit7 6 5 4 3 2 1 0

PA PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0PAC PAC7 PAC6 PAC5 PAC4 PAC3 PAC2 PAC1 PAC0

PAPU PAPU7 PAPU6 PAPU5 PAPU4 PAPU3 PAPU2 PAPU1 PAPU0PAWU PAWU7 PAWU6 PAWU5 PAWU4 PAWU3 PAWU2 PAWU1 PAWU0

I/O Logic Function Registers List




Pull-high ResistorsManyproductapplicationsrequirepull-highresistorsfortheirswitchinputsusuallyrequiringtheuseofanexternalresistor.Toeliminate theneedfor theseexternalresistors,all I/Opins,whenconfiguredasaninputhavethecapabilityofbeingconnectedtoaninternalpull-highresistor.Thesepull-highresistorsareselectedusingregistersPAPU,andare implementedusingweakPMOStransistors.

NotethatonlywhentheI/OportsareconfiguredasdigitalinputorNMOSoutput,theinternalpull-highfunctionscanbeenabledusing thePAPUregisters. Inotherconditions, internalpull-highfunctionsaredisabled.

PAPU RegisterBit 7 6 5 4 3 2 1 0

Name PAPU7 PAPU6 PAPU5 PAPU4 PAPU3 PAPU2 PAPU1 PAPU0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~0 PAPU7~PAPU0:PortAPinPull-highControl0:Disable1:Enable

Port A Wake-upTheHALTinstructionforcesthemicrocontroller intotheSLEEPorIDLEModewhichpreservespower,afeaturethat is importantforbatteryandotherlow-powerapplications.Variousmethodsexist towake-upthemicrocontroller,oneofwhichis tochangethelogicconditionononeofthePortApinsfromhightolow.Thisfunctionisespeciallysuitableforapplicationsthatcanbewokenupviaexternalswitches.EachpinonPortAcanbeselectedindividually tohave thiswake-upfeatureusingthePAWUregister.

NotethatonlywhenthePortApinsareconfiguredasgeneralpurposeI/OsandthedeviceisintheHALTstatus, thePortAwake-upfunctionscanbeenabledusingtherelevantbits in thePAWUregister.Inotherconditions,thewake-upfunctionsaredisabled.

PAWU RegisterBit 7 6 5 4 3 2 1 0

Name PAWU7 PAWU6 PAWU5 PAWU4 PAWU3 PAWU2 PAWU1 PAWU0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~0 PAWU7~PAWU0:PortAPinWake-upControl0:Disable1:Enable




I/O Port Control RegistersEachI/OporthasitsowncontrolregisterknownasPAC,tocontroltheinput/outputconfiguration.With thiscontrol register,eachCMOSoutputor inputcanbe reconfigureddynamicallyundersoftwarecontrol.EachpinoftheI/Oportsisdirectlymappedtoabitinitsassociatedportcontrolregister.FortheI/Opintofunctionasaninput, thecorrespondingbitofthecontrolregistermustbewrittenasa"1".Thiswill thenallowthe logicstateof the inputpin tobedirectly readbyinstructions.Whenthecorrespondingbitofthecontrolregisteriswrittenasa"0",theI/OpinwillbesetupasaCMOSoutput.Ifthepiniscurrentlysetupasanoutput,instructionscanstillbeusedtoreadtheoutputregister.However,itshouldbenotedthattheprogramwillinfactonlyreadthestatusoftheoutputdatalatchandnottheactuallogicstatusoftheoutputpin.

PAC RegisterBit 7 6 5 4 3 2 1 0

Name PAC7 PAC6 PAC5 PAC4 PAC3 PAC2 PAC1 PAC0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 1 1 1 1 1 1 1 1

Bit7~0 PAC7~PAC0:PortAPinInput/OutputTypeSelection0:Output1:Input

I/O Port Source Current ControlThedevicesupportsdifferentsourcecurrentdrivingcapabilityforPAport.Withthecorrespondingselection register,SLEDC,eachI/Oportcansupport four levelsof thesourcecurrentdrivingcapability.UsersshouldrefertotheD.C.characteristicssectiontoselectthedesiredsourcecurrentfordifferentapplications.

SLEDC RegisterBit 7 6 5 4 3 2 1 0

Name — — — — SLEDC3 SLEDC2 SLEDC1 SLEDC0R/W — — — — R/W R/W R/W R/WPOR — — — — 0 0 0 0

Bit7~4 Unimplemented,readas"0"Bit3~2 SLEDC3~SLEDC2:PA7~PA4SourceCurrentSelection

00:Sourcecurrent=Level0(min.)01:Sourcecurrent=Level110:Sourcecurrent=Level211:Sourcecurrent=Level3(max.)

Bit1~0 SLEDC1~SLEDC0:PA3,PA2,PA0SourceCurrentSelection00:Sourcecurrent=Level0(min.)01:Sourcecurrent=Level110:Sourcecurrent=Level211:Sourcecurrent=Level3(max.)

Note:UsersshouldrefertotheD.C.Characteristicssectiontoobtaintheexactvaluefordifferentapplications.




I/O Port Output Slew Rate ControlThe device supports different output slew rate driving capability for PA1port.With thecorrespondingselectionregister,SLEWC,PA1portcansupportfourlevelsoftheoutputslewratedrivingcapability.UsersshouldrefertotheD.C.characteristicssectiontoselectthedesiredoutputslewratefordifferentapplications.

SLEWC RegisterBit 7 6 5 4 3 2 1 0

Name — — — — — — SLEWC1 SLEWC0R/W — — — — — — R/W R/WPOR — — — — — — 0 0

Bit7~2 Unimplemented,readas"0"Bit1~0 SLEWC1~SLEWC0:PA1OutputSlewRateSelection

00:SlewRate=Level0(min.)01:SlewRate=Level110:SlewRate=Level211:SlewRate=Level3(max.)

Note:UsersshouldrefertotheD.C.Characteristicssectiontoobtaintheexactvaluefordifferentapplications.

Pin-shared FunctionTheflexibilityofthemicrocontrollerrangeisgreatlyenhancedbytheuseofpinsthathavemorethanonefunction.Limitednumbersofpinscanforceseriousdesignconstraintsondesignersbutbysupplyingpinswithmulti-functions,manyofthesedifficultiescanbeovercome.Forthesepins,thedesiredfunctionofthemulti-functionI/Opinsisselectedbyaseriesofregistersviatheapplicationprogramcontrol.

Pin-shared Function Selection RegistersThemostimportantpoint tonoteis tomakesurethat thedesiredpin-sharedfunctionisproperlyselectedandalsodeselected.Toselect thedesiredpin-sharedfunction, thepin-sharedfunctionshouldfirstbecorrectlyselectedusingthecorrespondingpin-sharedcontrolregister.Afterthatthecorrespondingperipheralfunctionalsettingshouldbeconfiguredandthentheperipheralfunctioncanbeenabled.Tocorrectlydeselectthepin-sharedfunction,theperipheralfunctionshouldfirstbedisabledandthenthecorrespondingpin-sharedfunctioncontrolregistercanbemodifiedtoselectotherpin-sharedfunctions.

When thepin-shared input function isselected tobeused, thecorresponding inputandoutputfunctions selection should be properlymanaged. For example, if theOCVP is used, thecorrespondingoutputpin-sharedfunctionshouldbeconfiguredastheOCVPAI0/OCVPCIfunctionbyconfiguringtheCTRL3registerandtheOCVPAI0signalintputshouldbeproperlyselectedusingtheCTRL2register.However,iftheexternalinterruptfunctionisselectedtobeused,therelevantoutputpin-sharedfunctionshouldbeselectedasanI/Ofunctionandtheinterruptinputsignalshouldbeselected.




• CTRL3 Register

Bit 7 6 5 4 3 2 1 0Name — IOCN6 IOCN5 IOCN4 IOCN3 IOCN2 IOCN1 IOCN0R/W — R/W R/W R/W R/W R/W R/W R/WPOR — 0 0 0 0 0 0 0

Bit7 Unimplemented,readas"0"Bit6 IOCN6:PA7pin-sharedfunctionselection

0:PA71:OCVPAI0

Bit5 IOCN5:PA6pin-sharedfunctionselection0:PA61:OCVPAI0

Bit4 IOCN4:PA5pin-sharedfunctionselection0:INT1/STCK/PA51:OCVPCI

TheINT1orSTCKpinfunctionisfurtherlyselectedusingthecorrespondingfunctionselectionbitsintheinterruptcontrolregisterorSTMcontrolregister.

Bit3~2 IOCN3 ~ IOCN2:PA4pin-sharedfunctionselection00:PA401:STP10:OCVPAI011:VREF

Bit1 IOCN1:PA3pin-sharedfunctionselection0:INT0/PTCK/PA31:OCVPAI0

TheINT0orPTCKpinfunctionisfurtherlyselectedusingthecorrespondingfunctionselectionbitsintheinterruptcontrolregisterorPTMcontrolregister.

Bit0 IOCN0:PA1pin-sharedfunctionselection0:PA11:PTP

• CTRL2 Register

Bit 7 6 5 4 3 2 1 0Name — — — — — — OCVPS1 OCVPS0R/W — — — — — — R/W R/WPOR — — — — — — 0 0

Bit7~2 Unimplemented,readas"0"Bit1~0 OCVPS1 ~ OCVPS0:OCVPAI0InputSourcePinSelection

00:OCVPAI0onPA401:OCVPAI0onPA310:OCVPAI0onPA611:OCVPAI0onPA7




I/O Pin StructuresTheaccompanyingdiagramillustratestheinternalstructuresofthelogicI/Ofuction.Astheexactlogicalconstructionof theI/Opinwilldifferfromthisdiagram,it issuppliedasaguideonlytoassistwiththefunctionalunderstandingofthelogicfunctionI/Opins.Thewiderangeofpin-sharedstructuresdoesnotpermitalltypestobeshown.

MUX

VDD

Control Bit

Data Bit

Data Bus

Write Control Register

Chip Reset

Read Control Register

Read Data Register

Write Data Register

System Wake-up wake-up Select PA only

I/O pin

WeakPull-up

Pull-highRegisterSelect

Q

D

CK

Q

D

CK

Q

QS

S

Logic Function Input/Output Structure

Programming ConsiderationsWithintheuserprogram,oneofthefirstthingstoconsiderisportinitialisation.Afterareset,alloftheI/Odataandportcontrolregisterswillbesethigh.ThismeansthatallI/Opinswilldefaulttoaninputstate, thelevelofwhichdependsontheotherconnectedcircuitryandwhetherpull-highselectionshavebeenchosen.Iftheportcontrolregisters,PAC,isthenprogrammedtosetupsomepinsasoutputs, theseoutputpinswillhaveaninitialhighoutputvalueunlesstheassociatedportdataregister,PA,isfirstprogrammed.Selectingwhichpinsareinputsandwhichareoutputscanbeachievedbyte-widebyloadingthecorrectvalues into theappropriateportcontrolregisterorbyprogrammingindividualbitsintheportcontrolregisterusingthe"SET[m].i"and"CLR[m].i"instructions.Notethatwhenusingthesebitcontrolinstructions,aread-modify-writeoperationtakesplace.Themicrocontrollermustfirstreadinthedataontheentireport,modifyittotherequirednewbitvaluesandthenrewritethisdatabacktotheoutputports.

PortAhas theadditionalcapabilityofprovidingwake-upfunctions.When thedevice is in theSLEEPorIDLEMode,variousmethodsareavailabletowakethedeviceup.OneoftheseisahightolowtransitionofanyofthePortApins.SingleormultiplepinsonPortAcanbesetuptohavethisfunction.




Timer Modules – TMOneofthemostfundamentalfunctionsinanymicrocontrollerdeviceistheabilitytocontrolandmeasure time.To implement timerelatedfunctions thedevice includesseveralTimerModules,abbreviated to thenameTM.TheTMsaremulti-purpose timingunits and serve toprovideoperationssuchasTimer/Counter,InputCapture,CompareMatchOutputandSinglePulseOutputaswellasbeingthefunctionalunitforthegenerationofPWMsignals.EachoftheTMshastwoindividual interrupts.Theadditionof inputandoutputpins foreachTMensures thatusersareprovidedwithtimingunitswithawideandflexiblerangeoffeatures.

ThecommonfeaturesofthedifferentTMtypesaredescribedherewithmoredetailedinformationprovidedintheindividual,StandardandPeriodicTMsections.

IntroductionThedevicecontainsa10-bitStandardTMnamedSTManda10-bitPeriodicTM,namedPTM.Althoughsimilarinnature, thedifferentTMtypesvaryintheirfeaturecomplexity.ThecommonfeaturestotheStandardandPeriodicTMswillbedescribedinthissectionandthedetailedoperationwillbedescribedincorrespondingsections.ThemainfeaturesanddifferencesbetweenthetwotypesofTMaresummarisedintheaccompanyingtable.

Function STM PTMTimer/Counter √ √I/P Capture √ √Compare Match Output √ √PWM Channels 1 1Single Pulse Output 1 1PWM Alignment Edge EdgePWM Adjustment Period & Duty Duty or Period Duty or Period

TM Function Summary

STM PTM10-bit STM 10-bit PTM

TM Name/Type Reference

TM OperationThetwodifferenttypesofTMsofferadiverserangeoffunctions,fromsimpletimingoperationstoPWMsignalgeneration.ThekeytounderstandinghowtheTMoperatesistoseeitintermsofafreerunningcounterwhosevalueis thencomparedwiththevalueofpre-programmedinternalcomparators.Whenthefreerunningcounterhasthesamevalueasthepre-programmedcomparator,knownasacomparematchsituation,aTMinterruptsignalwillbegeneratedwhichcanclearthecounterandperhapsalsochangetheconditionoftheTMoutputpin.TheinternalTMcounter isdrivenbyauserselectableclocksource,whichcanbeaninternalclockoranexternalpin.

TM Clock SourceTheclocksourcewhichdrivesthemaincounterintheTMcanoriginatefromvarioussources.Theselectionof therequiredclocksourceis implementedusingthexTCK2~xTCK0bits inthexTMcontrolregisters,where"x"canstandforSorPTypeTM.TheclocksourcecanbearatioofeitherthesystemclockfSYSortheinternalhighclockfH,thefSUBclocksourceortheexternalxTCKpin.ThexTCKpinclocksourceisusedtoallowanexternalsignaltodrivetheTMasanexternalclocksourceorforeventcounting.




TM InterruptsTheStandardandPeriodictypeTMseachhas twointernal interrupts, theinternalcomparatorAorcomparatorP,whichgenerateaTMinterruptwhenacomparematchconditionoccurs.WhenaTMinterruptisgenerated,itcanbeusedtoclearthecounterandalsotochangethestateoftheTMoutputpin.

TM External PinsEachoftheTMs,irrespectiveofwhattype,hasoneTMinputpin,withthelabelxTCK.TheTMinputpin,xTCK,isessentiallyaclocksourcefortheTMandisselectedusingthexTCK2~xTCK0bitsinthexTMC0register.ThisexternalTMinputpinallowsanexternalclocksourcetodrivetheinternalTM.TheTMinputpincanbechosentohaveeitherarisingorfallingactiveedge.

FortheSTMandPTM,thereisanotherinputpinxTP,whichalsocanbetheSTMorPTMoutputpin.TheSTMorPTMpin is thecapture inputpinwhoseactiveedgecanbea risingedge,afallingedgeorbothrisingandfallingedges.TheactiveedgetransitiontypeisselectedusingtheSTIO1~STIO0bits intheSTMC1registerorPTIO1~PTIO0bits inthePTMC1register.ForthePTM,thereisanothercaptureinput,PTCK,forPTMcaptureinputmode,whichcanbeusedastheexternaltriggerinputsource.

TheTMseachhaveoneoutputpins,namedxTP.TheTMoutputpincanbeselectedusing thecorrespondingpin-sharedfunctionselectionbitsdescribedinthePin-sharedFunctionsection.WhentheTMisintheCompareMatchOutputMode,thesepinscanbecontrolledbytheTMtoswitchtoahighorlowlevelortotogglewhenacomparematchsituationoccurs.TheexternalxTPnoutputpinisalsothepinwheretheTMgeneratesthePWMoutputwaveform.

AstheTMinputoroutputpinsarepin-sharedwithotherfunctions,theTMexternalpinfunctionmust firstbesetupusingregisters.Asinglebit in thePin-sharedFunctionSelectionRegistersdetermines if itsassociatedpin is tobeusedasanexternalTMpinor if it is tohaveanotherfunction.

STM PTMInput Output Input Output

STCK/STP STP PTCK/PTP PTP

TM External Pins

TM Input/Output Pin Control RegisterSelectingtohaveaTMinput/outputorwhethertoretainitsothersharedfunctionisimplementedusingoneregister,withasinglebitintheregistercorrespondingtoaTMinput/outputpin.SettingthebithighwillsetupthecorrespondingpinasaTMinput/output,ifresettozerothepinwillretainitsoriginalotherfunction.

STM

STCK

STPCCR capture input

CCR output

TCK input

STM Function Pin Control Block Diagram




PTM

PTCK

PTPCCR capture input

CCR output

CCR capture inputTCK input

PTM Function Pin Control Block Diagram

Programming ConsiderationsTheTMCounterRegistersandtheCapture/CompareCCRAandCCRPregisters,being10-bit,allhavealowandhighbytestructure.Thehighbytescanbedirectlyaccessed,butasthelowbytescanonlybeaccessedviaaninternal8-bitbuffer,readingorwritingtotheseregisterpairsmustbecarriedoutinaspecificway.Theimportantpointtonoteisthatdatatransfertoandfromthe8-bitbufferanditsrelatedlowbyteonlytakesplacewhenawriteorreadoperationtoitscorrespondinghighbyteisexecuted.

As theCCRAandCCRPregistersare implemented in thewayshownin thefollowingdiagramandaccessingtheseregistersiscarriedoutinaspecificwaydescribedabove,it isrecommendedtousethe"MOV"instructiontoaccesstheCCRAandCCRPlowbyteregisters,namedxTMALandPTMRPL,inthefollowingaccessprocedures.AccessingtheCCRAorCCRPlowbyteregisterwithoutfollowingtheseaccessprocedureswillresultinunpredictablevalues.

Data Bus

8-bitBuffer

xTMDHxTMDL

xTMAHxTMAL

xTM Counter Register (Read only)

xTM CCRA Register (Read/Write)

PTM CCRP Register (Read/Write)

PTMRPHPTMRPL

Thefollowingstepsshowthereadandwriteprocedures:

• WritingDatatoCCRAorCCRP♦ Step1.WritedatatoLowBytexTMALorPTMRPL

– notethatheredataisonlywrittentothe8-bitbuffer.♦ Step2.WritedatatoHighBytexTMAHorPTMRPH

– heredata iswrittendirectly to thehighbyteregistersandsimultaneouslydata is latchedfromthe8-bitbuffertotheLowByteregisters.

• ReadingDatafromtheCounterRegistersandCCRAorCCRP♦ Step1.ReaddatafromtheHighBytexTMDH,xTMAHorPTMRPH

– heredataisreaddirectlyfromtheHighByteregistersandsimultaneouslydataislatchedfromtheLowByteregisterintothe8-bitbuffer.

♦ Step2.ReaddatafromtheLowBytexTMDL,xTMALorPTMRPL– thisstepreadsdatafromthe8-bitbuffer.




Standard Type TM – STMTheStandardTypeTMcontainsfiveoperatingmodes,whichareCompareMatchOutput,Timer/EventCounter,CaptureInput,SinglePulseOutputandPWMOutputmodes.TheStandardTMcanbecontrolledwithoneexternalinputpinandcandriveoneexternaloutputpin.

fSYS

fSYS/4

fH/64fH/16

fSUB

STCK

000001010011100101110111

STCK2~STCK0

10-bit Count-up Counter

3-bit Comparator P

CCRP

b7~b9

b0~b9

10-bit Comparator A

STONSTPAU

Comparator A Match

Comparator P Match

Counter Clear 01

Output Control

Polarity Control STP

STOC

STM1, STM0STIO1, STIO0

STMAF Interrupt

STMPF Interrupt

STPOL

CCRA

STCCLR

EdgeDetector

STIO1, STIO0

PinControl

IOCN3~IOCN2

fSUB

Standard Type TM Block Diagram

Standard TM OperationAtitscoreisa10-bitcount-upcounterwhichisdrivenbyauserselectableinternalclocksource.Therearealsotwointernalcomparatorswiththenames,ComparatorAandComparatorP.ThesecomparatorswillcomparethevalueinthecounterwithCCRPandCCRAregisters.TheCCRPis3-bitwidewhosevalueiscomparedwiththehighest3bitsinthecounterwhiletheCCRAisthe10bitsandthereforecompareswithallcounterbits.

Theonlywayofchanging thevalueof the10-bitcounterusing theapplicationprogram, is toclear thecounterbychangingtheSTONbit fromlowtohigh.Thecounterwillalsobeclearedautomaticallybyacounteroverfloworacomparematchwithoneof itsassociatedcomparators.Whentheseconditionsoccur,aSTM interruptsignalwillalsousuallybegenerated.TheStandardTypeTMcanoperateinanumberofdifferentoperationalmodes,canbedrivenbydifferentclocksourcesandcanalsocontrolanoutputpin.Alloperatingsetupconditionsareselectedusingrelevantinternalregisters.

Standard Type TM Register DescriptionOveralloperationof theStandardTMiscontrolledusingseriesofregisters.Areadonlyregisterpairexiststostoretheinternalcounter10-bitvalue,whilearead/writeregisterpairexiststostoretheinternal10-bitCCRAvalue.TheremainingtworegistersarecontrolregisterswhichsetupthedifferentoperatingandcontrolmodesaswellasthreeCCRPbits.

RegisterName

Bit7 6 5 4 3 2 1 0

STMC0 STPAU STCK2 STCK1 STCK0 STON STRP2 STRP1 STRP0STMC1 STM1 STM0 STIO1 STIO0 STOC STPOL STDPX STCCLRSTMDL D7 D6 D5 D4 D3 D2 D1 D0STMDH — — — — — — D9 D8STMAL D7 D6 D5 D4 D3 D2 D1 D0STMAH — — — — — — D9 D8

10-bit Standard TM Register List




STMC0 RegisterBit 7 6 5 4 3 2 1 0

Name STPAU STCK2 STCK1 STCK0 STON STRP2 STRP1 STRP0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7 STPAU:STMCounterPauseControl0:Run1:Pause

Thecountercanbepausedbysettingthisbithigh.Clearingthebit tozerorestoresnormalcounteroperation.WheninaPauseconditiontheSTMwillremainpoweredupandcontinuetoconsumepower.Thecounterwillretainitsresidualvaluewhenthisbitchangesfromlowtohighandresumecountingfromthisvaluewhenthebitchangestoalowvalueagain.

Bit6~4 STCK2~STCK0:SelectSTMCounterclock000:fSYS/4001:fSYS

010:fH/16011:fH/64100:fSUB

101:fSUB

110:STCKrisingedgeclock111:STCKfallingedgeclock

ThesethreebitsareusedtoselecttheclocksourcefortheSTM.Theexternalpinclocksourcecanbechosentobeactiveontherisingorfallingedge.TheclocksourcefSYSisthesystemclock,whilefHandfSUBareotherinternalclocks,thedetailsofwhichcanbefoundintheoscillatorsection.

Bit3 STON:STMCounterOn/OffControl0:Off1:On

Thisbitcontrolstheoverallon/offfunctionoftheSTM.Settingthebithighenablesthecounter torun,clearingthebitdisables theSTM.Clearingthisbit tozerowillstop thecounterfromcountingand turnoff theSTMwhichwill reduce itspowerconsumption.Whenthebitchangesstatefromlowtohightheinternalcountervaluewillbereset tozero,howeverwhenthebitchangesfromhighto low, the internalcounterwillretainitsresidualvalueuntilthebitreturnshighagain.IftheSTMisintheCompareMatchOutputModeorthePWMoutputModeorSinglePulseOutputModethentheSTMoutputpinwillberesettoitsinitialcondition,asspecifiedbytheSTOCbit,whentheSTONbitchangesfromlowtohigh.

Bit2~0 STRP2 ~ STRP0:STMCCRP3-bitregister,comparedwiththeSTMCounterbit9~bit7ComparatorPMatchPeriod000:1024STMclocks001:128STMclocks010:256STMclocks011:384STMclocks100:512STMclocks101:640STMclocks110:768STMclocks111:896STMclocks

ThesethreebitsareusedtosetupthevalueontheinternalCCRP3-bitregister,whichare thencomparedwith the internalcounter’shighest threebits.Theresultof thiscomparisoncanbeselectedtocleartheinternalcounterif theSTCCLRbit isset tozero.SettingtheSTCCLRbit tozeroensuresthatacomparematchwiththeCCRPvalueswillreset theinternalcounter.AstheCCRPbitsareonlycomparedwiththehighest threecounterbits, thecomparevaluesexist in128clockcyclemultiples.Clearingall threebits tozero is ineffectallowing thecounter tooverflowat itsmaximumvalue.




STMC1 RegisterBit 7 6 5 4 3 2 1 0

Name STM1 STM0 STIO1 STIO0 STOC STPOL STDPX STCCLRR/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~6 STM1 ~ STM0:SelectSTMOperatingMode00:CompareMatchOutputMode01:CaptureInputMode10:PWMOutputModeorSinglePulseOutputMode11:Timer/CounterMode

ThesebitssetuptherequiredoperatingmodefortheSTM.ToensurereliableoperationtheSTMshouldbeswitchedoffbeforeanychangesaremadetotheSTM1andSTM0bits.IntheTimer/CounterMode,theSTMoutputpinstateisundefined.

Bit5~4 STIO1 ~ STIO0:SelectSTMfunctionCompareMatchOutputMode00:Nochange01:Outputlow10:Outputhigh11:Toggleoutput

PWMoutputMode/SinglePulseOutputMode00:PWMOutputinactivestate01:PWMOutputactivestate10:PWMoutput11:Singlepulseoutput

CaptureInputMode00:InputcaptureatrisingedgeofSTP01:InputcaptureatfallingedgeofSTP10:Inputcaptureatfalling/risingedgeofSTP11:Inputcapturedisabled

Timer/counterModeUnused

ThesetwobitsareusedtodeterminehowtheSTMoutputpinchangesstatewhenacertainconditionisreached.ThefunctionthatthesebitsselectdependsuponinwhichmodetheSTMisrunning.IntheCompareMatchOutputMode,theSTIO1~STIO0bitsdeterminehowtheSTMoutputpinchangesstatewhenacomparematchoccursfromtheComparatorA.TheSTMoutputpincanbesetuptoswitchhigh,switchlowortotoggleitspresentstatewhenacomparematchoccurs fromtheComparatorA.When theSTIO1~STIO0bitsarebothzero,thennochangewill takeplaceontheoutput.TheinitialvalueoftheSTMoutputpinshouldbesetupusingtheSTOCbit.Notethat theoutput levelrequestedby theSTIO1~STIO0bitsmustbedifferentfromthe initialvaluesetupusingtheSTOCbitotherwisenochangewilloccurontheSTMoutputpinwhenacomparematchoccurs.AftertheSTMoutputpinchangesstate, itcanberesettoitsinitiallevelbychangingtheleveloftheSTONbitfromlowtohigh.InthePWMOutputMode,theSTIO1andSTIO0bitsdeterminehowtheSTMoutputpinchangesstatewhenacertaincomparematchconditionoccurs.ThePWMoutputfunctionismodifiedbychangingthesetwobits.ItisnecessarytochangethevaluesoftheSTIO1andSTIO0bitsonlyaftertheSTMhasbeenswitchedoff.UnpredictablePWMoutputswilloccuriftheSTIO1andSTIO0bitsarechangedwhentheSTMisrunning.




Bit3 STOC:STMOutputcontrolbitCompareMatchOutputMode0:Initiallow1:Initialhigh

PWMoutputMode/SinglePulseOutputMode0:Activelow1:Activehigh

This is theoutputcontrolbit for theSTMoutputpin. ItsoperationdependsuponwhetherSTMisbeingused in theCompareMatchOutputModeor in thePWMoutputMode/SinglePulseOutputMode.IthasnoeffectiftheSTMisintheTimer/CounterMode. In theCompareMatchOutputMode itdetermines the logic leveloftheSTMoutputpinbeforeacomparematchoccurs.InthePWMoutputModeitdeterminesifthePWMsignalisactivehighoractivelow.IntheSinglePulseOutputModeitdeterminesthelogicleveloftheSTMoutputpinwhentheSTONbitchangesfromlowtohigh.

Bit2 STPOL:STMOutputpolarityControl0:Non-invert1:Invert

ThisbitcontrolsthepolarityoftheSTMoutputpin.WhenthebitissethightheSTMoutputpinwillbeinvertedandnotinvertedwhenthebitiszero.IthasnoeffectiftheSTMisintheTimer/CounterMode.

Bit1 STDPX:STMPWMperiod/dutyControl0:CCRP-period;CCRA-duty1:CCRP-duty;CCRA-period

Thisbit,determineswhichoftheCCRAandCCRPregistersareusedforperiodanddutycontrolofthePWMwaveform.

Bit0 STCCLR:SelectSTMCounterclearcondition0:STMComparatorPmatch1:STMComparatorAmatch

Thisbit isused toselect themethodwhichclears thecounter.Remember that theStandardTMcontainstwocomparators,ComparatorAandComparatorP,eitherofwhichcanbeselectedtoclear theinternalcounter.With theSTCCLRbitsethigh,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorA.Whenthebitislow,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorPorwithacounteroverflow.AcounteroverflowclearingmethodcanonlybeimplementediftheCCRPbitsareallclearedtozero.TheSTCCLRbitisnotusedinthePWMoutputmode,SinglePulseorInputCaptureMode.

STMDL Register Bit 7 6 5 4 3 2 1 0

Name D7 D6 D5 D4 D3 D2 D1 D0R/W R R R R R R R RPOR 0 0 0 0 0 0 0 0

Bit7~0 STMCounterLowByteRegisterbit7~bit0STM10-bitCounterbit7~bit0

STMDH Register Bit 7 6 5 4 3 2 1 0

Name — — — — — — D9 D8R/W — — — — — — R RPOR — — — — — — 0 0

Bit7~2 Unimplemented,readas"0"Bit1~0 STMCounterHighByteRegisterbit1~bit0

STM10-bitCounterbit9~bit8




STMAL RegisterBit 7 6 5 4 3 2 1 0


Bit7~0 STMCCRALowByteRegisterbit7~bit0STM10-bitCCRAbit7~bit0

STMAH RegisterBit 7 6 5 4 3 2 1 0

Name — — — — — — D9 D8R/W — — — — — — R/W R/WPOR — — — — — — 0 0

Bit7~2 Unimplemented,readas"0"Bit1~0 STMCCRAHighByteRegisterbit1~bit0

STM10-bitCCRAbit9~bit8

Standard Type TM Operating ModesTheStandardTypeTMcanoperateinoneoffiveoperatingmodes,CompareMatchOutputMode,PWMOutputMode,SinglePulseOutputMode,CaptureInputModeorTimer/CounterMode.TheoperatingmodeisselectedusingtheSTM1andSTM0bitsintheSTMC1register.

Compare Match Output ModeToselectthismode,bitsSTM1andSTM0intheSTMC1register,shouldbesetto00respectively.Inthismodeoncethecounterisenabledandrunningitcanbeclearedbythreemethods.Theseareacounteroverflow,acomparematchfromComparatorAandacomparematchfromComparatorP.WhentheSTCCLRbitislow,therearetwowaysinwhichthecountercanbecleared.OneiswhenacomparematchfromComparatorP,theotheriswhentheCCRPbitsareallzerowhichallowsthecountertooverflow.HerebothSTMAFandSTMPFinterruptrequestflagsforComparatorAandComparatorPrespectively,willbothbegenerated.

IftheSTCCLRbitintheSTMC1registerishighthenthecounterwillbeclearedwhenacomparematchoccursfromComparatorA.However,hereonlytheSTMAFinterruptrequestflagwillbegeneratedevenifthevalueoftheCCRPbitsislessthanthatoftheCCRAregisters.ThereforewhenSTCCLRishighnoSTMPFinterruptrequestflagwillbegenerated.IntheCompareMatchOutputMode,theCCRAcannotbesetto"0".IftheCCRAbitsareallzero,thecounterwilloverflowwhenitreachesitsmaximum10-bit,3FFHex,value,howeverheretheSTMAFinterruptrequestflagwillnotbegenerated.

Asthenameofthemodesuggests,afteracomparisonismade,theSTMoutputpin,willchangestate.TheSTMoutputpinconditionhoweveronlychangesstatewhenanSTMAFinterruptrequestflagisgeneratedafteracomparematchoccursfromComparatorA.TheSTMPFinterruptrequestflag,generatedfromacomparematchoccursfromComparatorP,willhavenoeffectontheSTMoutputpin.ThewayinwhichtheSTMoutputpinchangesstatearedeterminedbytheconditionoftheSTIO1andSTIO0bitsintheSTMC1register.TheSTMoutputpincanbeselectedusingtheSTIO1andSTIO0bitstogohigh,togolowortotogglefromitspresentconditionwhenacomparematchoccursfromComparatorA.TheinitialconditionoftheSTMoutputpin,whichissetupaftertheSTONbitchangesfromlowtohigh,issetupusingtheSTOCbit.Notethatif theSTIO1andSTIO0bitsarezerothennopinchangewilltakeplace.




Counter Value

0x3FF

CCRP

CCRA

STON

STPAU

STPOL

CCRP Int. flag STMPF

CCRA Int. flag STMAF

Time

CCRP=0

CCRP > 0

Counter overflowCCRP > 0Counter cleared by CCRP value

Pause

Resume

Stop

Counter Restart

STCCLR = 0; STM [1:0] = 00

Output pin set to initial Level Low if STOC=0

Output Toggle with STMAF flag

Note STIO [1:0] = 10 Active High Output selectHere STIO [1:0] = 11

Toggle Output select

Output not affected by STMAF flag. Remains High until reset by STON bit

Output PinReset to Initial value

Output controlled by other pin-shared function

Output Invertswhen STPOL is high

Compare Match Output Mode – STCCLR=0Note:1.WithSTCCLR=0aComparatorPmatchwillclearthecounter

2.TheSTMoutputpincontrolledonlybytheSTMAFflag3.TheoutputpinresettoinitialstatebyaSTONbitrisingedge




Counter Value

0x3FF

CCRP

CCRA

STON

STPAU

STPOL



Time

CCRA=0

CCRA = 0Counter overflowCCRA > 0 Counter cleared by CCRA value

Pause

Resume

Stop Counter Restart

STCCLR = 1; STM [1:0] = 00

Output pin set to initial Level Low if STOC=0

Output Toggle with STMAF flag

Note STIO [1:0] = 10 Active High Output selectHere STIO [1:0] = 11


Output not affected by STMAF flag. Remains High until reset by STON bit



Output Invertswhen STPOL is high

STMPF not generated

No STMAF flag generated on CCRA overflow

Output does not change

Compare Match Output Mode – STCCLR=1Note:1.WithSTCCLR=1aComparatorAmatchwillclearthecounter

2.TheSTMoutputpincontrolledonlybytheSTMAFflag3.TheoutputpinresettoinitialstatebyaSTONrisingedge4.TheSTMPFflagisnotgeneratedwhenSTCCLR=1




Timer/Counter ModeToselectthismode,bitsSTM1andSTM0intheSTMC1registershouldbesetto11respectively.TheTimer/CounterModeoperates in an identicalway to theCompareMatchOutputModegenerating thesameinterrupt flags.Theexception is that in theTimer/CounterMode theSTMoutputpin isnotused.Therefore theabovedescriptionandTimingDiagramsfor theCompareMatchOutputModecanbeusedtounderstanditsfunction.AstheSTMoutputpinisnotusedinthismode,thepincanbeusedasanormalI/Opinorotherpin-sharedfunctionbysettingpin-sharefunctionregister.

PWM Output ModeToselectthismode,bitsSTM1andSTM0intheSTMC1registershouldbesetto10respectivelyandalso theSTIO1andSTIO0bitsshouldbeset to10respectively.ThePWMfunctionwithintheSTMisusefulforapplicationswhichrequirefunctionssuchasmotorcontrol,heatingcontrol,illuminationcontroletc.ByprovidingasignaloffixedfrequencybutofvaryingdutycycleontheSTMoutputpin,asquarewaveACwaveformcanbegeneratedwithvaryingequivalentDCRMSvalues.

AsboththeperiodanddutycycleofthePWMwaveformcanbecontrolled,thechoiceofgeneratedwaveformisextremelyflexible.In thePWMoutputmode, theSTCCLRbithasnoeffectas thePWMperiod.BothoftheCCRAandCCRPregistersareusedtogeneratethePWMwaveform,oneregisterisusedtocleartheinternalcounterandthuscontrolthePWMwaveformfrequency,whiletheotheroneisusedtocontrol thedutycycle.Whichregister isusedtocontroleitherfrequencyordutycycle isdeterminedusing theSTDPXbit in theSTMC1register.ThePWMwaveformfrequencyanddutycyclecanthereforebecontrolledbythevaluesintheCCRAandCCRPregisters.

Aninterruptflag,oneforeachoftheCCRAandCCRP,willbegeneratedwhenacomparematchoccursfromeitherComparatorAorComparatorP.TheSTOCbitintheSTMC1registerisusedtoselecttherequiredpolarityofthePWMwaveformwhilethetwoSTIO1andSTIO0bitsareusedtoenablethePWMoutputortoforcetheSTMoutputpintoafixedhighorlowlevel.TheSTPOLbitisusedtoreversethepolarityofthePWMoutputwaveform.

• 10-bit STM, PWM Output Mode, Edge-aligned Mode, STDPX=0

CCRP 001b 010b 011b 100b 101b 110b 111b 000bPeriod 128 256 384 512 640 768 896 1024Duty CCRA

IffSYS=4MHz,TMclocksourceisfSYS/4,CCRP=100bandCCRA=128,

TheSTMPWMoutputfrequency=(fSYS/4)/512=fSYS/2048=1.9531kHz,duty=128/512=25%.

IftheDutyvaluedefinedbytheCCRAregisterisequaltoorgreaterthanthePeriodvalue,thenthePWMoutputdutyis100%.

• 10-bit STM, PWM Output Mode, Edge-aligned Mode, STDPX=1

CCRP 001b 010b 011b 100b 101b 110b 111b 000bPeriod CCRADuty 128 256 384 512 640 768 896 1024

ThePWMoutputperiodisdeterminedbytheCCRAregistervaluetogetherwiththeSTMclockwhilethePWMdutycycleisdefinedbytheCCRPregistervalue.




Counter Value

CCRP

CCRA

STON

STPAU

STPOL



STM O/P Pin(STOC=1)

Time

Counter cleared by CCRP

Pause Resume Counter Stop if STON bit low

Counter Reset when STON returns high

STDPX = 0; STM [1:0] = 10

PWM Duty Cycle set by CCRA

PWM resumes operation

Output controlled by other pin-shared function Output Inverts

when STPOL = 1PWM Period set by CCRP

STM O/P Pin(STOC=0)

PWM Output Mode – STDPX=0Note:1.HereSTDPX=0–CounterclearedbyCCRP

2.AcounterclearsetsPWMPeriod3.TheinternalPWMfunctioncontinuesrunningevenwhenSTIO[1:0]=00or014.TheSTCCLRbithasnoinfluenceonPWMoperation




Counter Value

CCRP

CCRA

STON

STPAU

STPOL



STM O/P Pin (STOC=1)

Time

Counter cleared by CCRA

Pause Resume Counter Stop if STON bit low

STDPX = 1; STM [1:0] = 10

PWM Duty Cycle set by CCRP

PWM resumes operation

Output controlled by other pin-shared function Output Inverts

when STPOL = 1PWM Period set by CCRA

STM O/P Pin (STOC=0)


PWM Output Mode – STDPX=1Note:1.HereSTDPX=1–CounterclearedbyCCRA

2.AcounterclearsetsPWMPeriod3.TheinternalPWMfunctioncontinuesevenwhenSTIO[1:0]=00or014.TheSTCCLRbithasnoinfluenceonPWMoperation




Single Pulse ModeToselectthismode,bitsSTM1andSTM0intheSTMC1registershouldbesetto10respectivelyandalsotheSTIO1andSTIO0bitsshouldbesetto11respectively.TheSinglePulseOutputMode,asthenamesuggests,willgenerateasingleshotpulseontheSTMoutputpin.

ThetriggerforthepulseoutputleadingedgeisalowtohightransitionoftheSTONbit,whichcanbeimplementedusingtheapplicationprogram.HoweverintheSinglePulseMode,theSTONbitcanalsobemadetoautomaticallychangefromlowtohighusingtheexternalSTCKpin,whichwillinturninitiatetheSinglePulseoutput.WhentheSTONbittransitionstoahighlevel,thecounterwillstartrunningandthepulseleadingedgewillbegenerated.TheSTONbitshouldremainhighwhenthepulseisinitsactivestate.ThegeneratedpulsetrailingedgewillbegeneratedwhentheSTONbit isclearedtozero,whichcanbeimplementedusingtheapplicationprogramorwhenacomparematchoccursfromComparatorA.

STON bit0 1

S/W Command SET“STON”

orSTCK Pin Transition

STON bit1 0

CCRA Trailing Edge

S/W Command CLR“STON”

orCCRA Compare Match

STP Output Pin

Pulse Width = CCRA Value

CCRA Leading Edge

Single Pulse Generation

Counter Value

CCRP

CCRA

STON

STPAU

STPOL

CCRP Int. Flag STMPF

CCRA Int. Flag STMAF

STM O/P Pin(STOC=1)

Time

Counter stopped by CCRA

PauseResume Counter Stops

by software


STM [1:0] = 10 ; STIO [1:0] = 11

Pulse Width set by CCRA

Output Invertswhen STPOL = 1

No CCRP Interrupts generated

STM O/P Pin(STOC=0)

STCK pin

Software Trigger

Cleared by CCRA match

STCK pin Trigger

Auto. set by STCK pin

Software Trigger

Software Clear

Software TriggerSoftware

Trigger

Single Pulse ModeNote:1.CounterstoppedbyCCRAmatch

2.CCRPisnotused3.ThepulseistriggeredbysettingtheSTONbithigh4.IntheSinglePulseMode,STIO[1:0]mustbesetto"11"andcannotbechanged.




HoweveracomparematchfromComparatorAwillalsoautomaticallycleartheSTONbitandthusgeneratetheSinglePulseoutputtrailingedge.InthiswaytheCCRAvaluecanbeusedtocontrolthepulsewidth.AcomparematchfromComparatorAwillalsogenerateaSTMinterrupt.Thecountercanonlyberesetback tozerowhen theSTONbitchangesfromlowtohighwhen thecounterrestarts.IntheSinglePulseModeCCRPisnotused.TheSTCCLRandSTDPXbitsarenotusedinthisMode.

Capture Input ModeToselectthismodebitsSTM1andSTM0intheSTMC1registershouldbesetto01respectively.Thismodeenablesexternalsignals tocaptureandstore thepresentvalueof theinternalcounterandcanthereforebeusedforapplicationssuchaspulsewidthmeasurement.TheexternalsignalissuppliedontheSTP,whoseactiveedgecanbeeitherarisingedge,afallingedgeorbothrisingandfallingedges; theactiveedgetransitiontypeisselectedusingtheSTIO1andSTIO0bits intheSTMC1register.ThecounterisstartedwhentheSTONbitchangesfromlowtohighwhichisinitiatedusingtheapplicationprogram.

When therequirededge transitionappearson theSTPthepresentvalue in thecounterwillbelatchedintotheCCRAregistersandaSTMinterruptgenerated.IrrespectiveofwhateventsoccurontheSTPthecounterwillcontinuetofreerununtiltheSTONbitchangesfromhightolow.WhenaCCRPcomparematchoccursthecounterwillresetbacktozero;inthiswaytheCCRPvaluecanbeusedtocontrolthemaximumcountervalue.WhenaCCRPcomparematchoccursfromComparatorP,aSTMinterruptwillalsobegenerated.CountingthenumberofoverflowinterruptsignalsfromtheCCRPcanbeausefulmethodinmeasuringlongpulsewidths.TheSTIO1andSTIO0bitscanselect theactive triggeredgeontheSTPtobearisingedge,fallingedgeorbothedgetypes.IftheSTIO1andSTIO0bitsarebothsethigh,thennocaptureoperationwilltakeplaceirrespectiveofwhathappensontheSTP,howeveritmustbenotedthat thecounterwillcontinuetorun.TheSTCCLRandSTDPXbitsarenotusedinthisMode.




Counter Value

YY

CCRP

STON

STPAU

CCRP Int. Flag STMPF

CCRA Int. Flag STMAF

CCRA Value

Time


PauseResume

Counter Reset

STM [1:0] = 01

STM capture pin STP

XX

Counter Stop

STIO [1:0] Value

XX YY XX YY

Active edge Active

edgeActive edge

00 – Rising edge 01 – Falling edge 10 – Both edges 11 – Disable Capture

Capture Input ModeNote:1.STM[1:0]=01andactiveedgesetbytheSTIO[1:0]bits

2.ATMCaptureinputpinactiveedgetransfersthecountervaluetoCCRA3.TheSTCCLRandSTDPXbitsarenotused4.Nooutputfunction–STOCandSTPOLbitsarenotused5.CCRPdeterminesthecountervalueandthecounterhasamaximumcountvaluewhenCCRPisequaltozero.




Periodic Type TM – PTMThePeriodicTypeTMcontainsfiveoperatingmodes,whichareCompareMatchOutput,Timer/EventCounter,CaptureInput,SinglePulseOutputandPWMOutputmodes.ThePeriodicTMcanbecontrolledwithoneexternalinputpinandcandriveoneexternaloutputpin.

PTCK

10-bit Count-up Counter

10-bit Comparator P

CCRP

10-bit Comparator A

Output Control

Polarity Control

PinControl PTP

CCRA Edge Detector

PinControl

PTCCLR

fSYS

fSYS/4

fH/64fH/16

fSUB

PTCK2~PTCK0

PTONPTPAU

Comparator A Match

Comparator P Match

Counter Clear

PTOC

PTM1, PTM0PTIO1, PTIO0

PTMAF Interrupt

PTMPF Interrupt

PTPOL IOCN0

PTIO1, PTIO0

fSUB

IOCN0PTCAPTS

000

001

010

011

100

101

110

111

b0~b9

b0~b9

01

10

Periodic Type TM Block Diagram

Periodic TM Operation ThePeriodicTypeTMcoreisa10-bitcount-upcounterwhichisdrivenbyauserselectableinternalorexternalclocksource.Therearealsotwointernalcomparatorswiththenames,ComparatorAandComparatorP.ThesecomparatorswillcomparethevalueinthecounterwithCCRPandCCRAregisters.TheCCRPcomparatoris10-bitwide.Theonlywayofchanging thevalueof the10-bitcounterusing theapplicationprogram, is toclear thecounterbychangingthePTONbit fromlowtohigh.Thecounterwillalsobeclearedautomaticallybyacounteroverfloworacomparematchwithoneof itsassociatedcomparators.Whentheseconditionsoccur,aPTMinterruptsignalwillalsousuallybegenerated.ThePeriodicTypeTMcanoperateinanumberofdifferentoperationalmodes,canbedrivenbydifferentclocksourcesincludinganinputpinandcanalsocontrolmorethanoneoutputpin.Alloperatingsetupconditionsareselectedusingrelevantinternalregisters.

Periodic Type TM Register Description Overalloperationof thePeriodicTypeTMiscontrolledusingaseriesofregisters.Areadonlyregisterpairexiststostoretheinternalcounter10-bitvalue,whiletworead/writeregisterpairsexisttostoretheinternal10-bitCCRAvalueandCCRPvalue.Theremainingtworegistersarecontrolregisterswhichsetupthedifferentoperatingandcontrolmodes.

RegisterName

Bit7 6 5 4 3 2 1 0

PTMC0 PTPAU PTCK2 PTCK1 PTCK0 PTON — — —PTMC1 PTM1 PTM0 PTIO1 PTIO0 PTOC PTPOL PTCAPTS PTCCLRPTMDL D7 D6 D5 D4 D3 D2 D1 D0PTMDH — — — — — — D9 D8PTMAL D7 D6 D5 D4 D3 D2 D1 D0PTMAH — — — — — — D9 D8PTMRPL D7 D6 D5 D4 D3 D2 D1 D0PTMRPH — — — — — — D9 D8

10-bit Periodic TM Register List




PTMC0 RegisterBit 7 6 5 4 3 2 1 0

Name PTPAU PTCK2 PTCK1 PTCK0 PTON — — —R/W R/W R/W R/W R/W R/W — — —POR 0 0 0 0 0 — — —

Bit7 PTPAU:PTMCounterPauseControl0:Run1:Pause

Thecountercanbepausedbysettingthisbithigh.Clearingthebit tozerorestoresnormalcounteroperation.WheninaPauseconditionthePTMwillremainpoweredupandcontinuetoconsumepower.Thecounterwillretainitsresidualvaluewhenthisbitchangesfromlowtohighandresumecountingfromthisvaluewhenthebitchangestoalowvalueagain.

Bit6~4 PTCK2~PTCK0:SelectPTMCounterclock000:fSYS/4001:fSYS

010:fH/16011:fH/64100:fSUB

101:fSUB

110:PTCKrisingedgeclock111:PTCKfallingedgeclock

ThesethreebitsareusedtoselecttheclocksourceforthePTM.Theexternalpinclocksourcecanbechosentobeactiveontherisingorfallingedge.TheclocksourcefSYSisthesystemclock,whilefHandfSUBareotherinternalclocks,thedetailsofwhichcanbefoundintheoscillatorsection.

Bit3 PTON:PTMCounterOn/OffControl0:Off1:On

Thisbitcontrolstheoverallon/offfunctionofthePTM.Settingthebithighenablesthecounter torun,clearingthebitdisables thePTM.Clearingthisbit tozerowillstop thecounterfromcountingand turnoff thePTMwhichwill reduce itspowerconsumption.Whenthebitchangesstatefromlowtohightheinternalcountervaluewillbereset tozero,howeverwhenthebitchangesfromhighto low, the internalcounterwillretainitsresidualvalueuntilthebitreturnshighagain.IfthePTMisintheCompareMatchOutputMode,PWMoutputModeorSinglePulseOutputModethenthePTMoutputpinwillberesettoitsinitialcondition,asspecifiedbythePTOCbit,whenthePTONbitchangesfromlowtohigh.

Bit2~0 Unimplemented,readas"0"




PTMC1 RegisterBit 7 6 5 4 3 2 1 0

Name PTM1 PTM0 PTIO1 PTIO0 PTOC PTPOL PTCAPTS PTCCLRR/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~6 PTM1~PTM0:SelectPTMOperatingMode00:CompareMatchOutputMode01:CaptureInputMode10:PWMOutputModeorSinglePulseOutputMode11:Timer/CounterMode

ThesebitssetuptherequiredoperatingmodeforthePTM.ToensurereliableoperationthePTMshouldbeswitchedoffbeforeanychangesaremadetothePTM1andPTM0bits.IntheTimer/CounterMode,thePTMoutputpinstateisundefined.

Bit5~4 PTIO1~PTIO0:SelectPTMpinPTPorPTCKfunctionCompareMatchOutputMode00:Nochange01:Outputlow10:Outputhigh11:Toggleoutput

PWMOutputMode/SinglePulseOutputMode00:PWMOutputinactivestate01:PWMOutputactivestate10:PWMoutput11:Singlepulseoutput

CaptureInputMode00:InputcaptureatrisingedgeofPTPorPTCK01:InputcaptureatfallingedgeofPTPorPTCK10:Inputcaptureatfalling/risingedgeofPTPorPTCK11:Inputcapturedisabled

Timer/CounterModeUnused

ThesetwobitsareusedtodeterminehowthePTMoutputpinchangesstatewhenacertainconditionisreached.ThefunctionthatthesebitsselectdependsuponinwhichmodethePTMisrunning.IntheCompareMatchOutputMode,thePTIO1andPTIO0bitsdeterminehowthePTMoutputpinchangesstatewhenacomparematchoccursfromtheComparatorA.ThePTMoutputpincanbesetuptoswitchhigh,switchlowortotoggleitspresentstatewhenacomparematchoccursfromtheComparatorA.Whenthebitsarebothzero,thennochangewilltakeplaceontheoutput.TheinitialvalueofthePTMoutputpinshouldbesetupusingthePTOCbitinthePTMC1register.NotethattheoutputlevelrequestedbythePTIO1andPTIO0bitsmustbedifferentfromtheinitialvaluesetupusingthePTOCbitotherwisenochangewilloccuronthePTMoutputpinwhenacomparematchoccurs.AfterthePTMoutputpinchangesstate,itcanberesettoitsinitiallevelbychangingthelevelofthePTONbitfromlowtohigh.In thePWMOutputMode, thePTIO1andPTIO0bitsdeterminehow thePTMoutputpinchangesstatewhenacertaincomparematchconditionoccurs.ThePWMoutputfunctionismodifiedbychangingthesetwobits.Itisnecessarytoonlychangethevaluesof thePTIO1andPTIO0bitsonlyafter theTMhasbeenswitchedoff.UnpredictablePWMoutputswilloccur if thePTIO1andPTIO0bitsarechangedwhenthePTMisrunning.




Bit3 PTOC:PTMPTPOutputcontrolbitCompareMatchOutputMode0:Initiallow1:Initialhigh

PWMOutputMode/SinglePulseOutputMode0:Activelow1:Activehigh

This is theoutputcontrolbit for thePTMoutputpin. ItsoperationdependsuponwhetherPTMisbeingused in theCompareMatchOutputModeor in thePWMOutputMode/SinglePulseOutputMode.IthasnoeffectifthePTMisintheTimer/CounterMode.IntheCompareMatchOutputModeitdeterminesthelogiclevelofthePTMoutputpinbeforeacomparematchoccurs. In thePWMOutputMode itdeterminesifthePWMsignalisactivehighoractivelow.

Bit2 PTPOL:PTMPTPOutputpolarityControl0:Non-invert1:Invert

ThisbitcontrolsthepolarityofthePTPoutputpin.WhenthebitissethighthePTMoutputpinwillbeinvertedandnotinvertedwhenthebitiszero.IthasnoeffectifthePTMisintheTimer/CounterMode.

Bit1 PTCAPTS:PTMCaptureTriggerSourceSelection0:FromPTPpin1:FromPTCKpin

Bit0 PTCCLR:SelectPTMCounterclearcondition0:PTMComparatorPmatch1:PTMComparatorAmatch

Thisbit isused toselect themethodwhichclears thecounter.Remember that thePeriodicTMcontains twocomparators,ComparatorAandComparatorP,eitherofwhichcanbeselectedtoclear theinternalcounter.With thePTCCLRbitsethigh,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorA.Whenthebitislow,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorPorwithacounteroverflow.AcounteroverflowclearingmethodcanonlybeimplementediftheCCRPbitsareallclearedtozero.ThePTCCLRbitisnotusedinthePWMOutputMode,SinglePulseorCaptureInputMode.

PTMDL RegisterBit 7 6 5 4 3 2 1 0

Name D7 D6 D5 D4 D3 D2 D1 D0R/W R R R R R R R RPOR 0 0 0 0 0 0 0 0

Bit7~0 D7~D0:PTMCounterLowByteRegisterbit7~bit0PTM10-bitCounterbit7~bit0

PTMDH RegisterBit 7 6 5 4 3 2 1 0

Name — — — — — — D9 D8R/W — — — — — — R RPOR — — — — — — 0 0

Bit7~2 Unimplemented,readas"0"Bit1~0 D9~D8:PTMCounterHighByteRegisterbit1~bit0

PTM10-bitCounterbit9~bit8




PTMAL RegisterBit 7 6 5 4 3 2 1 0


Bit7~0 D7~D0:PTMCCRALowByteRegisterbit7~bit0PTM10-bitCCRAbit7~bit0

PTMAH RegisterBit 7 6 5 4 3 2 1 0


Bit7~2 Unimplemented,readas"0"Bit1~0 D9~D8:PTMCCRAHighByteRegisterbit1~bit0

PTM10-bitCCRAbit9~bit8

PTMRPL RegisterBit 7 6 5 4 3 2 1 0


Bit7~0 D7~D0:PTMCCRPLowByteRegisterbit7~bit0PTM10-bitCCRPbit7~bit0

PTMRPH RegisterBit 7 6 5 4 3 2 1 0


Bit7~2 Unimplemented,readas"0"Bit1~0 D9~D8:PTMCCRPHighByteRegisterbit1~bit0

PTM10-bitCCRPbit9~bit8




Periodic Type TM Operating Modes ThePeriodicTypeTMcanoperateinoneoffiveoperatingmodes,CompareMatchOutputMode,PWMOutputMode,SinglePulseOutputMode,CaptureInputModeorTimer/CounterMode.TheoperatingmodeisselectedusingthePTM1andPTM0bitsinthePTMC1register.

Compare Match Output Mode Toselectthismode,bitsPTM1andPTM0inthePTMC1register,shouldbesetto00respectively.Inthismodeoncethecounterisenabledandrunningitcanbeclearedbythreemethods.Theseareacounteroverflow,acomparematchfromComparatorAandacomparematchfromComparatorP.WhenthePTCCLRbitislow,therearetwowaysinwhichthecountercanbecleared.OneiswhenacomparematchfromComparatorP,theotheriswhentheCCRPbitsareallzerowhichallowsthecountertooverflow.HerebothPTMAFandPTMPFinterruptrequestflagsforComparatorAandComparatorPrespectively,willbothbegenerated.

IfthePTCCLRbitinthePTMC1registerishighthenthecounterwillbeclearedwhenacomparematchoccursfromComparatorA.However,hereonlythePTMAFinterruptrequestflagwillbegeneratedevenifthevalueoftheCCRPbitsislessthanthatoftheCCRAregisters.ThereforewhenPTCCLRishighnoPTMPFinterruptrequestflagwillbegenerated.IntheCompareMatchOutputMode,theCCRAcannotbeclearedtozero.

IftheCCRAbitsareallzero,thecounterwilloverflowwhenitsreachesitsmaximum10-bit,3FFHex,value,howeverherethePTMAFinterruptrequestflagwillnotbegenerated.

Asthenameofthemodesuggests,afteracomparisonismade,thePTMoutputpin,willchangestate.ThePTMoutputpinconditionhoweveronlychangesstatewhenaPTMAFinterruptrequestflagisgeneratedafteracomparematchoccursfromComparatorA.ThePTMPFinterruptrequestflag,generatedfromacomparematchoccursfromComparatorP,willhavenoeffectonthePTMoutputpin.ThewayinwhichthePTMoutputpinchangesstatearedeterminedbytheconditionofthePTIO1andPTIO0bitsinthePTMC1register.ThePTMoutputpincanbeselectedusingthePTIO1andPTIO0bitstogohigh,togolowortotogglefromitspresentconditionwhenacomparematchoccursfromComparatorA.TheinitialconditionofthePTMoutputpin,whichissetupafterthePTONbitchangesfromlowtohigh,issetupusingthePTOCbit.Notethatif thePTIO1andPTIO0bitsarezerothennopinchangewilltakeplace.




Counter Value

0x3FF

CCRP

CCRA

PTON

PTPAU

PTPOL

CCRP Int. Flag PTMPF

CCRA Int. Flag PTMAF

PTM O/P Pin

Time

CCRP=0

CCRP > 0

Counter overflowCCRP > 0

Counter cleared by CCRP value

Pause

Resume

Stop

Counter Restart

PTCCLR = 0; PTM[1:0] = 00

Output pin set to initial Level Low if PTOC=0

Output Toggle with PTMAF flag

Note PTIO [1:0] = 10 Active High Output selectHere PTIO [1:0] = 11


Output not affected by PTMAF flag. Remains High until reset by PTON bit



Output Invertswhen PTPOL is high

Compare Match Output Mode – PTCCLR=0 Note:1.WithPTCCLR=0aComparatorPmatchwillclearthecounter

2.ThePTMoutputpiniscontrolledonlybythePTMAFflag3.TheoutputpinisresettoitsinitialstatebyaPTONbitrisingedge




Counter Value

0x3FF

CCRP

CCRA

PTON

PTPAU

PTPOL



PTM O/P Pin

Time

CCRA=0

CCRA = 0Counter overflowCCRA > 0 Counter cleared by CCRA value

Pause

Resume

Stop Counter Restart

PTCCLR = 1; PTM[1:0] = 00

Output pin set to initial Level Low if PTOC=0

Output Toggle with PTMAF flag

Note PTIO [1:0] = 10 Active High Output selectHere PTIO [1:0] = 11


Output not affected by PTMAF flag. Remains High until reset by PTON bit



Output Invertswhen PTPOL is high

PTMPF not generated

No PTMAF flag generated on CCRA overflow

Output does not change

Compare Match Output Mode – PTCCLR=1Note:1.WithPTCCLR=1aComparatorAmatchwillclearthecounter

2.ThePTMoutputpiniscontrolledonlybythePTMAFflag3.TheoutputpinisresettoitsinitialstatebyaPTONbitrisingedge4.APTMPFflagisnotgeneratedwhenPTCCLR=1




Timer/Counter Mode Toselectthismode,bitsPTM1andPTM0inthePTMC1registershouldbesetto11respectively.TheTimer/CounterModeoperates in an identicalway to theCompareMatchOutputModegeneratingthesameinterruptflags.TheexceptionisthatintheTimer/CounterModetheTMoutputpin isnotused.Therefore theabovedescriptionandTimingDiagramsfor theCompareMatchOutputModecanbeusedtounderstanditsfunction.AstheTMoutputpinisnotusedinthismode,thepincanbeusedasanormalI/Opinorotherpin-sharedfunction.

PWM Output Mode Toselectthismode,bitsPTM1andPTM0inthePTMC1registershouldbesetto10respectively.ThePWMfunctionwithinthePTMisusefulforapplicationswhichrequirefunctionssuchasmotorcontrol,heatingcontrol, illuminationcontroletc.ByprovidingasignaloffixedfrequencybutofvaryingdutycycleonthePTMoutputpin,asquarewaveACwaveformcanbegeneratedwithvaryingequivalentDCRMSvalues.

AsboththeperiodanddutycycleofthePWMwaveformcanbecontrolled,thechoiceofgeneratedwaveformisextremelyflexible.InthePWMOutputMode,thePTCCLRbithasnoeffectonthePWMoperation.BothoftheCCRAandCCRPregistersareusedtogeneratethePWMwaveform,oneregister isusedtocleartheinternalcounterandthuscontrol thePWMwaveformfrequency,whiletheotheroneisusedtocontrolthedutycycle.ThePWMwaveformfrequencyanddutycyclecanthereforebecontrolledbythevaluesintheCCRAandCCRPregisters.

Aninterruptflag,oneforeachoftheCCRAandCCRP,willbegeneratedwhenacomparematchoccursfromeitherComparatorAorComparatorP.ThePTOCbitinthePTMC1registerisusedtoselecttherequiredpolarityofthePWMwaveformwhilethetwoPTIO1andPTIO0bitsareusedtoenablethePWMoutputortoforcethePTMoutputpintoafixedhighorlowlevel.ThePTPOLbitisusedtoreversethepolarityofthePWMoutputwaveform.

• 10-bit PTM, PWM Output Mode, Edge-aligned Mode

CCRP 1~1023 0Period 1~1023 1024Duty CCRA

IffSYS=12MHz,PTMclocksourceselectfSYS/4,CCRP=512andCCRA=128,

ThePTMPWMoutputfrequency=(fSYS/4)/512=fSYS/2048=5.8594kHz,duty=128/(2×256)=25%.

IftheDutyvaluedefinedbytheCCRAregisterisequaltoorgreaterthanthePeriodvalue,thenthePWMoutputdutyis100%.




Counter Value

CCRP

CCRA

PTON

PTPAU

PTPOL



PTM O/P Pin(PTOC=1)

Time


Pause Resume Counter Stop if PTON bit low

Counter Reset when PTON returns high

PTM[1:0] = 10

PWM Duty Cycle set by CCRA PWM resumes

operationOutput controlled by other pin-shared function Output Inverts

When PTPOL = 1PWM Period set by CCRP

PTM O/P Pin(PTOC=0)

PWM Output Mode Note:1.CounterclearedbyCCRP

2.AcounterclearsetsthePWMPeriod3.TheinternalPWMfunctioncontinuesrunningevenwhenPTIO[1:0]=00or014.ThePTCCLRbithasnoinfluenceonPWMoperation




Single Pulse ModeToselectthismode,bitsPTM1andPTM0inthePTMC1registershouldbesetto10respectivelyandalsothePTIO1andPTIO0bitsshouldbesetto11respectively.TheSinglePulseOutputMode,asthenamesuggests,willgenerateasingleshotpulseonthePTMoutputpin.

ThetriggerforthepulseoutputleadingedgeisalowtohightransitionofthePTONbit,whichcanbeimplementedusingtheapplicationprogram.HoweverintheSinglePulseMode,thePTONbitcanalsobemadetoautomaticallychangefromlowtohighusingtheexternalPTCKpin,whichwillinturninitiatetheSinglePulseoutput.WhenthePTONbittransitionstoahighlevel,thecounterwillstartrunningandthepulseleadingedgewillbegenerated.ThePTONbitshouldremainhighwhenthepulseisinitsactivestate.ThegeneratedpulsetrailingedgewillbegeneratedwhenthePTONbit isclearedtozero,whichcanbeimplementedusingtheapplicationprogramorwhenacomparematchoccursfromComparatorA.

HoweveracomparematchfromComparatorAwillalsoautomaticallyclearthePTONbitandthusgeneratetheSinglePulseoutputtrailingedge.InthiswaytheCCRAvaluecanbeusedtocontrolthepulsewidth.AcomparematchfromComparatorAwillalsogenerateaPTMinterrupt.Thecountercanonlyberesetback tozerowhen thePTONbitchangesfromlowtohighwhen thecounterrestarts.IntheSinglePulseModeCCRPisnotused.ThePTCCLRbitisnotusedinthisMode.

PTON bit0 à 1

S/W Command SET“PTON”

orPTCK Pin Transition

PTON bit1 à 0

CCRA Trailing Edge

S/W Command CLR“PTON”

orCCRA Compare Match

PTP Output Pin

Pulse Width = CCRA Value

CCRA Leading Edge

Single Pulse Generation




Counter Value

CCRP

CCRA

PTON

PTPAU

PTPOL



PTM O/P Pin(PTOC=1)

Time

Counter stopped by CCRA

PauseResume Counter Stops by

software

Counter Reset when PTON returns high

PTM[1:0] = 10 ; PTIO[1:0] = 11

Pulse Width set by CCRA

Output Invertswhen PTPOL = 1

No CCRP Interrupts generated

PTM O/P Pin(PTOC=0)

PTCK pin

Software Trigger

Cleared by CCRA match

PTCK pin Trigger

Auto. set by PTCK pin

Software Trigger

Software Clear

Software TriggerSoftware

Trigger

Single Pulse Mode Note:1.CounterstoppedbyCCRA

2.CCRPisnotused3.ThepulseistriggeredbythePTCKpinorbysettingthePTONbithigh4.APTCKpinactiveedgewillautomaticallysetthePTONbithigh5.IntheSinglePulseMode,PTIO[1:0]mustbesetto"11"andcannotbechanged.




Capture Input Mode ToselectthismodebitsPTM1andPTM0inthePTMC1registershouldbesetto01respectively.Thismodeenablesexternalsignals tocaptureandstore thepresentvalueof theinternalcounterandcanthereforebeusedforapplicationssuchaspulsewidthmeasurements.TheexternalsignalissuppliedonthePTPorPTCKpinwhichisselectedusingthePTCAPTSbitinthePTMC1register.Theinputpinactiveedgecanbeeitherarisingedge,afallingedgeorbothrisingandfallingedges;theactiveedgetransitiontypeisselectedusingthePTIO1andPTIO0bitsinthePTMC1register.Thecounter isstartedwhenthePTONbitchangesfromlowtohighwhichis initiatedusingtheapplicationprogram.

WhentherequirededgetransitionappearsonthePTPorPTCKpinthepresentvalueinthecounterwillbelatchedintotheCCRAregistersandaPTMinterruptgenerated.IrrespectiveofwhateventsoccuronthePTPorPTCKpin,thecounterwillcontinuetofreerununtil thePTONbitchangesfromhightolow.WhenaCCRPcomparematchoccursthecounterwillresetbacktozero;inthiswaytheCCRPvaluecanbeusedtocontrolthemaximumcountervalue.WhenaCCRPcomparematchoccursfromComparatorP,aPTMinterruptwillalsobegenerated.CountingthenumberofoverflowinterruptsignalsfromtheCCRPcanbeausefulmethodinmeasuringlongpulsewidths.ThePTIO1andPTIO0bitscanselecttheactivetriggeredgeonthePTPorPTCKpintobearisingedge,fallingedgeorbothedgetypes.IfthePTIO1andPTIO0bitsarebothsethigh,thennocaptureoperationwilltakeplaceirrespectiveofwhathappensonthePTPorPTCKpin,howeveritmustbenotedthatthecounterwillcontinuetorun.

AsthePTPorPTCKpinispinsharedwithotherfunctions,caremustbetakenifthePTMisintheCaptureInputMode.Thisisbecauseifthepinissetupasanoutput,thenanytransitionsonthispinmaycauseaninputcaptureoperationtobeexecuted.ThePTCCLR,PTOCandPTPOLbitsarenotusedinthisMode.




Counter Value

YY

CCRP

PTON

PTPAU



CCRA Value

Time


PauseResume

Counter Reset

PTM[1:0] = 01

PTM Capture PinPTP or PTCK

XX

Counter Stop

PTIO [1:0] Value

Active edge

Active edge Active edge

00 - Rising edge 01 - Falling edge 10 - Both edges 11 - Disable Capture

XX YY XX YY

Capture Input ModeNote:1.PTM[1:0]=01andactiveedgesetbythePTIO[1:0]bits

2.APTMCaptureinputpinactiveedgetransfersthecountervaluetoCCRA3.PTCCLRbitnotused4.Nooutputfunction–PTOCandPTPOLbitsarenotused5.CCRPdeterminesthecountervalueandthecounterhasamaximumcountvaluewhenCCRPisequaltozero.




Nebuliser Resonance DetectorPleasereferHoltekApplicatoinNotes.

Water Shortage ProtectionDevelopedbyusers.

Over Current/Voltage ProtectionThedeviceincludesanovercurrent/voltageprotectionfunctionwhichprovidesanovercurrentorovervoltageprotectionprotectionmechanismforapplications.Thecurrenton theOCVPAI0pinisconvertedtoarelevantvoltagelevelaccordingtothecurrentvalueusingtheOCVPoperationalamplifier. It is thencomparedwitha referencevoltagegeneratedbyan8-bitD/Aconverter.ThevoltageontheOCVPCIpiniscomparedwithareferencevoltagegeneratedbythe8-bitD/Aconverter.WhentheOCVPFflagchangesfrom0to1andifthecorrespondinginterruptcontrolisenabled,anOCVPinterruptwillbegeneratedtoindicateaspecificcurrentorvoltageconditionhasoccurred.

OCVPDA[7:0]

Debounce

R1

R2

2kΩ or 4kΩ

OCVPO

S3

S2

S4

S5

OCVPG[2:0]

fDEB=fSYS

OCVPSWn(n=0~6)

OPAOCVPSPOL

OCVPCOUT

OCVPDEB[2:0]

OCVPINTCMP

OCVPCPS

OCVPEN

OCVPCI

OCVPEN

OCVPSW7

S7OCVPG2XEN

S6

OCVPAI0S1

S0

OCVPCHY

OCVPEN

OCVPS[1:0]

VDD

VREF

OCVPVRS

8-bitDAC

PinControl

OCVP Block Diagram

OCVP OperationTheOCVPcircuitisusedtopreventtheinputcurrentorvoltagefrombeinginanunexpectedlevelrange.ThecurrentontheOCVPAI0pinisconvertedtoavoltageandthenamplifiedbytheOCVPoperationalamplifierwithaprogrammablegainfrom1to65selectedbytheOCVPG2~OCVPG0bits in theOCVPC2register.This isknownas theProgrammableGainAmplifierorPGA.ThisPGAcanalsobeconfiguredtooperateinthenon-inverting,invertingorinputoffsetcancellationmodedeterminedbytheOCVPSW7~OCVPSW0bits in theOCVPC0register.After thecurrentisconvertedandamplifiedtoaspecificvoltagelevel,itwillbecomparedwithareferencevoltageprovidedbyan8-bitD/Aconverter.Thevoltageon theOCVPCIpin isalsocanbeselected tocomparewithareferenceprovidedbythe8-bitD/Aconverter.TocomparetheOCVPAOoutputsignalortheOCVPCIinputsignalwiththeD/AconverteroutputvoltageisselectedusingtheOCVPCPSbitintheOCVPC1register.The8-bitD/Aconverterpowercanbesuppliedbytheexternalpowerpin,VDDorVREF,selectedbytheOCVPVRSbit in theOCVPC1register.Thecomparatoroutput,OCVPCOUT,will firstbefilteredwithacertainde-bouncetimeperiodselectedbytheOCVPDEB2~OCVPDEB0bitsintheOCVPC2register.ThenafilteredOCVPdigitalcomparatoroutput,OCVPO,isobtainedtoindicatewhetherauser-definedcurrentorvoltageconditionoccursornot.




IftheOCVPSPOLbitisclearedto0andthecomparatorinputsforcetheOCVPObittochangefrom0to1,oriftheOCVPSPOLbitissetto1andthecomparatorinputsforcetheOCVPObitchangesfrom1to0, thecorrespondinginterruptwillbegeneratedif therelevantinterruptcontrolbit isenabled.Itisimportanttonotethat,onlyanOCVPINTrisingedgecantriggeranOCVPinterruptrequest,sotheOCVPSPOLbitmustbeproperlyconfiguredaccordingtouser’sapplicationrequirements.ThecomparatorintheOCVPcircuitalsohashysteresisfunctioncontrolledbyOCVPCHYbit.Notethatthedebounceclock,fDEB,comesfromthesystemclock,fSYS.TheDACoutputvoltageiscontrolledbytheOCVPDAregisterandtheDACoutputisdefinedasbelow:

DACVOUT=(DACreferencevoltage/256)×D[7:0]

OCVP Control RegistersOveralloperationoftheOCVPfunctioniscontrolledusingseveralregisters.TheCTRL2registerisused toselect theOCVPinputsignal inputpin.Oneregister isused toprovide thereferencevoltagesfortheOCVPcircuit.Tworegistersareusedfortheoperationalamplifierandcomparatorinputoffsetcalibration.The remaining three registersarecontrol registerswhichcontrol theOCVPfunction,D/Aconverterreferencevoltageselect,switcheson/offcontrol,PGAgainselect,comparatornon-invertinginputselect,comparatorde-bouncetime,comparatorhysteresisfunctionandcomparatoroutputpolaritycontrol,etc.Foramoredetaileddescriptionregardingthe inputoffsetvoltagecancellationprocedures,refertothecorrespondinginputoffsetcancellationsections.

Register Name

Bit7 6 5 4 3 2 1 0

CTRL2 — — — — — — OCVPS1 OCVPS0OCVPDA D7 D6 D5 D4 D3 D2 D1 D0OCVPC0 OCVPSW7 OCVPSW6 OCVPSW5 OCVPSW4 OCVPSW3 OCVPSW2 OCVPSW1 OCVPSW0OCVPC1 OCVPEN OCVPCHY OCVPO OCVPSPOL — — OCVPCPS OCVPVRSOCVPC2 — OCVPG2XEN OCVPG2 OCVPG1 OCVPG0 OCVPDEB2 OCVPDEB1 OCVPDEB0

OCVPOCAL OCVPOOFM OCVPORSP OCVPOOF5 OCVPOOF4 OCVPOOF3 OCVPOOF2 OCVPOOF1 OCVPOOF0OCVPCCAL OCVPCOUT OCVPCOFM OCVPCRSP OCVPCOF4 OCVPCOF3 OCVPCOF2 OCVPCOF1 OCVPCOF0

OCVP Register List

CTRL2 RegisterBit 7 6 5 4 3 2 1 0

Name — — — — — — OCVPS1 OCVPS0R/W — — — — — — R/W R/WPOR — — — — — — 0 0

Bit7~2 Unimplemented,readas"0"Bit1~0 OCVPS1 ~ OCVPS0:OCVPAI0InputSourcePinSelection

00:OCVPAI0onPA401:OCVPAI0onPA310:OCVPAI0onPA611:OCVPAI0onPA7




OCVPC0 RegisterBit 7 6 5 4 3 2 1 0

Name OCVPSW7 OCVPSW6 OCVPSW5 OCVPSW4 OCVPSW3 OCVPSW2 OCVPSW1 OCVPSW0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 1 1 0 0 1 0 0 0

Bit7 OCVPSW7:OCVPswitchS7on/offcontrol0:Off1:On









Name OCVPEN OCVPCHY OCVPO OCVPSPOL — — OCVPCPS OCVPVRSR/W R/W R/W R R/W — — R/W R/WPOR 0 0 0 0 — — 0 0

Bit7 OCVPEN:OCVPfunctionenablecontrol0:Disable1:Enable

Whenthisbit isclearedto0, theoverallOCVPoperationwillbedisabledandthecomparatoroutput,OCVPCOUT,willbeequalto0.

Bit6 OCVPCHY:OCVPComparatorHysteresisfunctioncontrol0:Disable1:Enable

Bit5 OCVPO:OCVPComparatordebounceoutputThisbitisthedebounceversionoftheOCVPCOUTbit.

Bit4 OCVPSPOL:OCVPOpolaritycontrol0:Non-invert1:Invert

Bit3~2 Unimplemented,readas"0"




Bit1 OCVPCPS:OCVPComparatornon-invertinginputselection0:FromOCVPAOsignal1:FromOCVPCIpin

Bit0 OCVPVRS:OCVPD/AConverterreferencevoltageselection0:FromVDD

1:FromVREFpin


Name — OCVPG2XEN OCVPG2 OCVPG1 OCVPG0 OCVPDEB2 OCVPDEB1 OCVPDEB0R/W — R/W R/W R/W R/W R/W R/W R/WPOR — 0 0 0 0 0 0 0

Bit7 Unimplemented,readas"0"Bit6 OCVPG2XEN:R2/R1ratiodoublingenablecontrol

0:Disable(R1=4kΩ)1:Enable(R1=2kΩ)

Whenthisbit is1, theR2/R1ratioselectedbytheOCVPG2~OCVPG0bitswillbedoubled.

Bit5~3 OCVPG2~OCVPG0:PGAR2/R1ratioselection000:R2/R1=1001:R2/R1=4010:R2/R1=6011:R2/R1=10100:R2/R1=15101:R2/R1=25110:R2/R1=40111:R2/R1=65

The internal resistors,R1andR2,shouldbeusedwhen thegain isdeterminedbythesebits.ThismeanstheS4orS5switchtogetherwiththeS7switchshouldbeon.Otherwise,thegainaccuracywillnotbeguaranteed.WhentheOCVPG2XENbitissetto1toenabletheR2/R1ratiodoublingfunction,theaboveR2/R1valueswillbedoubled.ThecalculatingformulaofthePGAgainfortheinvertingandnon-invertingmodeisdescribedinthe"InputVoltageRange"section.

Bit2~0 OCVPDEB2~OCVPDEB0:OCVPComparatoroutputdebouncetimecontrol000:Bypass,nodebounce001:(1~2)×tDEB010:(3~4)×tDEB011:(7~8)×tDEB100:(15~16)×tDEB101:(31~32)×tDEB110:(63~64)×tDEB111:(127~128)×tDEB

Note:fDEB=fSYS,tDEB=1/fDEB

OCVPDA RegisterBit 7 6 5 4 3 2 1 0


Bit7~0 OCVPD/AConverterDataRegisterbit7~bit0OCVPD/AConverterOutput=(DACreferencevoltage/256)×D[7:0]




OCVPOCAL RegisterBit 7 6 5 4 3 2 1 0

Name OCVPOOFM OCVPORSP OCVPOOF5 OCVPOOF4 OCVPOOF3 OCVPOOF2 OCVPOOF1 OCVPOOF0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 1 0 0 0 0 0

Bit7 OCVPOOFM:OCVPOperationalAmplifieroperatingmodeselection0:Normaloperatingmode1:Offsetcancellationmode

ThisbitisusedtoselecttheOCVPoperatingmode.Toselecttheoperationalamplifierinputoffsetcancellationmode, theOCVPSW7~OCVPSW0bitsmustfirstbeset to28HandthentheOCVPOOFMbitmustbeset to1followedbytheOCVPCOFMbitbeingclearedto0.Refertothe"OperationalAmplifierInputOffsetCancellation"sectionforthedetailedoffsetcancellationprocedures.

Bit6 OCVPORSP:OCVPOperationalAmplifierinputoffsetvoltagecancellationreferenceselection0:Operationalamplifierinvertinginputisselected1:Operationalamplifiernon-vertinginputisselected

Bit5~0 OCVPOOF5~OCVPOOF0:OCVPOperationalAmplifierinputoffsetvoltagecancellationvalueThis6-bitfieldisusedtoperformtheoperationalamplifierinputoffsetcancellationoperationandthevaluefortheOCVPoperationalamplifierinputoffsetcancellationcanbe restored into thisbit field.Moredetailed information isdescribed in the"OperationalAmplifierInputOffsetCancellation"section.

OCVPCCAL RegisterBit 7 6 5 4 3 2 1 0

Name OCVPCOUT OCVPCOFM OCVPCRSP OCVPCOF4 OCVPCOF3 OCVPCOF2 OCVPCOF1 OCVPCOF0

R/W R R/W R/W R/W R/W R/W R/W R/W

POR 0 0 0 1 0 0 0 0

Bit7 OCVPCOUT:OCVPComparatoroutput0:Non-vertinginputvoltage<DACoutputvoltage1:Non-vertinginputvoltage>DACoutputvoltage

Thisbit isusedtoindicatewhetherthenon-vertinginputvoltageisgreaterthantheDACoutputvoltage.IftheOCVPCOUTissetto1,thenon-vertinginputvoltageisgreaterthantheDACoutputvoltage.Otherwise,thenon-vertinginputvoltageislessthantheDACoutputvoltage.ThisbitvaluecanbeoutputontheOCVPCOUTpin.

Bit6 OCVPCOFM:OCVPComparatoroperatingmodeselection0:Normaloperatingmode1:Offsetcancellationmode

Thisbit is used to select theOCVPcomparatoroperatingmode.To select thecomparator inputoffsetcancellationmode, theOCVPSW7~OCVPSW0bitsmustfirstbe set to28Hand then theOCVPCOFMbitmustbe set to1 followedbytheOCVPOOFMbitbeingcleared to0.Refer to the "Comparator InputOffsetCancellation"sectionforthedetailedoffsetcancellationprocedures.

Bit5 OCVPCRSP:OCVPComparatorinputoffsetvoltagecancellationreferenceselection0:Invertinginputasthereferenceinput1:Non-invertinginputisselectedasthereferenceinput

Bit4~0 OCVPCOF4~OCVPCOF0:OCVPComparatorinputoffsetvoltagecancellationvalueThis5-bitfieldisusedtoperformthecomparatorinputoffsetcancellationoperationandthevaluefortheOCVPcomparatorinputoffsetcancellationcanberestoredintothisbitfield.Moredetailedinformationisdescribedinthe"ComparatorInputOffsetCancellation"section.




Input Voltage RangeTogetherwithdifferentPGAoperatingmodes, the inputvoltagecanbepositiveornegative toprovidediverseapplicationsforthedevice.ThePGAoutputforthepositiveornegativeinputvoltageisrespectivelycalculatedbasedondifferentformulasanddescribedbythefollowingexamples.

• ForVIN>0,thePGAoperatesinthenon-invertingmodeandthePGAoutputisobtainedusingtheformulabelow:

IN1

2OUT V)

RR(1V x

• WhenthePGAoperatesinthenon-invertingmode,aunitygainbufferisprovided.IfOCVPSW6~OCVPSW4bitsaresetto"000",thePGAgainwillbe1andthePGAwillactasaunitygainbuffer.TheswitchesS6,S5andS4willbeoffinternallyandtheoutputvoltageofPGAis:

INOUT VV

• IfS3andS4areon,theinputnodeisOCVPAI0.Forinputvoltage0>VIN>-0.4,thePGAoperatesintheinvertingmodeandthePGAoutputisobtainedusingtheformulabelow.NotethatiftheinputvoltageVINisnegative,itcannotbelowerthan-0.4Vwhichwillresultincurrentleakage.

IN1

2OUT V

RRV x

Offset CalibrationTooperateintheinputoffsetcancellationmodefortheOCVPcircuit,theOCVPSW7~OCVPSW0bitsshouldfirstbesetto28H.Foroperationalamplifierandcomparatorinputoffsetcancellation,theproceduresaresimilarexceptforsettingtherespectivecontrolbits.

Operational Amplifier Input Offset Cancellation Step1.SetOCVPSW[7:0]=28H(S3andS5areon,otherswitchesareoff),OCVPOOFM=1,

OCVPCOFM=0andOCVPORSP=1, theOCVPwilloperate intheoperationalamplifierinputoffsetcancellationmode.

Step2.SetOCVPDA[7:0]=40H

Step3.SetOCVPOOF[5:0]=000000andreadtheOCVPCOUTbit.

Step4.IncreasetheOCVPOOF[5:0]valueby1andthenreadtheOCVPCOUTbit.IftheOCVPCOUTbitstatehasnotchanged,thenrepeatStep4untiltheOCVPCOUTbitstatehaschanged.IftheOCVPCOUTbitstatehaschanged,recordtheOCVPOOFvalueasVOOS1andthengotoStep5.

Step5.SetOCVPOOF[5:0]=111111andreadtheOCVPCOUTbit.

Step6.DecreasetheOCVPOOF[5:0]valueby1andthenreadtheOCVPCOUTbit.IftheOCVPCOUTbitstatehasnotchanged,thenrepeatStep6untiltheOCVPCOUTbitstatehaschanged.IftheOCVPCOUTbitstatehaschanged,recordtheOCVPOOFvalueasVOOS2andthengotoStep7.

Step7.RestoretheoperationalamplifierinputoffsetcancellationvalueVOOSintotheOCVPOOF[5:0]bitfield.Theoffsetcancellationprocedureisnowfinished.

Where2

VOOS2VOOS1VOOS




Comparator input Offset Cancellation Beforetheoffsetcalibration,thehysteresisvoltageshouldbezerobysettingtheOCVPCHYbitto0.

Step1.SetOCVPSW[7:0]=28H,OCVPCOFM=1,OCVPOOFM=0andOCVPCRSP=0,theOCVPwillnowoperateinthecomparatorinputoffsetcancellationmode.

Step2.SetOCVPDA[7:0]=40H

Step3.SetOCVPCOF[4:0]=00000andreadtheOCVPCOUTbit.

Step4.IncreasetheOCVPCOF[4:0]valueby1andthenreadtheOCVPCOUTbit.IftheOCVPCOUTbitstatehasnotchanged,thenrepeatStep4untiltheOCVPCOUTbitstatehaschanged.IftheOCVPCOUTbitstatehaschanged,recordtheOCVPCOFvalueasVCOS1andthengotoStep5.

Step5.SetOCVPCOF[4:0]=11111andreadtheOCVPCOUTbit.

Step6.DecreasetheOCVPCOF[4:0]valueby1andthenreadtheOCVPCOUTbit.IftheOCVPCOUTbitstatehasnotchanged,thenrepeatStep6untiltheOCVPCOUTbitstatehaschanged.IftheOCVPCOUTbitstatehaschanged,recordtheOCVPCOFvalueasVCOS2andthengotoStep7.

Step7.RestorethecomparatorinputoffsetcancellationvalueVCOSintotheOCVPCOF[4:0]bitfield.Theoffsetcancellationprocedureisnowfinished.

Where2

VCOS2VCOS1VCOS

InterruptsInterruptsareanimportantpartofanymicrocontrollersystem.WhenanexternaleventoraninternalfunctionsuchasaTimerModuleoranLVDrequiresmicrocontrollerattention,theircorrespondinginterruptwillenforceatemporarysuspensionofthemainprogramallowingthemicrocontrollertodirectattentiontotheirrespectiveneeds.Thedevicecontainsseveralexternalinterruptandinternalinterruptfunctions.TheexternalinterruptisgeneratedbytheactionoftheexternalINT0andINT1pins,while the internal interruptsaregeneratedbyvarious internal functionssuchas theTimerModules(TMs),OverCurrent/VoltageProtectionfunction(OCVP),TimeBase,LVDandEEPROM.

Interrupt RegistersOverall interrupt control,whichbasicallymeans the settingof request flagswhen certainmicrocontrollerconditionsoccurandthesettingofinterruptenablebitsbytheapplicationprogram,iscontrolledbyaseriesofregisters,locatedintheSpecialPurposeDataMemory,asshownintheaccompanyingtable.Theinterruptregistersfallintothreecategories.ThefirstistheINTC0~INTC2registerswhichsetuptheprimaryinterrupts,thesecondistheMFI0~MFI2registerswhichsetuptheMulti-functioninterrupts.FinallythereisanINTEGregistertosetuptheexternalinterrupttriggeredgetype.

Eachregistercontainsanumberofenablebitstoenableordisableindividualregistersaswellasinterrupt flags to indicate thepresenceofan interrupt request.Thenamingconventionof thesefollowsaspecificpattern.Firstislistedanabbreviatedinterrupttype,thenthe(optional)numberofthatinterruptfollowedbyeitheran"E"forenable/disablebitor"F"forrequestflag.




Function Enable Bit Request Flag NotesGlobal EMI — —OCVP OCVPE OCVPF —INTn Pin INTnE INTnF n=0 or 1Multi-function MFnE MFnF n=0~2Time Base TBnE TBnF n=0 or 1LVD LVE LVF —EEPROM DEE DEF —

Timer Module

STMAE STMAF —STMPE STMPF —PTMAE PTMAF —PTMPE PTMPF —

Interrupt Register Bit Naming Conventions

RegisterName

Bit7 6 5 4 3 2 1 0

INTEG — — — — INT1S1 INT1S0 INT0S1 INT0S0INTC0 — — INT0F OCVPF — INT0E OCVPE EMIINTC1 TB0F MF2F MF1F MF0F TB0E MF2E MF1E MF0EINTC2 — — INT1F TB1F — — INT1E TB1EMFI0 — — STMAF STMPF — — STMAE STMPEMFI1 — — PTMAF PTMPF — — PTMAE PTMPEMFI2 — — DEF LVF — — DEE LVE

Interrupt Register List

INTEG Register Bit 7 6 5 4 3 2 1 0

Name — — — — INT1S1 INT1S0 INT0S1 INT0S0R/W — — — — R/W R/W R/W R/WPOR — — — — 0 0 0 0

Bit7~4 Unimplemented,readas"0"Bit3~2 INT1S1, INT1S0:DefinesINT1interruptactiveedge

00:DisabledInterrupt01:RisingEdgeInterrupt10:FallingEdgeInterrupt11:DualEdgeInterrupt

Bit1~0 INT0S1, INT0S0:DefinesINT0interruptactiveedge00:DisabledInterrupt01:RisingEdgeInterrupt10:FallingEdgeInterrupt11:DualEdgeInterrupt




INTC0 RegisterBit 7 6 5 4 3 2 1 0

Name — — INT0F OCVPF — INT0E OCVPE EMIR/W — — R/W R/W — R/W R/W R/WPOR — — 0 0 — 0 0 0

Bit7~6 Unimplemented,readas"0"Bit5 INT0F:Externalinterrupt0requestflag

0:Norequest1:Interruptrequest

Bit4 OCVPF:Overcurrent/voltageprotectioninterruptrequestflag0:Norequest1:Interruptrequest

Bit3 Unimplemented,readas"0"Bit2 INT0E:Externalinterrupt0control

0:Disable1:Enable

Bit1 OCVPE:Overcurrent/voltageprotectioninterruptcontrol0:Disable1:Enable

Bit0 EMI:GlobalInterruptControl0:Disable1:Enable

INTC1 RegisterBit 7 6 5 4 3 2 1 0

Name TB0F MF2F MF1F MF0F TB0E MF2E MF1E MF0ER/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7 TB0F:TimeBase0requestflag0:Norequest1:Interruptrequest

Bit6 MF2F:Multi-functioninterrupt2requestflag0:Norequest1:Interruptrequest



Bit3 TB0E:TimeBase0interruptcontrol0:Disable1:Enable

Bit2 MF2E:Multi-functioninterrupt2control0:Disable1:Enable






INTC2 Register Bit 7 6 5 4 3 2 1 0

Name — — INT1F TB1F — — INT1E TB1ER/W — — R/W R/W — — R/W R/WPOR — — 0 0 — — 0 0

Bit7~6 Unimplemented,readas"0"Bit5 INT1F:Externalinterrupt1requestflag


Bit4 TB1F:TimeBase1interruptrequestflag0:Norequest1:Interruptrequest

Bit3~2 Unimplemented,readas"0"Bit1 INT1E:Externalinterrupt1control

0:Disable1:Enable

Bit0 TB1E:TimeBase1interruptcontrol0:Disable1:Enable

MFI0 Register Bit 7 6 5 4 3 2 1 0

Name — — STMAF STMPF — — STMAE STMPER/W — — R/W R/W — — R/W R/WPOR — — 0 0 — — 0 0

Bit7~6 Unimplemented,readas"0"Bit5 STMAF:STMcomparatorAmatchinterruptrequestflag


Bit4 STMPF:STMcomparatorPmatchinterruptrequestflag0:Norequest1:Interruptrequest

Bit3~2 Unimplemented,readas"0"Bit1 STMAE:STMcomparatorAmatchinterruptcontrol

0:Disable1:Enable

Bit0 STMPE:STMcomparatorPmatchinterruptcontrol0:Disable1:Enable





Name — — PTMAF PTMPF — — PTMAE PTMPER/W — — R/W R/W — — R/W R/WPOR — — 0 0 — — 0 0

Bit7~6 Unimplemented,readas"0"Bit5 PTMAF:PTMcomparatorAmatchinterruptrequestflag


Bit4 PTMPF:PTMcomparatorPmatchinterruptrequestflag0:Norequest1:Interruptrequest

Bit3~2 Unimplemented,readas"0"Bit1 PTMAE:PTMcomparatorAmatchinterruptcontrol

0:Disable1:Enable

Bit0 PTMPE:PTMcomparatorPmatchinterruptcontrol0:Disable1:Enable


Name — — DEF LVF — — DEE LVER/W — — R/W R/W — — R/W R/WPOR — — 0 0 — — 0 0

Bit7~6 Unimplemented,readas"0"Bit5 DEF:DataEEPROMinterruptrequestflag


Bit4 LVF:LVDinterruptrequestflag0:Norequest1:Interruptrequest

Bit3~2 Unimplemented,readas"0"Bit1 DEE:DataEEPROMinterruptcontrol

0:Disable1:Enable

Bit0 LVE:LVDinterruptcontrol0:Disable1:Enable




Interrupt OperationWhentheconditionsforaninterrupteventoccur,suchasaTMComparatorPorComparatorAmatchetc,therelevantinterruptrequestflagwillbeset.Whethertherequestflagactuallygeneratesaprogramjumptotherelevantinterruptvectorisdeterminedbytheconditionoftheinterruptenablebit.Iftheenablebitissethighthentheprogramwilljumptoitsrelevantvector;iftheenablebitiszerothenalthoughtheinterruptrequestflagissetanactualinterruptwillnotbegeneratedandtheprogramwillnotjumptotherelevantinterruptvector.Theglobalinterruptenablebit,ifclearedtozero,willdisableallinterrupts.

Whenaninterruptisgenerated,theProgramCounter,whichstorestheaddressofthenextinstructiontobeexecuted,willbetransferredontothestack.TheProgramCounterwillthenbeloadedwithanewaddresswhichwillbethevalueofthecorrespondinginterruptvector.Themicrocontrollerwillthenfetchitsnextinstructionfromthisinterruptvector.Theinstructionatthisvectorwillusuallybea"JMP"whichwilljumptoanothersectionofprogramwhichisknownastheinterruptserviceroutine.Hereislocatedthecodetocontroltheappropriateinterrupt.Theinterruptserviceroutinemustbe terminatedwitha"RETI",whichretrieves theoriginalProgramCounteraddress fromthestackandallowsthemicrocontrollertocontinuewithnormalexecutionatthepointwheretheinterruptoccurred.

Thevarious interruptenablebits, togetherwith theirassociatedrequest flags,areshownin theaccompanyingdiagrams with theirorderofpriority.Some interrupt sourceshave theirownindividualvectorwhileothersshare thesamemulti-function interruptvector.Oncean interruptsubroutineisserviced,all theother interruptswillbeblocked,as theglobal interruptenablebit,EMIbitwillbeclearedautomatically.Thiswillpreventanyfurtherinterruptnestingfromoccurring.However, ifother interruptrequestsoccurduringthis interval,althoughtheinterruptwillnotbeimmediatelyserviced,therequestflagwillstillberecorded.

Ifaninterruptrequiresimmediateservicingwhiletheprogramisalreadyinanotherinterruptserviceroutine,theEMIbitshouldbesetafterenteringtheroutine,toallowinterruptnesting.Ifthestackisfull,theinterruptrequestwillnotbeacknowledged,eveniftherelatedinterruptisenabled,untiltheStackPointerisdecremented.Ifimmediateserviceisdesired,thestackmustbepreventedfrombecomingfull.Incaseofsimultaneousrequests,theaccompanyingdiagramshowstheprioritythatisapplied.Alloftheinterruptrequestflagswhensetwillwake-upthedeviceifit isinSLEEPorIDLEMode,however topreventawake-upfromoccurringthecorrespondingflagshouldbesetbeforethedeviceisinSLEEPorIDLEMode.




INT0 Pin

INT1 Pin

INT0F

INT1F

INT0E

INT1E

EMI

04H

08H

EMI

Time Base 0 TB0F TB0E EMI

Interrupt Name

Request Flags

Enable Bits

Master Enable Vector

EMI auto disabled in ISR

Priority

High

Low

Interrupts contained within Multi-Function Interrupts

xxE Enable Bits

xxF Request Flag, auto reset in ISR

LegendxxF Request Flag, no auto reset in ISR

EMI

1CH

EMI

20H

M. Funct. 0 MF0F MF0E

Time Base 1 TB1F TB1E

18HEMI

10H

LVD LVF LVE M. Funct. 2 MF2F MF2E

EEPROM DEF DEE

STM P STMPF STMPE

STM A STMAF STMAE

OCVP OCVPF OCVPE EMI

24H

14HEMIM. Funct. 1 MF1F MF1EPTM P PTMPF PTMPE

PTM A PTMAF PTMAE

Interrupt Structure

External InterruptsTheexternal interruptsarecontrolledbysignal transitionsonthepinsINT0~INT1.Anexternalinterruptrequestwill takeplacewhentheexternalinterruptrequestflags,INT0F~INT1F,areset,whichwilloccurwhenatransition,whosetypeischosenbytheedgeselectbits,appearsontheexternalinterruptpins.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,andrespectiveexternalinterruptenablebit,INT0E~INT1E,mustfirstbeset.AdditionallythecorrectinterruptedgetypemustbeselectedusingtheINTEGregistertoenabletheexternalinterruptfunctionandtochoosethetriggeredgetype.Astheexternalinterruptpinsarepin-sharedwithI/Opins, theycanonlybeconfiguredasexternal interruptpins if theirexternalinterruptenablebitinthecorrespondinginterruptregisterhasbeenset.Thepinmustalsobesetupasaninputbysettingthecorrespondingbitintheportcontrolregisteraswellastherelevantpin-sharedfunctionselectionbits.Whentheinterruptisenabled,thestackisnotfullandthecorrecttransitiontypeappearsontheexternalinterruptpin,asubroutinecalltotheexternalinterruptvector,will takeplace.Whentheinterruptisserviced,theexternalinterruptrequestflags,INT0F~INT1F,willbeautomaticallyresetandtheEMIbitwillbeautomaticallyclearedtodisableotherinterrupts.Notethatanypull-highresistorselectionsontheexternalinterruptpinswillremainvalidevenifthepinisusedasanexternalinterruptinput.

TheINTEGregisterisusedtoselectthetypeofactiveedgethatwilltriggertheexternalinterrupt.Achoiceofeitherrisingorfallingorbothedgetypescanbechosentotriggeranexternalinterrupt.NotethattheINTEGregistercanalsobeusedtodisabletheexternalinterruptfunction.




OCVP InterruptAnOCVPinterruptrequestwill takeplacewhentheOCVPInterruptrequestflag,OCVPF,isset,whichoccurswhentheOCVPcircuitdetectsaspecificcurrentorvoltagecondition.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress, theglobal interruptenablebit,EMI,andtheOCVPInterruptenablebit,OCVPE,mustfirstbeset.Whentheinterruptisenabled, thestack isnotfullandauser-definedcurrentorvoltageconditionoccurs,asubroutinecall to theOCVPInterruptvector,willtakeplace.WhentheOCVPInterruptisserviced,theEMIbitwillbeautomaticallyclearedtodisableotherinterruptsandtheOCVPinterruptrequestflagwillbealsoautomaticallycleared.

Multi-function InterruptsWithinthedevicetherearethreeMulti-functioninterrupts.Unliketheotherindependentinterrupts,these interruptshavenoindependentsource,butratherareformedfromotherexistinginterruptsources,namelytheTMInterrupts,LVDInterruptandEEPROMInterrupt.

AMulti-functioninterruptrequestwilltakeplacewhenanyoftheMulti-functioninterruptrequestflags,MFnFareset.TheMulti-function interrupt flagswillbesetwhenanyof their includedfunctionsgenerateaninterruptrequestflag.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,whentheMulti-functioninterruptisenabledandthestackisnotfull,andeitheroneoftheinterruptscontainedwithineachofMulti-functioninterruptoccurs,asubroutinecalltooneoftheMulti-functioninterruptvectorswilltakeplace.Whentheinterruptisserviced,therelatedMulti-Functionrequestflag,willbeautomaticallyresetandtheEMIbitwillbeautomaticallyclearedtodisableotherinterrupts.

However, itmustbenotedthat,althoughtheMulti-functionInterruptflagswillbeautomaticallyresetwhen the interrupt is serviced, the request flags from theoriginal sourceof theMulti-functioninterrupts,namelytheTMInterrupts,LVDInterrupt andEEPROMInterruptwillnotbeautomaticallyresetandmustbemanuallyresetbytheapplicationprogram.

Time Base InterruptsThefunctionoftheTimeBaseinterruptsistoprovideregulartimesignalintheformofaninternalinterrupt.Theyarecontrolledbytheoverflowsignalsfromtheirrespectivetimerfunctions.Whenthesehappens their respective interrupt request flags,TB0ForTB1Fwillbeset.Toallowtheprogramtobranchtotheirrespectiveinterruptvectoraddresses,theglobalinterruptenablebit,EMIandTimeBaseenablebits,TB0EorTB1E,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandtheTimeBaseoverflows,asubroutinecall totheirrespectivevectorlocationswilltakeplace.Whentheinterruptisserviced,therespectiveinterruptrequestflag,TB0ForTB1F,willbeautomaticallyresetandtheEMIbitwillbeclearedtodisableotherinterrupts.

ThepurposeoftheTimeBaseInterruptistoprovideaninterruptsignalatfixedtimeperiods.TheirclocksourcesoriginatefromtheinternalclocksourcefTB.ThisfTB inputclockpasses throughadivider, thedivisionratioofwhich isselectedbyprogrammingtheappropriatebits in theTBCregistertoobtainlongerinterruptperiodswhosevalueranges.TheclocksourcethatgeneratesfTB,whichinturncontrolstheTimeBaseinterruptperiod,canoriginatefromseveraldifferentsourceswhichisselectedusingtheTBCKbitintheTBCregister.




TBC RegisterBit 7 6 5 4 3 2 1 0

Name TBON TBCK TB11 TB10 — TB02 TB01 TB00R/W R/W R/W R/W R/W — R/W R/W R/WPOR 0 0 1 1 — 1 1 1

Bit7 TBON:TB0andTB1Controlbit0:Disable1:Enable

Bit6 TBCK:SelectfTBClockSource0:fTBC1:fSYS/4

Bit5~4 TB11 ~ TB10:SelectTimeBase1Time-outPeriod00:212/fTB

01:213/fTB

10:214/fTB

11:215/fTB

Bit3 Unimplemented,readas"0"Bit2~0 TB02 ~ TB00:SelectTimeBase0Time-outPeriod

000:28/fTB

001:29/fTB

010:210/fTB

011:211/fTB

100:212/fTB

101:213/fTB

110:214/fTB

111:215/fTB

Time Base 1 InterruptLIRC

MUX

fSYS/4

fTBCfTB

÷212~215

TB11~TB10

TBCK bit

Time Base 0 Interrupt÷28~215

TB02~TB00

Time Base Interrupt




EEPROM InterruptTheEEPROMinterrupt iscontainedwithintheMulti-functionInterrupt.AnEEPROMInterruptrequestwill takeplacewhen theEEPROMInterrupt request flag,DEF, is set,whichoccurswhenanEEPROMWritecycleends.Toallowtheprogramtobranchto itsrespectiveinterruptvectoraddress, theglobal interruptenablebit,EMI,andEEPROMInterruptenablebit,DEE,andassociatedMulti-functioninterruptenablebit,MF2E,mustfirstbeset.Whentheinterrupt isenabled,thestackisnotfullandanEEPROMWritecycleends,asubroutinecalltotherespectiveEEPROMInterruptvector,will takeplace.WhentheEEPROMInterruptisserviced,theEMIbitwillbeautomaticallyclearedtodisableotherinterrupts,howeveronlytheMulti-functioninterruptrequestflagwillbealsoautomaticallycleared.AstheDEFflagwillnotbeautomaticallycleared,ithastobeclearedbytheapplicationprogram.

LVD InterruptTheLVDinterruptiscontainedwithintheMulti-functionInterrupt.AnLVDInterruptrequestwilltakeplacewhentheLVDInterruptrequestflag,LVF,isset,whichoccurswhentheLowVoltageDetector functiondetectsa lowpower supplyvoltage.Toallow theprogram tobranch to itsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,andLowVoltageInterruptenablebit,LVE,andassociatedMulti-functioninterruptenablebit,MF2E,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandalowvoltageconditionoccurs,asubroutinecalltotheLVDInterruptvector,willtakeplace.WhentheLowVoltageInterruptisserviced,theEMIbitwillbeautomaticallyclearedtodisableotherinterrupts,howeveronlytheMulti-functioninterruptrequestflagwillbealsoautomaticallycleared.AstheLVDinterruptrequestflag,LVF,willnotbeautomaticallycleared,ithastobeclearedbytheapplicationprogram.

TM InterruptsTheStandardandPeriodicTypeTMseachhave two interrupts.Allof theTMinterruptsarecontainedwithintheMulti-functionInterrupts.ForthedifferentTypeTMstherearetwointerruptrequestflagsxTMPFandxTMAFandtwoenablebitsxTMPEandxTMAE.ATMinterruptrequestwill takeplacewhenanyof theTMrequest flagsareset,asituationwhichoccurswhenaTMcomparatorPorcomparatorAmatchsituationhappens.

Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,andtherespectiveTMInterruptenablebit,andassociatedMulti-functioninterruptenablebit,MFnF,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandaTMcomparatormatchsituationoccurs,asubroutinecall to therelevantTMInterruptvector locations,will takeplace.WhentheTMinterruptisserviced,theEMIbitwillbeautomaticallyclearedtodisableotherinterrupts,howeveronlytherelatedMFnFflagwillbeautomaticallycleared.AstheTMinterruptrequestflagswillnotbeautomaticallycleared,theyhavetobeclearedbytheapplicationprogram.




Interrupt Wake-up FunctionEachof the interruptfunctionshas thecapabilityofwakingupthemicrocontrollerwhenin theSLEEPorIDLEMode.Awake-upisgeneratedwhenaninterruptrequestflagchangesfromlowtohighandisindependentofwhethertheinterruptisenabledornot.Therefore,eventhoughthedeviceisintheSLEEPorIDLEModeanditssystemoscillatorstopped,situationssuchasexternaledgetransitionsontheexternalinterruptpinsoralowpowersupplyvoltagemaycausetheirrespectiveinterruptflagtobesethighandconsequentlygenerateaninterrupt.Caremustthereforebetakenifspuriouswake-upsituationsaretobeavoided.Ifaninterruptwake-upfunctionistobedisabledthenthecorrespondinginterruptrequestflagshouldbesethighbeforethedeviceenterstheSLEEPorIDLEMode.Theinterruptenablebitshavenoeffectontheinterruptwake-upfunction.

Programming ConsiderationsBydisablingtherelevantinterruptenablebits,arequestedinterruptcanbepreventedfrombeingserviced,however,oncean interrupt request flag is set, itwill remain in thiscondition in theinterruptregisteruntilthecorrespondinginterruptisservicedoruntiltherequestflagisclearedbytheapplicationprogram.

Whereacertain interrupt iscontainedwithinaMulti-function interrupt, thenwhenthe interruptserviceroutineisexecuted,asonlytheMulti-functioninterruptrequestflags,MF0F~MF2F,willbeautomaticallycleared, the individualrequestflagfor thefunctionneeds tobeclearedbytheapplicationprogram.

It isrecommendedthatprogramsdonotusethe"CALL"instructionwithintheinterruptservicesubroutine.Interruptsoftenoccurinanunpredictablemannerorneedtobeservicedimmediately.Ifonlyonestackisleftandtheinterruptisnotwellcontrolled,theoriginalcontrolsequencewillbedamagedonceaCALLsubroutineisexecutedintheinterruptsubroutine.

Everyinterrupthasthecapabilityofwakingupthemicrocontrollerwhenit isinSLEEPorIDLEMode,thewakeupbeinggeneratedwhentheinterruptrequestflagchangesfromlowtohigh.IfitisrequiredtopreventacertaininterruptfromwakingupthemicrocontrollerthenitsrespectiverequestflagshouldbefirstsethighbeforeenterSLEEPorIDLEMode.

AsonlytheProgramCounter ispushedontothestack, thenwhentheinterrupt isserviced, if thecontentsof theaccumulator,statusregisterorotherregistersarealteredbythe interruptserviceprogram,theircontentsshouldbesavedto thememoryat thebeginningof the interruptserviceroutine.

Toreturnfromaninterruptsubroutine,eitheraRETorRETIinstructionmaybeexecuted.TheRETIinstructioninadditiontoexecutingareturntothemainprogramalsoautomaticallysetstheEMIbithightoallowfurtherinterrupts.TheRETinstructionhoweveronlyexecutesareturntothemainprogramleavingtheEMIbitinitspresentzerostateandthereforedisablingtheexecutionoffurtherinterrupts.




Low Voltage Detector – LVDThedevicehasaLowVoltageDetectorfunction,alsoknownasLVD.Thisenablesthedevicetomonitorthepowersupplyvoltage,VDD,andprovidesawarningsignalshoulditfallbelowacertainlevel.Thisfunctionmaybeespeciallyusefulinbatteryapplicationswherethesupplyvoltagewillgraduallyreduceasthebatteryages,asitallowsanearlywarningbatterylowsignaltobegenerated.TheLowVoltageDetectoralsohasthecapabilityofgeneratinganinterruptsignal.

LVD RegisterTheLowVoltageDetectorfunctioniscontrolledusingasingleregisterwiththenameLVDC.Threebits inthisregister,VLVD2~VLVD0,areusedtoselectoneofeightfixedvoltagesbelowwhichalowvoltageconditionwillbedetermined.AlowvoltageconditionisindicatedwhentheLVDObitisset.IftheLVDObitislow,thisindicatesthattheVDDvoltageisabovethepresetlowvoltagevalue.TheLVDENbit isusedtocontrol theoverallon/offfunctionof thelowvoltagedetector.Settingthebithighwillenablethelowvoltagedetector.Clearingthebittozerowillswitchofftheinternallowvoltagedetectorcircuits.Asthelowvoltagedetectorwillconsumeacertainamountofpower,itmaybedesirabletoswitchoffthecircuitwhennotinuse,animportantconsiderationinpowersensitivebatterypoweredapplications.

LVDC Register Bit 7 6 5 4 3 2 1 0

Name — — LVDO LVDEN — VLVD2 VLVD1 VLVD0R/W — — R R/W — R/W R/W R/WPOR — — 0 0 — 0 0 0

Bit7~6 Unimplemented,readas"0"Bit5 LVDO:LVDOutputFlag

0:NoLowVoltageDetected1:LowVoltageDetected

Bit4 LVDEN:LowVoltageDetectorControl0:Disable1:Enable

Bit3 Unimplemented,readas"0"Bit2~0 VLVD2 ~ VLVD0:SelectLVDVoltage

000:2.0V001:2.2V010:2.4V011:2.7V100:3.0V101:3.3V110:3.6V111:4.0V




LVD OperationTheLowVoltageDetectorfunctionoperatesbycomparingthepowersupplyvoltage,VDD,withapre-specifiedvoltagelevelstoredintheLVDCregister.Thishasarangeofbetween2.0Vand4.0V.Whenthepowersupplyvoltage,VDD,fallsbelowthispre-determinedvalue,theLVDObitwillbesethighindicatinga lowpowersupplyvoltagecondition.TheLowVoltageDetectorfunctionissuppliedbyareferencevoltagewhichwillbeautomaticallyenabled.AfterenablingtheLowVoltageDetector,atimedelaytLVDSshouldbeallowedforthecircuitrytostabilisebeforereadingtheLVDObit.NotealsothatastheVDDvoltagemayriseandfallratherslowly,at thevoltagenearsthatofVLVD,theremaybemultiplebitLVDOtransitions.

VDD

LVDEN

LVDO

VLVD

tLVDS

LVD Operation

TheLowVoltageDetectoralsohasitsowninterruptwhichiscontainedwithinoneof themulti-functioninterrupts,providinganalternativemeansoflowvoltagedetection,inadditiontopollingtheLVDObit.TheinterruptwillonlybegeneratedafteradelayoftLVDaftertheLVDObithasbeensethighbyalowvoltagecondition.Inthiscase,theLVFinterruptrequestflagwillbeset,causinganinterrupttobegeneratedifVDDfallsbelowthepresetLVDvoltage.Thiswillcausethedevicetowake-upfromtheSLEEPorIDLEMode,howeveriftheLowVoltageDetectorwakeupfunctionisnotrequiredthentheLVFflagshouldbefirstsethighbeforethedeviceenterstheSLEEPorIDLEMode.

Configuration OptionsConfigurationoptionsrefertocertainoptionswithintheMCUthatareprogrammedintothedeviceduringtheprogrammingprocess.Duringthedevelopmentprocess,theseoptionsareselectedusingtheHT-IDEsoftwaredevelopment tools.Astheseoptionsareprogrammedintothedeviceusingthehardwareprogrammingtools,once theyareselectedtheycannotbechangedlaterusingtheapplicationprogram.Alloptionsmustbedefinedforpropersystemfunction,thedetailsofwhichareshowninthetable.

No. OptionsWatchdog Timer Option

1Watchdog Timer Enable/disable Selection: Controlled by WDTC registerAlways enabled




Application Circuits

VDD PTP/PA1

OCVPCI/INT1/STCK/PA5


PA0/ICPDA

PA2/ICPCK

HT45F3820_8SOP

3

4

7

8

1

6

5

2VSS

3

1

2

OCVP0AI0/STP/PA4/VREF

21

CON1

24VIN

+24V

VIN

GND Vout

+24V +5V

C610μF/50V

C8104

1 3

2

U2 7805

C9104

C710μF/10V

+ +

GNDGND

C3104

C210μF/10V

+

+5V

U1

+24V

C4104

C5104

R1

20KΩ

R2

20KΩ

R31Ω

C1

104/400VNebuliser

L14.7μH

U3




Instruction Set

IntroductionCentral to thesuccessfuloperationofanymicrocontroller is its instructionset,whichisasetofprograminstructioncodesthatdirectsthemicrocontrollertoperformcertainoperations.InthecaseofHoltekmicrocontroller,acomprehensiveandflexiblesetofover60instructionsisprovidedtoenableprogrammerstoimplementtheirapplicationwiththeminimumofprogrammingoverheads.

Foreasierunderstandingofthevariousinstructioncodes, theyhavebeensubdividedintoseveralfunctionalgroupings.

Instruction TimingMostinstructionsareimplementedwithinoneinstructioncycle.Theexceptionstothisarebranch,call,or tablereadinstructionswheretwoinstructioncyclesarerequired.Oneinstructioncycleisequalto4systemclockcycles,thereforeinthecaseofan8MHzsystemoscillator,mostinstructionswouldbeimplementedwithin0.5μsandbranchorcall instructionswouldbeimplementedwithin1μs.Although instructionswhichrequireonemorecycle to implementaregenerally limited totheJMP,CALL,RET,RETIandtablereadinstructions, it is important torealize thatanyotherinstructionswhichinvolvemanipulationoftheProgramCounterLowregisterorPCLwillalsotakeonemorecycletoimplement.AsinstructionswhichchangethecontentsofthePCLwill implyadirect jumptothatnewaddress,onemorecyclewillberequired.Examplesofsuchinstructionswouldbe"CLRPCL"or"MOVPCL,A".Forthecaseofskipinstructions,itmustbenotedthatiftheresultofthecomparisoninvolvesaskipoperationthenthiswillalsotakeonemorecycle,ifnoskipisinvolvedthenonlyonecycleisrequired.

Moving and Transferring DataThe transferofdatawithin themicrocontrollerprogram isoneof themost frequentlyusedoperations.MakinguseofthreekindsofMOVinstructions,datacanbetransferredfromregisterstotheAccumulatorandvice-versaaswellasbeingabletomovespecificimmediatedatadirectlyintotheAccumulator.Oneofthemostimportantdatatransferapplicationsis toreceivedatafromtheinputportsandtransferdatatotheoutputports.

Arithmetic OperationsTheabilitytoperformcertainarithmeticoperationsanddatamanipulationisanecessaryfeatureofmostmicrocontrollerapplications.WithintheHoltekmicrocontrollerinstructionsetarearangeofaddandsubtract instructionmnemonicstoenablethenecessaryarithmetictobecarriedout.Caremustbe taken toensurecorrecthandlingofcarryandborrowdatawhenresultsexceed255foradditionandlessthan0forsubtraction.TheincrementanddecrementinstructionsINC,INCA,DECandDECAprovideasimplemeansofincreasingordecreasingbyavalueofoneofthevaluesinthedestinationspecified.




Logical and Rotate OperationThestandardlogicaloperationssuchasAND,OR,XORandCPLallhavetheirowninstructionwithintheHoltekmicrocontroller instructionset.Aswiththecaseofmost instructionsinvolvingdatamanipulation, datamust pass through theAccumulatorwhichmay involve additionalprogrammingsteps. Inall logicaldataoperations, thezero flagmaybeset if the resultof theoperationiszero.AnotherformoflogicaldatamanipulationcomesfromtherotateinstructionssuchasRR,RL,RRCandRLCwhichprovideasimplemeansofrotatingonebitrightorleft.Differentrotateinstructionsexistdependingonprogramrequirements.Rotateinstructionsareusefulforserialportprogrammingapplicationswheredatacanberotatedfromaninternalregister intotheCarrybitfromwhereitcanbeexaminedandthenecessaryserialbitsethighorlow.Anotherapplicationwhichrotatedataoperationsareusedistoimplementmultiplicationanddivisioncalculations.

Branches and Control TransferProgrambranchingtakestheformofeitherjumpstospecifiedlocationsusingtheJMPinstructionor toa subroutineusing theCALL instruction.Theydiffer in the sense that in thecaseofasubroutinecall, theprogrammustreturn to the instruction immediatelywhenthesubroutinehasbeencarriedout.Thisisdonebyplacingareturninstruction"RET"inthesubroutinewhichwillcausetheprogramtojumpbacktotheaddressrightaftertheCALLinstruction.InthecaseofaJMPinstruction,theprogramsimplyjumpstothedesiredlocation.ThereisnorequirementtojumpbacktotheoriginaljumpingoffpointasinthecaseoftheCALLinstruction.Onespecialandextremelyusefulsetofbranchinstructionsaretheconditionalbranches.Hereadecisionisfirstmaderegardingtheconditionofacertaindatamemoryor individualbits.Dependingupon theconditions, theprogramwillcontinuewiththenextinstructionorskipoveritandjumptothefollowinginstruction.These instructionsare thekey todecisionmakingandbranchingwithin theprogramperhapsdeterminedbytheconditionofcertaininputswitchesorbytheconditionofinternaldatabits.

Bit OperationsTheabilitytoprovidesinglebitoperationsonDataMemoryisanextremelyflexiblefeatureofallHoltekmicrocontrollers.Thisfeature isespeciallyusefulforoutputportbitprogrammingwhereindividualbitsorportpinscanbedirectlysethighorlowusingeitherthe"SET[m].i"or"CLR[m].i" instructionsrespectively.Thefeatureremovestheneedforprogrammers tofirstreadthe8-bitoutputport,manipulatetheinputdatatoensurethatotherbitsarenotchangedandthenoutputtheportwiththecorrectnewdata.Thisread-modify-writeprocessistakencareofautomaticallywhenthesebitoperationinstructionsareused.

Table Read OperationsDatastorage isnormally implementedbyusing registers.However,whenworkingwith largeamountsoffixeddata, thevolumeinvolvedoftenmakesit inconvenienttostorethefixeddataintheDataMemory.Toovercomethisproblem,HoltekmicrocontrollersallowanareaofProgramMemory tobesetasa tablewheredatacanbedirectlystored.Asetofeasy touse instructionsprovides themeansbywhich this fixeddatacanbereferencedandretrievedfromtheProgramMemory.

Other OperationsInaddition to theabovefunctional instructions,a rangeofother instructionsalsoexistsuchasthe"HALT"instructionforPower-downoperationsand instructions tocontrol theoperationoftheWatchdogTimerfor reliableprogramoperationsunderextremeelectricorelectromagneticenvironments.Fortheirrelevantoperations,refertothefunctionalrelatedsections.




Instruction Set SummaryThefollowingtabledepictsasummaryoftheinstructionsetcategorisedaccordingtofunctionandcanbeconsultedasabasicinstructionreferenceusingthefollowinglistedconventions.

Table Conventionsx:Bitsimmediatedatam:DataMemoryaddressA:Accumulatori:0~7numberofbitsaddr:Programmemoryaddress

Mnemonic Description Cycles Flag AffectedArithmeticADD A,[m] Add Data Memory to ACC 1 Z, C, AC, OVADDM A,[m] Add ACC to Data Memory 1Note Z, C, AC, OVADD A,x Add immediate data to ACC 1 Z, C, AC, OVADC A,[m] Add Data Memory to ACC with Carry 1 Z, C, AC, OVADCM A,[m] Add ACC to Data memory with Carry 1Note Z, C, AC, OVSUB A,x Subtract immediate data from the ACC 1 Z, C, AC, OVSUB A,[m] Subtract Data Memory from ACC 1 Z, C, AC, OVSUBM A,[m] Subtract Data Memory from ACC with result in Data Memory 1Note Z, C, AC, OVSBC A,[m] Subtract Data Memory from ACC with Carry 1 Z, C, AC, OVSBCM A,[m] Subtract Data Memory from ACC with Carry, result in Data Memory 1Note Z, C, AC, OVDAA [m] Decimal adjust ACC for Addition with result in Data Memory 1Note CLogic OperationAND A,[m] Logical AND Data Memory to ACC 1 ZOR A,[m] Logical OR Data Memory to ACC 1 ZXOR A,[m] Logical XOR Data Memory to ACC 1 ZANDM A,[m] Logical AND ACC to Data Memory 1Note ZORM A,[m] Logical OR ACC to Data Memory 1Note ZXORM A,[m] Logical XOR ACC to Data Memory 1Note ZAND A,x Logical AND immediate Data to ACC 1 ZOR A,x Logical OR immediate Data to ACC 1 ZXOR A,x Logical XOR immediate Data to ACC 1 ZCPL [m] Complement Data Memory 1Note ZCPLA [m] Complement Data Memory with result in ACC 1 ZIncrement & DecrementINCA [m] Increment Data Memory with result in ACC 1 ZINC [m] Increment Data Memory 1Note ZDECA [m] Decrement Data Memory with result in ACC 1 ZDEC [m] Decrement Data Memory 1Note ZRotateRRA [m] Rotate Data Memory right with result in ACC 1 NoneRR [m] Rotate Data Memory right 1Note NoneRRCA [m] Rotate Data Memory right through Carry with result in ACC 1 CRRC [m] Rotate Data Memory right through Carry 1Note CRLA [m] Rotate Data Memory left with result in ACC 1 NoneRL [m] Rotate Data Memory left 1Note NoneRLCA [m] Rotate Data Memory left through Carry with result in ACC 1 CRLC [m] Rotate Data Memory left through Carry 1Note C




Mnemonic Description Cycles Flag AffectedData MoveMOV A,[m] Move Data Memory to ACC 1 NoneMOV [m],A Move ACC to Data Memory 1Note NoneMOV A,x Move immediate data to ACC 1 NoneBit OperationCLR [m].i Clear bit of Data Memory 1Note NoneSET [m].i Set bit of Data Memory 1Note NoneBranch OperationJMP addr Jump unconditionally 2 NoneSZ [m] Skip if Data Memory is zero 1Note NoneSZA [m] Skip if Data Memory is zero with data movement to ACC 1Note NoneSZ [m].i Skip if bit i of Data Memory is zero 1Note NoneSNZ [m].i Skip if bit i of Data Memory is not zero 1Note NoneSIZ [m] Skip if increment Data Memory is zero 1Note NoneSDZ [m] Skip if decrement Data Memory is zero 1Note NoneSIZA [m] Skip if increment Data Memory is zero with result in ACC 1Note NoneSDZA [m] Skip if decrement Data Memory is zero with result in ACC 1Note NoneCALL addr Subroutine call 2 NoneRET Return from subroutine 2 NoneRET A,x Return from subroutine and load immediate data to ACC 2 NoneRETI Return from interrupt 2 NoneTable Read OperationTABRD [m] Read table (specific page) to TBLH and Data Memory 2Note NoneTABRDC [m] Read table (current page) to TBLH and Data Memory 2Note NoneTABRDL [m] Read table (last page) to TBLH and Data Memory 2Note NoneMiscellaneousNOP No operation 1 NoneCLR [m] Clear Data Memory 1Note NoneSET [m] Set Data Memory 1Note NoneCLR WDT Clear Watchdog Timer 1 TO, PDFCLR WDT1 Pre-clear Watchdog Timer 1 TO, PDFCLR WDT2 Pre-clear Watchdog Timer 1 TO, PDFSWAP [m] Swap nibbles of Data Memory 1Note NoneSWAPA [m] Swap nibbles of Data Memory with result in ACC 1 NoneHALT Enter power down mode 1 TO, PDF

Note:1.Forskipinstructions,iftheresultofthecomparisoninvolvesaskipthentwocyclesarerequired,ifnoskiptakesplaceonlyonecycleisrequired.

2.AnyinstructionwhichchangesthecontentsofthePCLwillalsorequire2cyclesforexecution.3.For the“CLRWDT1”and“CLRWDT2”instructionstheTOandPDFflagsmaybeaffectedbytheexecution status.TheTOandPDFflagsareclearedafterboth“CLRWDT1”and“CLRWDT2”instructionsareconsecutivelyexecuted.OtherwisetheTOandPDFflagsremainunchanged.




Instruction Definition

ADC A,[m] AddDataMemorytoACCwithCarryDescription ThecontentsofthespecifiedDataMemory,Accumulatorandthecarryflagareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+[m]+CAffectedflag(s) OV,Z,AC,C

ADCM A,[m] AddACCtoDataMemorywithCarryDescription ThecontentsofthespecifiedDataMemory,Accumulatorandthecarryflagareadded. TheresultisstoredinthespecifiedDataMemory.Operation [m]←ACC+[m]+CAffectedflag(s) OV,Z,AC,C

ADD A,[m] AddDataMemorytoACCDescription ThecontentsofthespecifiedDataMemoryandtheAccumulatorareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+[m]Affectedflag(s) OV,Z,AC,C

ADD A,x AddimmediatedatatoACCDescription ThecontentsoftheAccumulatorandthespecifiedimmediatedataareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+xAffectedflag(s) OV,Z,AC,C

ADDM A,[m] AddACCtoDataMemoryDescription ThecontentsofthespecifiedDataMemoryandtheAccumulatorareadded. TheresultisstoredinthespecifiedDataMemory.Operation [m]←ACC+[m]Affectedflag(s) OV,Z,AC,C

AND A,[m] LogicalANDDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalAND operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″AND″[m]Affectedflag(s) Z

AND A,x LogicalANDimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalAND operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″AND″xAffectedflag(s) Z

ANDM A,[m] LogicalANDACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalAND operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″AND″[m]Affectedflag(s) Z




CALL addr SubroutinecallDescription Unconditionallycallsasubroutineatthespecifiedaddress.TheProgramCounterthen incrementsby1toobtaintheaddressofthenextinstructionwhichisthenpushedontothe stack.Thespecifiedaddressisthenloadedandtheprogramcontinuesexecutionfromthis newaddress.Asthisinstructionrequiresanadditionaloperation,itisatwocycleinstruction.Operation Stack←ProgramCounter+1 ProgramCounter←addrAffectedflag(s) None

CLR [m] ClearDataMemoryDescription EachbitofthespecifiedDataMemoryisclearedto0.Operation [m]←00HAffectedflag(s) None

CLR [m].i ClearbitofDataMemoryDescription BitiofthespecifiedDataMemoryisclearedto0.Operation [m].i←0Affectedflag(s) None

CLR WDT ClearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF

CLR WDT1 Pre-clearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Notethatthisinstructionworksin conjunctionwithCLRWDT2andmustbeexecutedalternatelywithCLRWDT2tohave effect.RepetitivelyexecutingthisinstructionwithoutalternatelyexecutingCLRWDT2will havenoeffect.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF

CLR WDT2 Pre-clearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Notethatthisinstructionworksinconjunction withCLRWDT1andmustbeexecutedalternatelywithCLRWDT1tohaveeffect. RepetitivelyexecutingthisinstructionwithoutalternatelyexecutingCLRWDT1willhaveno effect.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF

CPL [m] ComplementDataMemoryDescription EachbitofthespecifiedDataMemoryislogicallycomplemented(1′scomplement).Bitswhich previouslycontaineda1arechangedto0andviceversa.Operation [m]←[m]Affectedflag(s) Z




CPLA [m] ComplementDataMemorywithresultinACCDescription EachbitofthespecifiedDataMemoryislogicallycomplemented(1′scomplement).Bitswhich previouslycontaineda1arechangedto0andviceversa.Thecomplementedresultisstoredin theAccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]Affectedflag(s) Z

DAA [m] Decimal-AdjustACCforadditionwithresultinDataMemoryDescription ConvertthecontentsoftheAccumulatorvaluetoaBCD(BinaryCodedDecimal)value resultingfromthepreviousadditionoftwoBCDvariables.Ifthelownibbleisgreaterthan9 orifACflagisset,thenavalueof6willbeaddedtothelownibble.Otherwisethelownibble remainsunchanged.Ifthehighnibbleisgreaterthan9oriftheCflagisset,thenavalueof6 willbeaddedtothehighnibble.Essentially,thedecimalconversionisperformedbyadding 00H,06H,60Hor66HdependingontheAccumulatorandflagconditions.OnlytheCflag maybeaffectedbythisinstructionwhichindicatesthatiftheoriginalBCDsumisgreaterthan 100,itallowsmultipleprecisiondecimaladdition.Operation [m]←ACC+00Hor [m]←ACC+06Hor [m]←ACC+60Hor [m]←ACC+66HAffectedflag(s) C

DEC [m] DecrementDataMemoryDescription DatainthespecifiedDataMemoryisdecrementedby1.Operation [m]←[m]−1Affectedflag(s) Z

DECA [m] DecrementDataMemorywithresultinACCDescription DatainthespecifiedDataMemoryisdecrementedby1.Theresultisstoredinthe Accumulator.ThecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]−1Affectedflag(s) Z

HALT EnterpowerdownmodeDescription Thisinstructionstopstheprogramexecutionandturnsoffthesystemclock.Thecontentsof theDataMemoryandregistersareretained.TheWDTandprescalerarecleared.Thepower downflagPDFissetandtheWDTtime-outflagTOiscleared.Operation TO←0 PDF←1Affectedflag(s) TO,PDF

INC [m] IncrementDataMemoryDescription DatainthespecifiedDataMemoryisincrementedby1.Operation [m]←[m]+1Affectedflag(s) Z

INCA [m] IncrementDataMemorywithresultinACCDescription DatainthespecifiedDataMemoryisincrementedby1.TheresultisstoredintheAccumulator. ThecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]+1Affectedflag(s) Z




JMP addr JumpunconditionallyDescription ThecontentsoftheProgramCounterarereplacedwiththespecifiedaddress.Program executionthencontinuesfromthisnewaddress.Asthisrequirestheinsertionofadummy instructionwhilethenewaddressisloaded,itisatwocycleinstruction.Operation ProgramCounter←addrAffectedflag(s) None

MOV A,[m] MoveDataMemorytoACCDescription ThecontentsofthespecifiedDataMemoryarecopiedtotheAccumulator.Operation ACC←[m]Affectedflag(s) None

MOV A,x MoveimmediatedatatoACCDescription TheimmediatedataspecifiedisloadedintotheAccumulator.Operation ACC←xAffectedflag(s) None

MOV [m],A MoveACCtoDataMemoryDescription ThecontentsoftheAccumulatorarecopiedtothespecifiedDataMemory.Operation [m]←ACCAffectedflag(s) None

NOP NooperationDescription Nooperationisperformed.Executioncontinueswiththenextinstruction.Operation NooperationAffectedflag(s) None

OR A,[m] LogicalORDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwise logicalORoperation.TheresultisstoredintheAccumulator.Operation ACC←ACC″OR″[m]Affectedflag(s) Z

OR A,x LogicalORimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″OR″xAffectedflag(s) Z

ORM A,[m] LogicalORACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalOR operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″OR″[m]Affectedflag(s) Z

RET ReturnfromsubroutineDescription TheProgramCounterisrestoredfromthestack.Programexecutioncontinuesattherestored address.Operation ProgramCounter←StackAffectedflag(s) None




RET A,x ReturnfromsubroutineandloadimmediatedatatoACCDescription TheProgramCounterisrestoredfromthestackandtheAccumulatorloadedwiththespecified immediatedata.Programexecutioncontinuesattherestoredaddress.Operation ProgramCounter←Stack ACC←xAffectedflag(s) None

RETI ReturnfrominterruptDescription TheProgramCounterisrestoredfromthestackandtheinterruptsarere-enabledbysettingthe EMIbit.EMIisthemasterinterruptglobalenablebit.Ifaninterruptwaspendingwhenthe RETIinstructionisexecuted,thependingInterruptroutinewillbeprocessedbeforereturning tothemainprogram.Operation ProgramCounter←Stack EMI←1Affectedflag(s) None

RL [m] RotateDataMemoryleftDescription ThecontentsofthespecifiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0.Operation [m].(i+1)←[m].i;(i=0~6) [m].0←[m].7Affectedflag(s) None

RLA [m] RotateDataMemoryleftwithresultinACCDescription ThecontentsofthespecifiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0. TherotatedresultisstoredintheAccumulatorandthecontentsoftheDataMemoryremain unchanged.Operation ACC.(i+1)←[m].i;(i=0~6) ACC.0←[m].7Affectedflag(s) None

RLC [m] RotateDataMemoryleftthroughCarryDescription ThecontentsofthespecifiedDataMemoryandthecarryflagarerotatedleftby1bit.Bit7 replacestheCarrybitandtheoriginalcarryflagisrotatedintobit0.Operation [m].(i+1)←[m].i;(i=0~6) [m].0←C C←[m].7Affectedflag(s) C

RLCA [m] RotateDataMemoryleftthroughCarrywithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedleftby1bit.Bit7replacesthe Carrybitandtheoriginalcarryflagisrotatedintothebit0.Therotatedresultisstoredinthe AccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC.(i+1)←[m].i;(i=0~6) ACC.0←C C←[m].7Affectedflag(s) C

RR [m] RotateDataMemoryrightDescription ThecontentsofthespecifiedDataMemoryarerotatedrightby1bitwithbit0rotatedintobit7.Operation [m].i←[m].(i+1);(i=0~6) [m].7←[m].0Affectedflag(s) None




RRA [m] RotateDataMemoryrightwithresultinACCDescription DatainthespecifiedDataMemoryisrotatedrightby1bitwithbit0rotatedintobit7. TherotatedresultisstoredintheAccumulatorandthecontentsoftheDataMemoryremain unchanged.Operation ACC.i←[m].(i+1);(i=0~6) ACC.7←[m].0Affectedflag(s) None

RRC [m] RotateDataMemoryrightthroughCarryDescription ThecontentsofthespecifiedDataMemoryandthecarryflagarerotatedrightby1bit.Bit0 replacestheCarrybitandtheoriginalcarryflagisrotatedintobit7.Operation [m].i←[m].(i+1);(i=0~6) [m].7←C C←[m].0Affectedflag(s) C

RRCA [m] RotateDataMemoryrightthroughCarrywithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedrightby1bit.Bit0replaces theCarrybitandtheoriginalcarryflagisrotatedintobit7.Therotatedresultisstoredinthe AccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC.i←[m].(i+1);(i=0~6) ACC.7←C C←[m].0Affectedflag(s) C

SBC A,[m] SubtractDataMemoryfromACCwithCarryDescription ThecontentsofthespecifiedDataMemoryandthecomplementofthecarryflagare subtractedfromtheAccumulator.TheresultisstoredintheAccumulator.Notethatifthe resultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultis positiveorzero,theCflagwillbesetto1.Operation ACC←ACC−[m]−CAffectedflag(s) OV,Z,AC,C

SBCM A,[m] SubtractDataMemoryfromACCwithCarryandresultinDataMemoryDescription ThecontentsofthespecifiedDataMemoryandthecomplementofthecarryflagare subtractedfromtheAccumulator.TheresultisstoredintheDataMemory.Notethatifthe resultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultis positiveorzero,theCflagwillbesetto1.Operation [m]←ACC−[m]−CAffectedflag(s) OV,Z,AC,C

SDZ [m] SkipifdecrementDataMemoryis0Description ThecontentsofthespecifiedDataMemoryarefirstdecrementedby1.Iftheresultis0the followinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhile thenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogram proceedswiththefollowinginstruction.Operation [m]←[m]−1 Skipif[m]=0Affectedflag(s) None




SDZA [m] SkipifdecrementDataMemoryiszerowithresultinACCDescription ThecontentsofthespecifiedDataMemoryarefirstdecrementedby1.Iftheresultis0,the followinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespecified DataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummy instructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0, theprogramproceedswiththefollowinginstruction.Operation ACC←[m]−1 SkipifACC=0Affectedflag(s) None

SET [m] SetDataMemoryDescription EachbitofthespecifiedDataMemoryissetto1.Operation [m]←FFHAffectedflag(s) None

SET [m].i SetbitofDataMemoryDescription BitiofthespecifiedDataMemoryissetto1.Operation [m].i←1Affectedflag(s) None

SIZ [m] SkipifincrementDataMemoryis0Description ThecontentsofthespecifiedDataMemoryarefirstincrementedby1.Iftheresultis0,the followinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhile thenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogram proceedswiththefollowinginstruction.Operation [m]←[m]+1 Skipif[m]=0Affectedflag(s) None

SIZA [m] SkipifincrementDataMemoryiszerowithresultinACCDescription ThecontentsofthespecifiedDataMemoryarefirstincrementedby1.Iftheresultis0,the followinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespecified DataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummy instructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot 0theprogramproceedswiththefollowinginstruction.Operation ACC←[m]+1 SkipifACC=0Affectedflag(s) None

SNZ [m].i SkipifbitiofDataMemoryisnot0Description IfbitiofthespecifiedDataMemoryisnot0,thefollowinginstructionisskipped.Asthis requirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwo cycleinstruction.Iftheresultis0theprogramproceedswiththefollowinginstruction.Operation Skipif[m].i≠0Affectedflag(s) None

SUB A,[m] SubtractDataMemoryfromACCDescription ThespecifiedDataMemoryissubtractedfromthecontentsoftheAccumulator.Theresultis storedintheAccumulator.Notethatiftheresultofsubtractionisnegative,theCflagwillbe clearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation ACC←ACC−[m]Affectedflag(s) OV,Z,AC,C




SUBM A,[m] SubtractDataMemoryfromACCwithresultinDataMemoryDescription ThespecifiedDataMemoryissubtractedfromthecontentsoftheAccumulator.Theresultis storedintheDataMemory.Notethatiftheresultofsubtractionisnegative,theCflagwillbe clearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation [m]←ACC−[m]Affectedflag(s) OV,Z,AC,C

SUB A,x SubtractimmediatedatafromACCDescription TheimmediatedataspecifiedbythecodeissubtractedfromthecontentsoftheAccumulator. TheresultisstoredintheAccumulator.Notethatiftheresultofsubtractionisnegative,theC flagwillbeclearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation ACC←ACC−xAffectedflag(s) OV,Z,AC,C

SWAP [m] SwapnibblesofDataMemoryDescription Thelow-orderandhigh-ordernibblesofthespecifiedDataMemoryareinterchanged.Operation [m].3~[m].0↔[m].7~[m].4Affectedflag(s) None

SWAPA [m] SwapnibblesofDataMemorywithresultinACCDescription Thelow-orderandhigh-ordernibblesofthespecifiedDataMemoryareinterchanged.The resultisstoredintheAccumulator.ThecontentsoftheDataMemoryremainunchanged.Operation ACC.3~ACC.0←[m].7~[m].4 ACC.7~ACC.4←[m].3~[m].0Affectedflag(s) None

SZ [m] SkipifDataMemoryis0Description IfthecontentsofthespecifiedDataMemoryis0,thefollowinginstructionisskipped.Asthis requirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwo cycleinstruction.Iftheresultisnot0theprogramproceedswiththefollowinginstruction.Operation Skipif[m]=0Affectedflag(s) None

SZA [m] SkipifDataMemoryis0withdatamovementtoACCDescription ThecontentsofthespecifiedDataMemoryarecopiedtotheAccumulator.Ifthevalueiszero, thefollowinginstructionisskipped.Asthisrequirestheinsertionofadummyinstruction whilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0the programproceedswiththefollowinginstruction.Operation ACC←[m] Skipif[m]=0Affectedflag(s) None

SZ [m].i SkipifbitiofDataMemoryis0Description IfbitiofthespecifiedDataMemoryis0,thefollowinginstructionisskipped.Asthisrequires theinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwocycle instruction.Iftheresultisnot0,theprogramproceedswiththefollowinginstruction.Operation Skipif[m].i=0Affectedflag(s) None




TABRD [m] Readtable(specificpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(specificpage)addressedbythetablepointerpair (TBHPandTBLP)ismovedtothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

TABRDC [m] Readtable(currentpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(currentpage)addressedbythetablepointer(TBLP)is movedtothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

TABRDL [m] Readtable(lastpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(lastpage)addressedbythetablepointer(TBLP)ismoved tothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

XOR A,[m] LogicalXORDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalXOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″XOR″[m]Affectedflag(s) Z

XORM A,[m] LogicalXORACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalXOR operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″XOR″[m]Affectedflag(s) Z

XOR A,x LogicalXORimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalXOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″XOR″xAffectedflag(s) Z




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8-pin SOP (150mil) Outline Dimensions

SymbolDimensions in inch

Min. Nom. Max.A — 0.236 BSC —

B — 0.154 BSC —

C 0.012 — 0.020C’ — 0.193 BSC —D — — 0.069E — 0.050 BSC —F 0.004 — 0.010G 0.016 — 0.050H 0.004 — 0.010α 0° — 8°

SymbolDimensions in mm

Min. Nom. Max.A — 6.00 BSC —B — 3.90 BSC —C 0.31 — 0.51C’ — 4.90 BSC —D — — 1.75E — 1.27 BSC —F 0.10 — 0.25G 0.40 — 1.27H 0.10 — 0.25α 0° — 8°




10-pin SOP (150mil) Outline Dimensions

SymbolDimensions in inch

Min. Nom. Max.A — 0.236 BSC —B — 0.154 BSC —C 0.012 — 0.018C′ — 0.193 BSC —D — — 0.069E — 0.039 BSC —F 0.004 — 0.010G 0.016 — 0.050H 0.004 — 0.010α 0° — 8°

SymbolDimensions in mm

Min. Nom. Max.A — 6.00 BSC —B — 3.90 BSC —C 0.30 — 0.45C′ — 4.90 BSC —D — — 1.75E — 1.00 BSC —F 0.10 — 0.25G 0.40 — 1.27H 0.10 — 0.25α 0° — 8°




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The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek's products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.

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