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Ultra Thin HDI Multi-purpose Test Vehicle
Idea Stage ProjectC.B. Katzko, TTM Technologies
HDPUG Member Meeting, 2013 September 25Bennington, Vermont, USA
© High Density Packaging Users Group, Inc.
Project Background
• The “Post PC Era” is upon us• PC sales peaked Q1 2011, declined 4.9% YoY Q4-2011/Q4-2012
• Tablets outsold notebooks in USA, China in 2012
• Rapid adoption of consumer cloud computing
• OEMs/ODMs shifting R+D focus from desktop to mobile/wearable
© High Density Packaging Users Group, Inc.
Worldwide Shipments by Segment (Thousands)
2012 2013 2014 2017
PC (DT & NB) 341,263 315,229 302,315 271,612
Ultra Book 9,822 23,592 38,687 96,350
Tablet 116,113 197,202 265,731 467,951
Mobile Phone1,746,17
61,875,77
41,949,72
22,128,87
1
Total2,213,37
32,411,79
62,556,45
52,964,78
3
Source : Gartner, April 2013
2012-Q1 2013-Q10
500,000
1,000,000
1,500,000
2,000,000
2,500,000
1,470,202
2,100,202
Global Smartphone Sales
Source : Gartner, May 2013
42.85%
Project Background
• Handheld/wearable electronic packaging:• Design envelope dominated by batteries & displays
• Miniaturized & modularized PCBA design with high flex content
• Extensive use of SoC design, with SiP, PoP & WCSP packaging
• Low profile CSP, WCSP & microQFN devices, 0.40~0.30mm pitch
• Ultra-thin 8-14 Layer HDI PCB design, current and near term:
• Via in Pad/stacked via ICT with decreasing pad diameter
• Conductor line/space design rules approaching 40/60
• 2 track routing in 0.40umm pitch devices up to 36x36 BGA
• 25~40um dielectrics
• 250~800um thickness
• Flex & coreless HDI
© High Density Packaging Users Group, Inc.
How does the performance & reliability stack-up?
Examples
© High Density Packaging Users Group, Inc.
Source : IFIXIT www.ifixit.com/Teardown
Problem Statement
• Methods & test vehicles lag design by a decade• Do not capture interconnect density or thinness
• Miss potential failure mechanisms (e.g., ion migration)
• Low density patterns introduce artifacts not seen in production (e.g., distortion of via stack)
• Test parameters may exceed practical limits of design or are inappropriate to application (e.g., 50V CAF)
• Increasingly abandoned by OEMs in favor of non-standardized “end product” test vehicles
• Widen the gap between up-stream development & down-stream practice
• Must be solved by component, PCB & material supply-chain actors, OEMs are working in a black box
© High Density Packaging Users Group, Inc.
Project Proposal
• Design, test & standardize an open-source rigid HDI test vehicle for qualification of components, PCBs & PCBA
• Scaled to smartphone form factors
• Modularized for various mixes of bare board & assembly testing
• 0.40, 0.35, 0.30 & 0.25mm pitch BGA devices
• 01005 passive devices
• 40/60um nominal line/space design rules
• All Layer Via interconnect with stacked vias, Via in Pad
• 12 layer build-up with options for HF FR4 & coreless materials with 25~40um thick dielectrics (e.g., 1027, 1037, PI film, RCC)
• SMT or fine pitch test connectors
• Standardized array modules & fixtures for assembly & test
• Deliverables: TV Design, test build & test report
• Duration : 12-16 months (depending on duration of tests)
© High Density Packaging Users Group, Inc.
Project Work Flow
PCBA TV PCBA TV
Data Analysis &
Failure Analysis
PCBA Assembly &
ICT
PCB Fabrication& SOT
PCB TV PoCBuild & Test
( reflow, MSA )
PCB TV Redesign
( if required)
PCBA Assembly
Tooling Design & Preparation
PCB Materials
Components & Assembly
Materials
Short Term Tests
Long Term Tests
Test Report Paper & Poster
PCBA TV PCB TV PCB TV
Short Term Tests
Long Term Tests
End
Start
PCB TV Design& Tooling
Idea Stage
Implementation Stage
Project Task ListPCB TV at CAD Sept.23
Define b
y Q
1-2
01
4
Participants
Engent Fei Xie
Kyzen Mike Bixenmann
Panasonic Tony Senese
TTM Tommy Huang
Zaron Huang
Angela Lee
Summer Xiao
C.B. Katzko Project Leader
HDPUG Ruben Bergman
Robert Smith Project Facilitator
Test Vehicle Design Progress
12 Layer Build-up
• Typical logic board design is 10-14 layers
• 12 layers is best match to electrical & IST coupons
• 1037 construction for proof of concept builds
Layer Material TypeTarget
Thickness um Description Cu Density
Build-up Layers
1 9um Cu Foil + Cu Plating 25 SMD Assembly -
1x1067, 1037 or 1027 0.4 Prepreg Dielectric
2 9um Cu Foil + Cu Plating 18 Plane 75%
1x1067, 1037 or 1027 40 Prepreg Dielectric
3 9um Cu Foil + Cu Plating 18 Signal 50%
1x1067, 1037 or 1027 40 Prepreg Dielectric
4 9um Cu Foil + Cu Plating 18 Plane 75%
1x1067, 1037 or 1027 40 Prepreg Dielectric
5 9um Cu Foil + Cu Plating 18 Signal 50%
1x1067, 1037 or 1027 40 Prepreg Dielectric
Core
6 9um Cu Foil + Cu Plating 18 Plane 75%
0.60mm 1x1067 or 1080 60 Core Dielectric
7 9um Cu Foil + Cu Plating 18 Plane 75%
Build-up Layers
1x1067, 1037 or 1027 40 Prepreg Dielectric
8 9um Cu Foil + Cu Plating 18 Signal 50%
1x1067, 1037 or 1027 40 Prepreg Dielectric
9 9um Cu Foil + Cu Plating 18 Plane 75%
1x1067, 1037 or 1027 40 Prepreg Dielectric
10 9um Cu Foil + Cu Plating 18 Signal 50%
1x1067, 1037 or 1027 40 Prepreg Dielectric
11 9um Cu Foil + Cu Plating 18 Plane 75%
1x1067, 1037 or 1027 40 Prepreg Dielectric
12 9um Cu Foil + Cu Plating 25 SMD Assembly -
650.4 Total Thickness NB - Prepreg resin content % requires adjustment based on copper pattern density
Confirmed for
Design
high density & thickness
yield
low density & thickness
yield
Panel Layout
• 2 set designs, “PCB test” & “PCBA” test, 2+2 sets per panel
• Sets step diagonally opposite, “inside” & “outside”• “PCBA Test” sets can be divided into sub-sets for assembly
Confirmed for
Design
Set B1 PCBA
Set APCB
Set B2PCBA
Set A2PCB
500mm Y-axis (warp)
400
mm
X –
axis
(fi
ll)
PC
B p
rocess d
irecti
on
17
0.
0220.
0
Set Design
220.00
170
.00
kerf 2.0 typical
50.00 5
0.0 0
Confirmed for
Design
206.00
154
.00
PC
B p
rocess d
irecti
on
Multiple
modules
combined for
large
coupons
50x50mm Module
connector & break-away coupon zone
con
nect
or
& b
reak-
aw
ay c
ou
pon
zon
e
connector & break-away coupon zone
con
nect
or
& b
reak-
aw
ay c
ou
pon
zon
e
6mm x 38mm1~4 sidesas required
populated zone38mm x 38mm
Ø 2mm NPTHfor fixture or
hangingConnectors : 2.54mm pitchWire : 26 AWG or 28 AWGPins : Typically 0.50mm squarePTH : Ø1.05mm (1.2mm drill)
3mm
3mm
support tab of fixture
Confirmed for
Design
PCB Floor Plan
X –
axis
(fill)
Y-axis (warp)
PC
B p
rocess d
irecti
on
Under Redesig
n
Confirmed for
Design
PCBA Floor PlanP
CB
pro
cess d
irecti
on
Preliminary
Proposal
X –
axis
(fill)
Y-axis (warp)
Drop Test Holes
One Pitch Each Side
Pending,
need
OEM
inputs
EL coupons
include lines
with vias to
characterize
interconnect
s
Due to ultra-
thin
dielectric
layers,
electrical
performance
is critical
Want Ad
• Human Resources – Practitioners or Developers
• Device ODMs
• PCB designers (OEMs or fabricators)
• PCB & assembly materials suppliers
• Assembler with 0.30mm pitch P+P capability
• Captive or Independent test labs
• Material Resources
• Daisy-chain devices (donated or purchased)
• PCB materials (donated)
• PCB fabrication & assembly services
• Test services
• Timeline
• Design 3-4 months
• PoC Lot Fabrication & Test 1 month
• PCB Fab, Assembly & Test 6-9 months © High Density Packaging Users Group,
Inc.
Join
Now!
Thank You
Q&A© High Density Packaging Users Group,
Inc.