INDIAN INSTITUTE OF SPACE SCIENCE AND TECHNOLOGY

THIRUVANANTHAPURAM

IMPLEMENTATION OF DIGITAL DOWN CONVERTER IN FPGA

INTERNAL PROJECT REPORT

Submitted By:

Amritha Prasad

Brajpal Singh

Dheerendra Kumar

Sujeev Kumar

IN

DIGITAL SIGNAL PROCESSING DIVISION (DSD) AT

VIKRAM SARABHAI SPACE CENTRE, THIRUVANANTHAPURAM

5th JULY ’10 – 13th AUGUST ’10

Acknowledgement

A small step in the field of technology requires great support and expert guidance.

Our successful project is a faithful culmination effort by many people, some directly

involved, some enlightening us with their concealed presence.

We extend a warm gratitude to Ms.Sajitha G (Sc. /Engg. – SF), DSD/CDSG/AVN

who has been an integral part of our project for being an enormous support in achieving and

successfully completing this project. Her guidance has been a major thrust for our project.

Our hands on session at the Lab were very educative. We thus, thank Mr. Prakash,

(Sr. Technical Assistant), DSD/CDSG/AVN who helped us with almost everything

including our experimental procedure, visits to various labs and lastly for spending his

valuable time with us.

We take this opportunity to thank the administrative team of VSSC as well as of IIST

for accessing ISRO’s facilities. We at this juncture would like to extend our profound

gratitude to Dr. B.N. Suresh, Director IIST without whom this endeavour would not have

been a reality.

Lastly, we would like to thank all those who had silently been behind us but may have

left our notice for making this project a success.

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Abstract

Digital Down Converters (DDCs) represent a cornerstone technology in RADAR

communication system. Over the past several years, the tuning, data reduction and filtering

functions associated with DDCs have shifted from ASIC implementations towards IP cores in

FPGAs. This shift brings many critical advantages including architectural flexibility, higher

precision processing, higher channel density, and lower power and cost per channel. With the

advent of each new higher performance FPGA family, these benefits grow. This article,

explores implementing DDC designs in FPGAs.

iii

Acronyms

FPGA - Field Programmable Gate Array

ASIC - Application Specific Integrated Circuit

DSD - Digital Signal Processing Division

DOS - Department of Space

ISRO - Indian Space Research Organization

VSSC - Vikram Sarabhai Space Centre

VHDL - Very high-speed integrated circuit Hardware Description Language

DDS - Direct Digital Synthesis

NCO - Numeric Controlled Oscillator

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Contents

Acknowledgement....................................................................................................................... i

Abstract....................................................................................................................................... ii

Acronyms.................................................................................................................................... iii

1 Introduction .......................................................................................................................... - 1 -

1.1 About the Organization: ISRO ......................................................................................... - 1 -

1.2 About the Centre: VSSC .................................................................................................. - 2 -

1.3 About the Division: Digital Signal Processing Division (DSD) ............................................ - 2 -

2 Objectives .............................................................................................................................. - 4 -

3 Description of the Works ....................................................................................................... - 5 -

3.1 DDC: Theory ................................................................................................................... - 5 -

3.1.1 Direct digital synthesis ............................................................................................ - 8 -

3.2 About the tools and software used ................................................................................. - 9 -

3.2.1 Libero IDE V8.3 The Simulation and Synthesis Software .......................................... - 9 -

3.2.2 VHDL .................................................................................................................... - 12 -

3.2.3 ModelSim ............................................................................................................. - 15 -

3.2.4 FPGA .................................................................................................................... - 15 -

3.2.5 Actel ProASICPLUS Evaluation Board ....................................................................... - 26 -

3.3 Design .......................................................................................................................... - 28 -

3.3.1 DDS ...................................................................................................................... - 28 -

3.3.2 Digital Multiplier................................................................................................... - 28 -

3.3.3 FIR filter design ..................................................................................................... - 28 -

3.3.4 Decimator ............................................................................................................ - 28 -

3.4 Codes ........................................................................................................................... - 29 -

3.4.1 MATLAB Codes ..................................................................................................... - 29 -

3.4.2 VHDL Codes .......................................................................................................... - 30 -

4 Observations and Results ..................................................................................................... - 55 -

5 Conclusion ........................................................................................................................... - 60 -

6 Discussion ............................................................................................................................ - 61 -

7 BIBLIOGRAPHY ..................................................................................................................... - 62 -

APPENDIX .................................................................................................................................... - 63 -

v

LIST OF FIGURES

Figure 1: Block diagram of DDC ...................................................................................................... - 5 - Figure 2: Spectrum of the analog received signal before digitization .............................................. - 6 - Figure 3: Spectrum of the received signal after digitization ............................................................ - 6 - Figure 4: Spectrum of the signal after mixer showing sum and difference frequencies ................... - 6 - Figure 5: Response of a low pass filter used in DDC ....................................................................... - 7 - Figure 6: Spectrum of the signal after filter .................................................................................... - 7 - Figure 7: Spectrum of the signal after decimation .......................................................................... - 7 - Figure 8:Basic functional block diagram and signal flow of a DDS system ....................................... - 8 - Figure 9:Simplified example illustration of a logic cell .................................................................. - 22 - Figure 10:Logic Block Pin Locations .............................................................................................. - 22 - Figure 11: Switch box topology .................................................................................................... - 23 - Figure 12: Single sided amplitude spectrum after DDS. Fc=10MHz ............................................... - 55 - Figure 13: Single sided amplitude spectrum after DDS fc=40 MHz ................................................ - 55 - Figure 14: Single sided amplitude spectrum after DDS fc=80 MHz ................................................ - 56 - Figure 15: Single sided amplitude spectrum after multiplier ........................................................ - 56 - Figure 16: Single sided amplitude spectrum after filter ................................................................ - 57 - Figure 17: Single sided amplitude spectrum after decimator........................................................ - 57 - Figure 18: Waveforms obtained during simulation of vhd code for DDS ....................................... - 58 - Figure 19: Waveforms obtained during simulation of vhd code for DDC ...................................... - 59 -

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1 Introduction

1.1 About the Organization: ISRO India as a developing country is proud today that it is second to none in this

world in harnessing space technology for its national development and this is mainly due to

the foresight of our leaders and the recognition of the immense potential of the space

technology and its contribution towards national development.

Space based research is clearly the frontier technology that the world is moving on

today. The Indian space research program, started in 1962 has a broad scope covering many

fields such as development of spacecraft launch vehicles, satellites and conduct of large scale

application missions. The Indian space program has to its credits lots of achievements in the

development of application in various fields such as telecommunication, broadcasting,

nation-wide telecasts, resource survey and management, environment monitoring,

meteorological service and other such activities. These services are implemented through

development of operational spacecraft with emphasis on self reliance. The program is well

integrated to provide space service in real time manner.

ISRO is one of the most prestigious organizations of our nation. The ISRO Satellite

Centre is a part of it. The Department of Space (DOS) is responsible for the execution of the

activities of our country in space technology. ISRO under DOS carries out technical activities

related to space research and its applications. Self-reliance in space technology and

applications is its ultimate goal. ISRO armed with its goal, has set out to provide the means to

achieve it. A number of centres and units have been established by ISRO in order to develop

expertise in major areas of space technology, launch vehicles, spacecrafts and launch

facilities.

The Indian Space Research Organization under DOS plays a key role in planning and

execution of national space program. Over the years, ISRO has developed a family of

sounding rockets, launch vehicles and satellites. India has made significant progress in

developing an indigenous capability in space technology and has come long way in realizing

the primary objective of its space program. By achieving self-reliance in launch capability

through PSLV and GSLV projects, ISRO is in the forefront among the leading nations in

technology.

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1.2 About the Centre: VSSC Vikram Sarabhai Space Centre is ISRO’s lead Centre for launch vehicles, with its expertise in

design, development and realization of sounding rockets and launch vehicles. It has earned

considerable expertise in design, development and integration of satellite launch vehicles for

various missions; technology development, qualification and realization of various sub-

systems; realization of components materials, chemicals and components, avionics, control

systems, aeronautics and solid propulsion; precision fabrication; establishing and

maintaining state of-the-art infrastructure within VSSC and industry; technology transfer and

exploring areas for spin off technologies; specialization in launch vehicle projects

management; advanced R&D in areas of relevance to satellite launch vehicles; self reliance in

launch vehicle technology with the full use of industry and academic institutions and through

a planned technology transfer process including spin-offs; and design, development and

realization of identified spacecraft subsystems for ISRO’s satellite programme.

The Organisation of VSSC is structured in a matrix form comprising of Projects and

Entities. The core project teams manage project activities. System level activities of the

projects are carried out by system development agencies. Major programmes of VSSC

include Polar Satellite Launch Vehicle (PSLV), Geosynchronous Satellite Launch Vehicle

(GSLV), Rohini Sounding Rocket, Space Capsule Recovery Experiment, Reusable Launch

Vehicles and Air Breathing Propulsion.

1.3 About the Division: Digital Signal Processing Division (DSD) The Digital Signal processing Division (DSD) comes under the Avionics entity and is

responsible for design of various packages in the launch vehicle. It has three major sections

viz. Signal processing section, image processing section and sequencing electronics and

power conditioning section.

Signal Processing Section has designed the Flush Air Data Systems (FADS) for real time

computation of the various air data parameters such as Mach number (M), angle of attack

(alpha), angle of side slip (beta) and dynamic pressure (q) of RLV-TD. The Advanced Signal

Processing Unit & Integrated Structural Measurement Unit (ISMU) for measuring onboard

vibration, acoustics and shock channels of LV (on board processing done with ADSP 21060)

is also being developed by this section. This section is also responsible for the Signal

Processing Card for SRE-II which measures the re- entry vibration, acoustics, shock and

pyro current signals of the re-entry module (on board processing done with ADSP 21060).

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Image Processing Section handles the Advanced Video Imaging System for GSLV Mk III

which captures the various separation events in Launch Vehicles. The Radiation Dosimeter

payload for SRE-2 / HSP used for measuring space radiation in real time has also been

developed by this section in collaboration with PRL. The development of Triggering Unit &

SEM for SRE-2, Miniaturized Video Imaging System (Mini VIS) and the Audio Video

Processing System for HSP are some of the other main activities of the image processing

section.

Sequencing electronics and power conditioning section is responsible for the design and

implementation of DC-DC converters, power modules for ATS, Sequencer for ATV D 01

Mission. The section is currently working on the implementation of short circuit protection

for SMT DC-DC converters, SMT DC-DC Converter for SRE II mission, 70V Boost

converter for SRE II mission and the Miniaturization of SMT DC-DC Converter using planar

magnetic

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2 Objectives The objectives of the project are as follows:

1 To write a vhd code for DDC.

2 Implement DDS (a component of DDC) using FPGA.

3 To analyze its behavior, feature and characteristics using MATLAB.

4 To gain a deeper understanding of the concepts of a digital receiver.

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3 Description of the Works

3.1 DDC: Theory A fundamental part of many communications systems is Digital Down Conversion

(DDC). Digital radio receivers often have fast ADC converters to digitize the band limited

RF or IF signal generating high data rates. But in many cases, the signal of interest represents

a small proportion of that bandwidth. To extract the band of interest at this high sample rate

would require a prohibitively large filter. A DDC allows the frequency band of interest to be

moved down the spectrum so the sample rate can be reduced, filter requirements and further

processing on the signal of interest become more easily realizable.

In the Doppler Radar systems we send an RF frequency and receive the sum of RF

and Doppler frequency. The DDC allows us to select the RF band, and to shift its frequency

down to baseband (Doppler frequency) and in doing so reduce the sample rate.

Figure: 1 Block diagram of DDC.

A Digital Down Converter is basically complex mixer, shifting the frequency band of

interest to baseband. Block diagram of DDC is shown above in Figure 1.

Consider the spectrum of the original continuous analogue signal prior to digitization, as

shown in Figure 2, because it is a real signal it has both positive and negative frequency

components. If this signal is sampled by a single A/D converter at a rate that is greater than

twice the highest frequency the resulting spectrum is as shown in Figure 3. The continuous

analogue spectrum repeated around all of the sample frequency spectral lines

Mixer

NCO (Local Oscillator)

ADC Decimator 16 – tap FIR Low Pass Filter

Output

Analog Input

Figure 1: Block diagram of DDC

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Figure 2: Spectrum of the analog received signal before digitization

Figure 3: Spectrum of the received signal after digitization

The first stage of the DDC is to mix, or multiply, this digitized stream of samples with

a digitized cosine for the phase channel and a digitized sine for the quadrature channel and so

generating the sum and difference frequency components. The mixer frequency has been

chosen to move the signal frequency band down to baseband. The amplitude spectrum of

either the phase or quadrature channel after mixing, looks like shown in Figure 4.

Figure 4: Spectrum of the signal after mixer showing sum and difference frequencies

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The phase and quadrature samples must be filtered with identical filters, which, with

digital filters in an FPGA are not a problem. A digital filter frequency response is always

symmetrical about 0.5Fs. The filter response is shown in Figure 5. The unwanted frequency

components fall outside the pass bands of the filter, giving the resultant spectrum for both

phase and quadrature as shown in Figure 6.

Figure 5: Response of a low pass filter used in DDC

Figure 6: Spectrum of the signal after filter

The sample frequency is now much higher than required for the maximum frequency

in our frequency band and so the sample frequency can be reduced or decimated, without any

loss of information. Spectrum after decimation is shown in Figure 7.

Figure 7: Spectrum of the signal after decimation

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3.1.1 Direct digital synthesis DDS technology is an innovative circuit architecture that allows fast and precise

manipulation of its output frequency, under full digital control. DDS also enables very high

resolution in the incremental selection of output frequency, generating a phase-continuous

waveform. The basic functional block diagram and signal flow of a DDS system is shown in

Figure 8. The output frequency of a DDS system can be expressed by

푓 = Δ휑 × ,

usually called tuning equation, where Δφ is the phase increment value of the accumulator,

fclk is the system clock frequency and N is the accumulator resolution. Being fclk and N fixed

system parameters, the output frequency is linearly dependent of the phase increment

number.

In analog systems, FM is accomplished by using reactance modulation. Typically, the

modulating analog signal is applied to a varicap diode which forms part of the resonant

oscillator circuit. Unfortunately the relationship between modulating voltage and oscillator

frequency is nonlinear. Furthermore, it is often difficult to prevent over modulation and

maintain consistent deviations over wide output center frequency variations. All these

problems are completely solved with DDS numeric FM. Linearity is typically orders of

magnitude better in numeric FM systems than analog reactance modulators. In the last couple

of years, there has been a considerable increase in the availability of low-power, high-

performance and high-speed DDS devices based on the CMOS fabrication process.

NCO

Phase Register Clock Look-Up

Table

Frequency Control (Tune) word

Adder DAC

Reset Output

Figure 8:Basic functional block diagram and signal flow of a DDS system

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3.2 About the tools and software used

3.2.1 Libero IDE V8.3 The Simulation and Synthesis Software Libero IDE is the most comprehensive and powerful FPGA design and development software

available, providing start-to-finish design flow guidance and support for novice and

experienced users alike. Libero IDE combines Actel tools with such EDA powerhouses as

Sinplify, ModelSim, ViewDraw, PALACE, and WaveFormer Lite. Libero IDE software

supports all Actel Flash and antifuse products, Including the popular Fusion, IGLOO/e,

ProASIC3E, ProASIC3, ProASICPLUS, and Axcelerator products.

The following are highlights of features for Libero IDE v8.3:-

Designer Blocks:

A block design flow enables you to create a design that can be defined as a unique Designer

Block. The Designer Block can be instantiated into a design or saved for future use. You can

optimize a completed block using the standard synthesis, simulation and place-and-route

flows. Component placement and block timing are preserved when you publish your

Designer Block. When creating a new project in Libero IDE, enable Block Creation, proceed

with the standard Libero IDE design flow, and publish your block. The block can then be

instantiated into any design.

Synplicity Identify AE Debug Software:

Synplicity Identify AE Debug software is now integrated in Libero IDE. It supports Ariel's

Fusion, ProASIC3/E, and ProASlCPLUS devices. Launch the Identity debugger directly from

the Libero IDE Project Manager.

Mixed VHDL and Verilog Source Files:

Libero IDE now supports designs with mixed VHDL and Verilog

source files. Libero passes libraries and generates netlists in your preferred HDL

format. Synplify Pro AE is required for synthesis and ModelSim SE (full feature version

from Mentor) is required to run simulation on a mixed HDL design.

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HDL Templates for Verilog and VHDL:

HDL Templates for Verilog or VHDL are available for quick insertion into the HDL code.

HDL templates are in a library of cast HDL command statements that can be copied or

automatically inserted into the HDL design in the text editor window. A Templates window

makes it easy to copy/insert from a large list with commands such as "path delay statement",

"wait statement", or "port declaration".

SmartTime:

Enhanced Min Delay (EMD) support for ProASIC - SmartTime now provides support for

precise minimum delay/hold-time analysis. This new feature eliminates the need to over-

guardband a design for minimum delay, providing a more comprehensive, precise way to

perform chip-to-chip evaluation of external setup/hold and clock-to-out timing.

Clock Analysis for Virtual Clocks:

In some cases, paths from one FPGA may sensitize or be sensitized by paths outside the

FPGA (e.g. on the board, or on another FPGA). The new Virtual Clock capability in

SmartTime enables you to specify a constraint for a clock that is running outside the FPGA,

and thus do timing analysis on the design as it interacts with this "virtual" circuitry.

Bottleneck Analysis:

A bottleneck is a point in the design that contributes to multiple railing paths. This new

feature finds and lists all bottlenecks according to severity. The list has a format similar to the

existing "datasheet" report.

SmartPower:

Initialization with SmartTime Timing Constraints - For each clock in SmartPower, the

equivalent clock and its constraints are found in SmartTime. The power is then calculated

using your actual timing constraints. This approach gives an accurate view of the power

consumption based on actual expected operating frequencies, and enables you to keep

frequency information between SmartTime and SmartPower in sync.

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Advanced Power Analysis for Memories:

This feature adds the capability to view power consumption for memory blocks such as

RAM, FIFO and Flash Memory based on specifics of the memories, such as number of active

bits, aspect ratio of the memory blocks, the number of memory blocks, etc. improved

Thermal Analysis in the Summary Tab and an InstanceProperties Pop-Up box that provides

detailed information about a specific selected Instance.

WaveFormer Lite Analog Testbenches for Fusion:

WaveFormer Lite includes analog waveform creation for Fusion design testbenches. Various

pre-defined analog waveforms are available such as Sinusoidal, Step, Increment, Random,

RC discharge. For a given input, the testbench is created by specifying or creating the

waveform type and then defining the specific timing and signal height requirement.

RAM interfacing now available for ProASIC:

Synplify/Pro can automatically infer synchronous and synchronously resettable RAMs from

your HDL (Verilog or VHDL) source code and, where appropriate, generate technology-

specific single or dual-port Rams. You do not need any special input, like attributes or

directives in your source code for this inference. The RTL-level RAM inferred by the

compiler always has an asynchronous READ. During synthesis, the mappers convert this to

the appropriate technology specific RAM primitives. Depending on the technology used, the

synthesized design can include RAM primitives with either synchronous or asynchronous

READs.

AX RAM/FIFO Support:

Synplify previously treated RAM & FIFOs as black boxes with respect to timing as there

were no RAM or FIFO timing models. RAM timing was not distinguished for the different

antifuse families. Synplify has separate AX libraries for RAM and FIFO timing models.

AX I/O Attribute synthesis support:

The SCOPE constraint editor enables you to specify an I/O standard (LVTTL, LVCMOS,

etc) and set the attributes such as drive strength, slew rate, and termination. The software

stores the pad type specification and the parameter values in the syn_padtype attribute. When

you synthesize your design, the I/O specifications are mapped to the appropriate I/O pads

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within the technology. Advanced Fanout Control provides three different levels of fanout -

You can set independent fanouts for local nets, for blocks, and global nets.

FlashPro 8.3:

Flashpro 8.3 introduces support for Fusion and ProASIC devices in the Chainbuilder

programming chain.

3.2.2 VHDL

The name: VHSIC (Very High Speed Integrated Circuit) Hardware Description Language

Main Features

Supports the whole design process:

system level

RT level

logic level

circuit level (to some extent)

It is suitable for specification in both behavioural domain and structural domain. Precise

simulation semantics is associated with the language constructs.

Basic Constructs

The basic building block of a VHDL model is the entity. An entity is described as a set of

design units: entity declaration, architecture body, package declaration, package body,

configuration declaration.

History

VHDL was originally developed at the behest of the US Department of Defence in order to

document the behaviour of the ASICs that supplier companies were including in equipment.

That is to say, VHDL was developed as an alternative to huge, complex manuals which were

subject to implementation-specific details.

The idea of being able to simulate this documentation was so obviously attractive that logic

simulators were developed that could read the VHDL files. The next step was the

development of logic synthesis tools that read the VHDL, and output a definition of the

physical implementation of the circuit. Modern synthesis tools can extract RAM, counter, and

arithmetic blocks out of the code, and implement them according to what the user specifies.

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Thus, the same VHDL code could be synthesized differently for lowest area, lowest power

consumption, highest clock speed, or other requirements.

VHDL borrows heavily from the Ada programming language in both concepts (for example,

the slice notation for indexing part of a one-dimensional array) and syntax. VHDL has

constructs to handle the parallelism inherent in hardware designs, but these constructs

(processes) differ in syntax from the parallel constructs in Ada (tasks). Like Ada, VHDL is

strongly typed and is not case sensitive. There are many features of VHDL which are not

found in Ada, such as an extended set of Boolean operators including nand and nor, in order

to directly represent operations which are common in hardware. VHDL also allows arrays to

be indexed in either direction (ascending or descending) because both conventions are used in

hardware, whereas Ada (like most programming languages) provides ascending indexing

only. The reason for the similarity between the two languages is that the Department of

Defense required as much of the syntax as possible to be based on Ada, in order to avoid re-

inventing concepts that had already been thoroughly tested in the development of Ada.

Important dates:

1983: development started with support from US government.

1987: adopted by IEEE as a standard (IEEE Std. 1076 - 1987).

1993: VHDL’92 adopted as a standard after revision of the initial version

(IEEE Std. 1076 - 1993).

Design

VHDL is commonly used to write text models that describe a logic circuit. Such a model is

processed by a synthesis program, only if it is part of the logic design. A simulation program

is used to test the logic design using simulation models to represent the logic circuits that

interface to the design. This collection of simulation models is commonly called a testbench.

VHDL has file input and output capabilities, and can be used as a general-purpose language

for text processing, but files are more commonly used by a simulation testbench for stimulus

or verification data. There are some VHDL compilers which build executable binaries. In this

case, it might be possible to use VHDL to write a testbench to verify the functionality of the

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design using files on the host computer to define stimuli, to interact with the user, and to

compare results with those expected. However, most designers leave this job to the simulator.

It is relatively easy for an inexperienced developer to produce code that simulates

successfully but that cannot be synthesized into a real device, or is too large to be practical.

One particular pitfall is the accidental production of transparent latches rather than D-type

flip-flops as storage elements.

VHDL is not a case sensitive language. One can design hardware in a VHDL IDE (for FPGA

implementation such as Xilinx ISE, Altera Quartus, or Synopsys Synplify) to produce the

RTL schematic of the desired circuit. After that, the generated schematic can be verified

using simulation software which shows the waveforms of inputs and outputs of the circuit

after generating the appropriate testbench. To generate an appropriate testbench for a

particular circuit or VHDL code, the inputs have to be defined correctly. For example, for

clock input, a loop process or an iterative statement is required.

The key advantage of VHDL when used for systems design is that it allows the behavior of

the required system to be described (modeled) and verified (simulated) before synthesis tools

translate the design into real hardware (gates and wires).

Another benefit is that VHDL allows the description of a concurrent system (many parts,

each with its own sub-behavior, working together at the same time). VHDL is a Dataflow

language, unlike procedural computing languages such as BASIC, C, and assembly code,

which all run sequentially, one instruction at a time.

A final point is that when a VHDL model is translated into the "gates and wires" that are

mapped onto a programmable logic device such as a CPLD or FPGA, then it is the actual

hardware being configured, rather than the VHDL code being "executed" as if on some form

of a processor chip.

Synthesizable constructs and VHDL templates

VHDL is frequently used for two different goals: simulation of electronic designs and

synthesis of such designs. Synthesis is a process where a VHDL is compiled and mapped into

an implementation technology such as an FPGA or an ASIC. Many FPGA vendors have free

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(or inexpensive) tools to synthesize VHDL for use with their chips, where ASIC tools are

often very expensive.

Not all constructs in VHDL are suitable for synthesis. For example, most constructs that

explicitly deal with timing such as wait for 10 ns; are not synthesizable despite being

valid for simulation. While different synthesis tools have different capabilities, there exists a

common synthesizable subset of VHDL that defines what language constructs and idioms

map into common hardware for many synthesis tools. IEEE 1076.6 defines a subset of the

language that is considered the official synthesis subset. It is generally considered a "best

practice" to write very idiomatic code for synthesis as results can be incorrect or suboptimal

for non-standard constructs.

3.2.3 ModelSim Modelsim is a simulation tool. It doesn’t create any hardware, even on the monitor (as

Leonardo does). Modelsim just compiles the code, checks syntax and provides the waveform

of the design behavior according to the inputs values defined at the Test Bench file.

Therefore, Modelsim is a tool for the functional checking of the design.

3.2.4 FPGA In the 1980s, when the first programmable DSP chips began appearing on the market,

engineers quickly began designing boards and systems around these parts to replace the

discrete registers, adders, state machines and logic of traditional digital signal processing

hardware.

About ten years later, programmable RISC processors for workstations like the Intel i860 and

Motorola PowerPC were found to perform quite well on DSP algorithms. Even though these

chips were not aimed at the DSP embedded computing market, because their built-in floating-

point ALUs and hardware multipliers, they were recruited as alternatives to native DSP chips

and began appearing on embedded system boards.

Then at the turn of the century, the relatively sophisticated FPGA (field programmable gate

array) emerged to replace more primitive programmable devices used for glue logic, state

machines, and interface engines. With a reasonable density of resources, FPGAs could now

implement the ALUs, multipliers and logic functions essential for DSP. Once FPGA vendors

became aware of this trend, they invested heavily in boosting DSP capabilities. As a result,

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FPGAs can now easily outperform DSP and RISC processors in many key benchmark

algorithms.

But this performance comes at a price: FPGA algorithm development requires a completely

different skill set and is much more challenging than programming a DSP or RISC processor.

To help overcome this, optimized IP cores with fully characterized performance are now

available from many sources.

A field-programmable gate array (FPGA) is an integrated circuit designed to be

configured by the customer or designer after manufacturing—hence "field-programmable".

The FPGA configuration is generally specified using a hardware description language (HDL),

similar to that used for an application-specific integrated circuit (ASIC) (circuit diagrams

were previously used to specify the configuration, as they were for ASICs, but this is

increasingly rare). FPGAs can be used to implement any logical function that an ASIC could

perform. The ability to update the functionality after shipping, partial re-configuration of the

portion of the design and the low non-recurring engineering costs relative to an ASIC design

(not withstanding the generally higher unit cost), offer advantages for many applications.\

FPGAs contain programmable logic components called "logic blocks", and a hierarchy of

reconfigurable interconnects that allow the blocks to be "wired together"—somewhat like a

one-chip programmable breadboard. Logic blocks can be configured to perform complex

combinational functions, or merely simple logic gates like AND and XOR. In most FPGAs,

the logic blocks also include memory elements, which may be simple flip-flops or more

complete blocks of memory.

In addition to digital functions, some FPGAs have analog features. The most common analog

feature is programmable slew rate and drive strength on each output pin, allowing the

engineer to set slow rates on lightly loaded pins that would otherwise ring unacceptably, and

to set stronger, faster rates on heavily loaded pins on high-speed channels that would

otherwise run too slow. Another relatively common analog feature is differential comparators

on input pins designed to be connected to differential signaling channels. A few "mixed

signal FPGAs" have integrated peripheral ADCs and DACs and analog signal conditioning

blocks allowing them to operate as a system-on-a-chip. Such devices blur the line between an

FPGA, which carries digital ones and zeros on its internal programmable interconnect fabric,

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and field-programmable analog array (FPAA), which carries analog values on its internal

programmable interconnect fabric.

History

The FPGA industry sprouted from programmable read-only memory (PROM) and

programmable logic devices (PLDs). PROMs and PLDs both had the option of being

programmed in batches in a factory or in the field (field programmable), however

programmable logic was hard-wired between logic gates.

In the late 1980s the Naval Surface Warfare Department funded an experiment proposed by

Steve Casselman to develop a computer that would implement 600,000 reprogrammable

gates. Casselman was successful and a patent related to the system was issued in 1992.

Some of the industry’s foundational concepts and technologies for programmable logic

arrays, gates, and logic blocks are founded in patents awarded to David W. Page and

LuVerne R. Peterson in 1985.

Xilinx Co-Founders, Ross Freeman and Bernard Vonderschmitt, invented the first

commercially viable field programmable gate array in 1985 – the XC2064. The XC2064 had

programmable gates and programmable interconnects between gates, the beginnings of a new

technology and market. The XC2064 boasted a mere 64 configurable logic blocks (CLBs),

with two 3-input lookup tables (LUTs). More than 20 years later, Freeman was entered into

the National Inventor's Hall of Fame for his invention.

Xilinx continued unchallenged and quickly growing from 1985 to the mid-1990s, when

competitors sprouted up, eroding significant market-share. By 1993, Actel was serving about

18 percent of the market.

The 1990s were an explosive period of time for FPGAs, both in sophistication and the

volume of production. In the early 1990s, FPGAs were primarily used in telecommunications

and networking. By the end of the decade, FPGAs found their way into consumer,

automotive, and industrial applications.

FPGAs got a glimpse of fame in 1997, when Adrian Thompson, a researcher working at the

University of Sussex, England, merged genetic algorithm technology and FPGAs to create a

- 18 -

sound recognition device. Thomson’s algorithm configured an array of 10 x 10 cells in a

Xilinx FPGA chip to discriminate between two tones, utilising analogue features of the

digital chip. The application of genetic algorithms to the configuration of devices like

FPGA's is now referred to as evolvable hardware.

Modern developments

A recent trend has been to take the coarse-grained architectural approach a step further by

combining the logic blocks and interconnects of traditional FPGAs with embedded

microprocessors and related peripherals to form a complete "system on a programmable

chip". This work mirrors the architecture by Ron Perlof and Hana Potash of Burroughs

Advanced Systems Group which combined a reconfigurable CPU architecture on a single

chip called the SB24. That work was done in 1982. Examples of such hybrid technologies

can be found in the Xilinx Virtex-II PRO and Virtex-4 devices, which include one or more

PowerPC processors embedded within the FPGA's logic fabric. The Atmel FPSLIC is another

such device, which uses an AVR processor in combination with Atmel's programmable logic

architecture. The Actel SmartFusion devices incorporate an ARM architecture Cortex-M3

hard processor core (with up to 512kB of flash and 64kB of RAM) and analog peripherals

such as a multi-channel ADC and DACs to their flash-based FPGA fabric.

An alternate approach to using hard-macro processors is to make use of soft processor cores

that are implemented within the FPGA logic.

As previously mentioned, many modern FPGAs have the ability to be reprogrammed at "run

time," and this is leading to the idea of reconfigurable computing or reconfigurable systems

— CPUs that reconfigure themselves to suit the task at hand. The Mitrion Virtual Processor

from Mitrionics is an example of a reconfigurable soft processor, implemented on FPGAs.

However, it does not support dynamic reconfiguration at runtime, but instead adapts itself to

a specific program.

Additionally, new, non-FPGA architectures are beginning to emerge. Software-configurable

microprocessors such as the Stretch S5000 adopt a hybrid approach by providing an array of

processor cores and FPGA-like programmable cores on the same chip.

- 19 -

FPGA comparisons

Historically, FPGAs have been slower, less energy efficient and generally achieved less

functionality than their fixed ASIC counterparts. A combination of volume, fabrication

improvements, research and development, and the I/O capabilities of new supercomputers

have largely closed the performance gap between ASICs and FPGAs.

Advantages include the ability to re-program in the field to fix bugs, and may include a

shorter time to market and lower non-recurring engineering costs. Vendors can also take a

middle road by developing their hardware on ordinary FPGAs, but manufacture their final

version so it can no longer be modified after the design has been committed.

These trends make FPGAs a better alternative than ASICs for a larger number of higher-

volume applications than they have been historically used for, to which the company

attributes the growing number of FPGA design starts (see History).

Some FPGAs have the capability of partial re-configuration that lets one portion of the device

be re-programmed while other portions continue running.

Versus complex programmable logic devices

The primary differences between CPLDs and FPGAs are architectural. A CPLD has a

somewhat restrictive structure consisting of one or more programmable sum-of-products

logic arrays feeding a relatively small number of clocked registers. The result of this is less

flexibility, with the advantage of more predictable timing delays and a higher logic-to-

interconnect ratio. The FPGA architectures, on the other hand, are dominated by interconnect.

This makes them far more flexible (in terms of the range of designs that are practical for

implementation within them) but also far more complex to design for.

Another notable difference between CPLDs and FPGAs is the presence in most FPGAs of

higher-level embedded functions (such as adders and multipliers) and embedded memories,

as well as to have logic blocks implement decoders or mathematical functions.

- 20 -

Security considerations

With respect to security, FPGAs have both advantages and disadvantages as compared to

ASICs or secure microprocessors. FPGAs' flexibility makes malicious modifications during

fabrication a lower risk. For many FPGAs, the loaded design is exposed while it is loaded

(typically on every power-on). To address this issue, some FPGAs support bitstream

encryption.

Applications

Applications of FPGAs include digital signal processing, software-defined radio, aerospace

and defense systems, ASIC prototyping, medical imaging, computer vision, speech

recognition, cryptography, bioinformatics, computer hardware emulation, radio astronomy,

metal detection and a growing range of other areas.

FPGAs originally began as competitors to CPLDs and competed in a similar space, that of

glue logic for PCBs. As their size, capabilities, and speed increased, they began to take over

larger and larger functions to the state where some are now marketed as full systems on chips

(SoC). Particularly with the introduction of dedicated multipliers into FPGA architectures in

the late 1990s, applications, which had traditionally been the sole reserve of DSPs, began to

incorporate FPGAs instead.

FPGAs especially find applications in any area or algorithm that can make use of the

massive parallelism offered by their architecture. One such area is code breaking, in

particular brute-force attack, of cryptographic algorithms.

FPGAs are increasingly used in conventional high performance computing applications

where computational kernels such as FFT or Convolution are performed on the FPGA instead

of a microprocessor.

The inherent parallelism of the logic resources on an FPGA allows for considerable

computational throughput even at a low MHz clock rates. The flexibility of the FPGA allows

for even higher performance by trading off precision and range in the number format for an

increased number of parallel arithmetic units. This has driven a new type of processing called

reconfigurable computing, where time intensive tasks are offloaded from software to FPGAs.

- 21 -

The adoption of FPGAs in high performance computing is currently limited by the

complexity of FPGA design compared to conventional software and the turn-around times of

current design tools.

Traditionally, FPGAs have been reserved for specific vertical applications where the volume

of production is small. For these low-volume applications, the premium that companies pay

in hardware costs per unit for a programmable chip is more affordable than the development

resources spent on creating an ASIC for a low-volume application. Today, new cost and

performance dynamics have broadened the range of viable applications.

Architecture

The most common FPGA architecture consists of an array of logic blocks (called

Configurable Logic Block, CLB, or Logic Array Block, LAB, depending on vendor), I/O

pads, and routing channels. Generally, all the routing channels have the same width (number

of wires). Multiple I/O pads may fit into the height of one row or the width of one column in

the array.

An application circuit must be mapped into an FPGA with adequate resources. While the

number of CLBs/LABs and I/Os required is easily determined from the design, the number of

routing tracks needed may vary considerably even among designs with the same amount of

logic. For example, a crossbar switch requires much more routing than a systolic array with

the same gate count. Since unused routing tracks increase the cost (and decrease the

performance) of the part without providing any benefit, FPGA manufacturers try to provide

just enough tracks so that most designs that will fit in terms of LUTs and IOs can be routed.

This is determined by estimates such as those derived from Rent's rule or by experiments

with existing designs.

In general, a logic block (CLB or LAB) consists of a few logical cells (called ALM, LE, Slice

etc). A typical cell consists of a 4-input Lookup table (LUT), a Full adder (FA) and a D-type

flip-flop, as shown below. The LUT are in this figure split into two 3-input LUTs. In normal

mode those are combined into a 4-input LUT through the left mux. In arithmetic mode, their

outputs are fed to the FA. The selection of mode are programmed into the middle mux. The

output can be either synchronous or asynchronous, depending on the programming of the

- 22 -

mux to the right, in the figure example. In practice, entire or parts of the FA are put as

functions into the LUTs in order to save space.

Figure 9:Simplified example illustration of a logic cell

ALMs and Slices usually contain 2 or 4 structures similar to the example figure, with some

shared signals. CLBs/LABs typically contain a few ALMs/LEs/Slices. In recent years,

manufacturers have started moving to 6-input LUTs in their high performance parts, claiming

increased performance.

Since clock signals (and often other high-fanout signals) are normally routed via special-

purpose dedicated routing networks in commercial FPGAs, they and other signals are

separately managed.

For this example architecture, the locations of the FPGA logic block pins are shown below.

Figure 10:Logic Block Pin Locations

Each input is accessible from one side of the logic block, while the output pin can connect to

routing wires in both the channel to the right and the channel below the logic block.

- 23 -

Each logic block output pin can connect to any of the wiring segments in the channels

adjacent to it.

Similarly, an I/O pad can connect to any one of the wiring segments in the channel adjacent

to it. For example, an I/O pad at the top of the chip can connect to any of the W wires (where

W is the channel width) in the horizontal channel immediately below it.

Generally, the FPGA routing is unsegmented. That is, each wiring segment spans only one

logic block before it terminates in a switch box. By turning on some of the programmable

switches within a switch box, longer paths can be constructed. For higher speed interconnect,

some FPGA architectures use longer routing lines that span multiple logic blocks.

Whenever a vertical and a horizontal channel intersect, there is a switch box. In this

architecture, when a wire enters a switch box, there are three programmable switches that

allow it to connect to three other wires in adjacent channel segments. The pattern, or

topology, of switches used in this architecture is the planar or domain-based switch box

topology. In this switch box topology, a wire in track number one connects only to wires in

track number one in adjacent channel segments, wires in track number 2 connect only to

other wires in track number 2 and so on. The figure below illustrates the connections in a

switch box.

Figure 11: Switch box topology

- 24 -

Modern FPGA families expand upon the above capabilities to include higher level

functionality fixed into the silicon. Having these common functions embedded into the

silicon reduces the area required and gives those functions increased speed compared to

building them from primitives. Examples of these include multipliers, generic DSP blocks,

embedded processors, high speed IO logic and embedded memories.

FPGAs are also widely used for systems validation including pre-silicon validation, post-

silicon validation, and firmware development. This allows chip companies to validate their

design before the chip is produced in the factory, reducing the time-to-market.

FPGA design and programming

To define the behaviour of the FPGA, the user provides a hardware description language

(HDL) or a schematic design. The HDL form is more suited to work with large structures

because it's possible to just specify them numerically rather than having to draw every piece

by hand. However, schematic entry can allow for easier visualisation of a design.

Then, using an electronic design automation tool, a technology-mapped netlist is generated.

The netlist can then be fitted to the actual FPGA architecture using a process called place-

and-route, usually performed by the FPGA company's proprietary place-and-route software.

The user will validate the map, place and route results via timing analysis, simulation, and

other verification methodologies. Once the design and validation process is complete, the

binary file generated (also using the FPGA company's proprietary software) is used to

(re)configure the FPGA.

Schematic/HDL source files to actual configuration:

The source files are fed to a software suite from the FPGA/CPLD vendor that through

different steps will produce a file. This file is then transferred to the FPGA/CPLD via a serial

interface (JTAG) or to an external memory device like an EEPROM.

The most common HDLs are VHDL and Verilog, although in an attempt to reduce the

complexity of designing in HDLs, which have been compared to the equivalent of assembly

languages, there are moves to raise the abstraction level through the introduction of

alternative languages.

- 25 -

To simplify the design of complex systems in FPGAs, there exist libraries of predefined

complex functions and circuits that have been tested and optimized to speed up the design

process. These predefined circuits are commonly called IP cores, and are available from

FPGA vendors and third-party IP suppliers (rarely free, and typically released under

proprietary licenses). Other predefined circuits are available from developer communities

such as OpenCores (typically released under free and open source licenses such as the GPL,

BSD or similar license), and other sources.

In a typical design flow, an FPGA application developer will simulate the design at multiple

stages throughout the design process. Initially the RTL description in VHDL or Verilog is

simulated by creating test benches to simulate the system and observe results. Then, after the

synthesis engine has mapped the design to a netlist, the netlist is translated to a gate level

description where simulation is repeated to confirm the synthesis proceeded without errors.

Finally the design is laid out in the FPGA at which point propagation delays can be added

and the simulation run again with these values back-annotated onto the netlist.

Basic process technology types

SRAM - based on static memory technology. In-system programmable and re-

programmable. Requires external boot devices. CMOS.

Antifuse - One-time programmable. CMOS.

PROM - Programmable Read-Only Memory technology. One-time programmable

because of plastic packaging.

EPROM - Erasable Programmable Read-Only Memory technology. One-time

programmable but with window, can be erased with ultraviolet (UV) light. CMOS.

EEPROM - Electrically Erasable Programmable Read-Only Memory technology. Can

be erased, even in plastic packages. Some but not all EEPROM devices can be in-

system programmed. CMOS.

Flash - Flash-erase EPROM technology. Can be erased, even in plastic packages.

Some but not all flash devices can be in-system programmed. Usually, a flash cell is

smaller than an equivalent EEPROM cell and is therefore less expensive to

manufacture. CMOS.

Fuse - One-time programmable. Bipolar.

- 26 -

3.2.5 Actel ProASICPLUS Evaluation Board

PROASIC PLUS FPGA APA300 The VHDL code for DDS was implemented using ProASIC PLUS APA300 FPGA. The

layout was done using ACTEL LIBERO IDE and the program was fused using FlashPro Lite

programmer.

The ProASIC PLUS device core consists of a Sea-of-Tiles. Each tile can be configured as a

three-input logic function (e.g., NAND gate, D-Flip-Flop, etc.) by programming the

appropriate flash switch interconnections. Tiles and larger functions are connected with any

of the four levels of routing hierarchy. Flash switches are distributed throughout the device to

provide non-volatile, reconfigurable interconnect programming. Flash switches are

programmed to connect signal lines to the appropriate logic cell inputs and outputs. ProASIC

PLUS devices also contain embedded, two-port SRAM blocks with built-in FIFO/RAM

control logic. Programming options include synchronous or asynchronous operation, two-port

RAM configurations, user-defined depth and width, and parity generation or checking.

To test the evaluation board:

1. Connect the power supply to the board.

2. Turn on the ON/OFF switch.

3. Perform the actions described in the following table

Action Result Pass/Fail

Press PB1 multiple times, but

not too quickly

Count sequence should be

visible on the LEDs

Pass

Press and hold SW1 All LEDs are unlit Pass

Press and hold SW2 All LEDs are lit Pass

Press and hold SW3 Count sequence runs while

you hold the switch

Pass

Press and hold SW4 LED is lit/unlit alternately in

a 10101010 pattern

Pass

Press any two switches

simultaneously

Creates a 00110011 pattern

Pass

- 27 -

To setup FlashPro Lite:

1. From the File menu, click Connect.

2. In the Port list, select the port the FlashPro programmer is connected to.

3. In the Configuration list, select ProASIC PLUS.

4. (Optional) Disable voltages from the programmer if they are available on the board.

5. Click Connect. A successful connect, or any errors, will appear in the Log window.

The Setup looks as follows:

- 28 -

3.3 Design

3.3.1 DDS The output frequency of a DDS system can be expressed by

푓 = Δ휑 × 푓2

,

usually called tuning equation, where Δφ is the phase increment value of the accumulator, clk

is the system clock frequency and N is the accumulator resolution.

For the system that is to be implemented, the clock frequency is 40 MHz. A 40 MHz clock

was selected due to the higher spectral purity it provides compared to a 10 MHz oscillator.

The required output frequency of the DDS for our application (a digital radar receiver) is 2.5

MHz. This is the frequency of the signal transmitted by the radar. We have selected N as 10

for good accuracy. Higher values may be selected to improve the accuracy; however this will

cause the look up table size to increase exponentially.

For these set of values, we calculated the phase increment Δφ using he tuning equation given

above. Δφ was obtained to be 64.

3.3.2 Digital Multiplier

A digital multiplier was implemented to multiply the incoming Doppler shifted received

signal (frec) and the 2.5 MHz wave (fo) generated by the DDS. The digital multiplier output

contains both frec + fo and frec - fo.

3.3.3 FIR filter design

We require only the difference signal (frec - fo). The sum signal (frec + fo) is filtered away

using an FIR filter. The filter design was done using fdatool in MATLAB. A sampling

frequency of 4MHz was used. Based on the required bandwidth, pass and stop band

attenuation, and number of taps of the filter the pass and stop band cut-off frequencies have

been kept at 80 kHz and 500 kHz respectively.

3.3.4 Decimator

The output signal of the FIR filter is in the range of a few Hertz. However, the sampling rate

is in the order of Megahertz. We do not require these many samples. So we employ a

decimation filter to down sample the output.

- 29 -

3.4 Codes

3.4.1 MATLAB Codes

The following MATLAB codes were used for simulating the DDC and verifying the design.

3.4.1.1 Code for DDC clear all clc %dds r=50; fs=40e6; %sampling frequency t=linspace(0,r*1023/fs,r*1024); x=sin(2*pi*fs*t/1024); n=64; figure(1); plot(t,x) t1=t(1:r*1024/n); y=x(1:n:r*1024); figure(2); plot(t1,y,t1,x(1:r*1024/n)) L=length(y);NFFT = 2^nextpow2(L); Y = fft(y,NFFT)/L; f = fs/2*linspace(0,1,NFFT/2); figure; plot(f,2*abs(Y(1:NFFT/2))) title('Single-Sided Amplitude Spectrum of y(t) after dds. fc = 40 MHz') xlabel('Frequency (Hz)') ylabel('|Y(f)|') %multiplier in=sin(2*pi*(2.5e6+10)*t1); figure; plot(t1,in,t1,y) mul=in.*y; figure; plot(t1,mul) L=length(mul);NFFT = 2^nextpow2(L); Y = fft(mul,NFFT)/L; f = fs/2*linspace(0,1,NFFT/2); figure plot(f,2*abs(Y(1:NFFT/2))) title('Single-Sided Amplitude Spectrum of mul(t) after multiplier') xlabel('Frequency (Hz)') ylabel('|Y(f)|') %filter fir=fir_iist2; fout=filter(fir,1,mul); L=length(fout);NFFT = 2^nextpow2(L); Y = fft(fout,NFFT)/L; f = fs/2*linspace(0,1,NFFT/2); figure plot(f,2*abs(Y(1:NFFT/2))) title('Single-Sided Amplitude Spectrum of fout(t) after filter') xlabel('Frequency (Hz)') ylabel('|Y(f)|') %decimator M=2; d=fout(1:M:length(fout)); L=length(d);NFFT = 2^nextpow2(L);

- 30 -

Y = fft(d,NFFT)/L; f = fs/2*linspace(0,1,NFFT/2); figure; plot(f,2*abs(Y(1:NFFT/2))) title('Single-Sided Amplitude Spectrum of d(t) after decimator') xlabel('Frequency (Hz)') ylabel('|Y(f)|')

3.4.1.2 Code for FIR filter function b=fir_iist2 %all freq in kHz Fs=4000; N=15; fp=80; fs=500; wp=1; ws=100; dens=20; b=firpm(N, [0 fp fs Fs/2]/(Fs/2), [1 1 0 0], [wp ws], {dens});

3.4.2 VHDL Codes

3.4.2.1 Code for DDS --DIRECT DIGITAL SYNTHESIS (DDS) --------------------------------- --Design Parameters:- --CLK = 40.0 MHz --O/P Frequency = 2.5 MHz library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity dds_final is port ( clk : in std_logic; rst : in std_logic; tune : in std_logic_vector(7 downto 0); sinee : out std_logic_vector(8 downto 0) ); end dds_final; architecture behavior of dds_final is signal address : std_logic_vector(9 downto 0); --ROM ( 1024 X 9 b ) LUT type rom is array(0 to 1023) of std_logic_vector(8 downto 0); constant mem : rom :=( 0 => "001100100", 1 => "001100100", 2 => "001100101",

- 31 -

3 => "001100101", 4 => "001100110", 5 => "001100111", 6 => "001100111", 7 => "001101000", 8 => "001101000", 9 => "001101001", 10 => "001101010", 11 => "001101010", 12 => "001101011", 13 => "001101011", 14 => "001101100", 15 => "001101101", 16 => "001101101", 17 => "001101110", 18 => "001101111", 19 => "001101111", 20 => "001110000", 21 => "001110000", 22 => "001110001", 23 => "001110010", 24 => "001110010", 25 => "001110011", 26 => "001110011", 27 => "001110100", 28 => "001110101", 29 => "001110101", 30 => "001110110", 31 => "001110110", 32 => "001110111", 33 => "001111000", 34 => "001111000", 35 => "001111001", 36 => "001111001", 37 => "001111010", 38 => "001111011", 39 => "001111011", 40 => "001111100", 41 => "001111100", 42 => "001111101", 43 => "001111110", 44 => "001111110", 45 => "001111111", 46 => "001111111", 47 => "010000000", 48 => "010000001", 49 => "010000001", 50 => "010000010", 51 => "010000010", 52 => "010000011", 53 => "010000011", 54 => "010000100", 55 => "010000101", 56 => "010000101",

- 32 -

57 => "010000110", 58 => "010000110", 59 => "010000111", 60 => "010001000", 61 => "010001000", 62 => "010001001", 63 => "010001001", 64 => "010001010", 65 => "010001010", 66 => "010001011", 67 => "010001011", 68 => "010001100", 69 => "010001101", 70 => "010001101", 71 => "010001110", 72 => "010001110", 73 => "010001111", 74 => "010001111", 75 => "010010000", 76 => "010010001", 77 => "010010001", 78 => "010010010", 79 => "010010010", 80 => "010010011", 81 => "010010011", 82 => "010010100", 83 => "010010100", 84 => "010010101", 85 => "010010101", 86 => "010010110", 87 => "010010110", 88 => "010010111", 89 => "010010111", 90 => "010011000", 91 => "010011001", 92 => "010011001", 93 => "010011010", 94 => "010011010", 95 => "010011011", 96 => "010011011", 97 => "010011100", 98 => "010011100", 99 => "010011101", 100 => "010011101", 101 => "010011110", 102 => "010011110", 103 => "010011111", 104 => "010011111", 105 => "010100000", 106 => "010100000", 107 => "010100001", 108 => "010100001", 109 => "010100010", 110 => "010100010",

- 33 -

111 => "010100011", 112 => "010100011", 113 => "010100011", 114 => "010100100", 115 => "010100100", 116 => "010100101", 117 => "010100101", 118 => "010100110", 119 => "010100110", 120 => "010100111", 121 => "010100111", 122 => "010101000", 123 => "010101000", 124 => "010101001", 125 => "010101001", 126 => "010101001", 127 => "010101010", 128 => "010101010", 129 => "010101011", 130 => "010101011", 131 => "010101100", 132 => "010101100", 133 => "010101100", 134 => "010101101", 135 => "010101101", 136 => "010101110", 137 => "010101110", 138 => "010101110", 139 => "010101111", 140 => "010101111", 141 => "010110000", 142 => "010110000", 143 => "010110000", 144 => "010110001", 145 => "010110001", 146 => "010110010", 147 => "010110010", 148 => "010110010", 149 => "010110011", 150 => "010110011", 151 => "010110100", 152 => "010110100", 153 => "010110100", 154 => "010110101", 155 => "010110101", 156 => "010110101", 157 => "010110110", 158 => "010110110", 159 => "010110110", 160 => "010110111", 161 => "010110111", 162 => "010110111", 163 => "010111000", 164 => "010111000",

- 34 -

165 => "010111000", 166 => "010111001", 167 => "010111001", 168 => "010111001", 169 => "010111010", 170 => "010111010", 171 => "010111010", 172 => "010111011", 173 => "010111011", 174 => "010111011", 175 => "010111011", 176 => "010111100", 177 => "010111100", 178 => "010111100", 179 => "010111101", 180 => "010111101", 181 => "010111101", 182 => "010111101", 183 => "010111110", 184 => "010111110", 185 => "010111110", 186 => "010111110", 187 => "010111111", 188 => "010111111", 189 => "010111111", 190 => "010111111", 191 => "011000000", 192 => "011000000", 193 => "011000000", 194 => "011000000", 195 => "011000001", 196 => "011000001", 197 => "011000001", 198 => "011000001", 199 => "011000001", 200 => "011000010", 201 => "011000010", 202 => "011000010", 203 => "011000010", 204 => "011000010", 205 => "011000011", 206 => "011000011", 207 => "011000011", 208 => "011000011", 209 => "011000011", 210 => "011000100", 211 => "011000100", 212 => "011000100", 213 => "011000100", 214 => "011000100", 215 => "011000100", 216 => "011000101", 217 => "011000101", 218 => "011000101",

- 35 -

219 => "011000101", 220 => "011000101", 221 => "011000101", 222 => "011000101", 223 => "011000101", 224 => "011000110", 225 => "011000110", 226 => "011000110", 227 => "011000110", 228 => "011000110", 229 => "011000110", 230 => "011000110", 231 => "011000110", 232 => "011000110", 233 => "011000111", 234 => "011000111", 235 => "011000111", 236 => "011000111", 237 => "011000111", 238 => "011000111", 239 => "011000111", 240 => "011000111", 241 => "011000111", 242 => "011000111", 243 => "011000111", 244 => "011000111", 245 => "011000111", 246 => "011000111", 247 => "011000111", 248 => "011000111", 249 => "011000111", 250 => "011000111", 251 => "011000111", 252 => "011000111", 253 => "011000111", 254 => "011000111", 255 => "011000111", 256 => "011000111", 257 => "011000111", 258 => "011000111", 259 => "011000111", 260 => "011000111", 261 => "011000111", 262 => "011000111", 263 => "011000111", 264 => "011000111", 265 => "011000111", 266 => "011000111", 267 => "011000111", 268 => "011000111", 269 => "011000111", 270 => "011000111", 271 => "011000111", 272 => "011000111",

- 36 -

273 => "011000111", 274 => "011000111", 275 => "011000111", 276 => "011000111", 277 => "011000111", 278 => "011000111", 279 => "011000110", 280 => "011000110", 281 => "011000110", 282 => "011000110", 283 => "011000110", 284 => "011000110", 285 => "011000110", 286 => "011000110", 287 => "011000110", 288 => "011000110", 289 => "011000101", 290 => "011000101", 291 => "011000101", 292 => "011000101", 293 => "011000101", 294 => "011000101", 295 => "011000101", 296 => "011000100", 297 => "011000100", 298 => "011000100", 299 => "011000100", 300 => "011000100", 301 => "011000100", 302 => "011000011", 303 => "011000011", 304 => "011000011", 305 => "011000011", 306 => "011000011", 307 => "011000011", 308 => "011000010", 309 => "011000010", 310 => "011000010", 311 => "011000010", 312 => "011000010", 313 => "011000001", 314 => "011000001", 315 => "011000001", 316 => "011000001", 317 => "011000001", 318 => "011000000", 319 => "011000000", 320 => "011000000", 321 => "011000000", 322 => "010111111", 323 => "010111111", 324 => "010111111", 325 => "010111111", 326 => "010111110",

- 37 -

327 => "010111110", 328 => "010111110", 329 => "010111110", 330 => "010111101", 331 => "010111101", 332 => "010111101", 333 => "010111100", 334 => "010111100", 335 => "010111100", 336 => "010111100", 337 => "010111011", 338 => "010111011", 339 => "010111011", 340 => "010111010", 341 => "010111010", 342 => "010111010", 343 => "010111001", 344 => "010111001", 345 => "010111001", 346 => "010111001", 347 => "010111000", 348 => "010111000", 349 => "010111000", 350 => "010110111", 351 => "010110111", 352 => "010110111", 353 => "010110110", 354 => "010110110", 355 => "010110101", 356 => "010110101", 357 => "010110101", 358 => "010110100", 359 => "010110100", 360 => "010110100", 361 => "010110011", 362 => "010110011", 363 => "010110011", 364 => "010110010", 365 => "010110010", 366 => "010110001", 367 => "010110001", 368 => "010110001", 369 => "010110000", 370 => "010110000", 371 => "010101111", 372 => "010101111", 373 => "010101111", 374 => "010101110", 375 => "010101110", 376 => "010101101", 377 => "010101101", 378 => "010101101", 379 => "010101100", 380 => "010101100",

- 38 -

381 => "010101011", 382 => "010101011", 383 => "010101010", 384 => "010101010", 385 => "010101010", 386 => "010101001", 387 => "010101001", 388 => "010101000", 389 => "010101000", 390 => "010100111", 391 => "010100111", 392 => "010100110", 393 => "010100110", 394 => "010100110", 395 => "010100101", 396 => "010100101", 397 => "010100100", 398 => "010100100", 399 => "010100011", 400 => "010100011", 401 => "010100010", 402 => "010100010", 403 => "010100001", 404 => "010100001", 405 => "010100000", 406 => "010100000", 407 => "010011111", 408 => "010011111", 409 => "010011110", 410 => "010011110", 411 => "010011101", 412 => "010011101", 413 => "010011100", 414 => "010011100", 415 => "010011011", 416 => "010011011", 417 => "010011010", 418 => "010011010", 419 => "010011001", 420 => "010011001", 421 => "010011000", 422 => "010011000", 423 => "010010111", 424 => "010010111", 425 => "010010110", 426 => "010010110", 427 => "010010101", 428 => "010010101", 429 => "010010100", 430 => "010010011", 431 => "010010011", 432 => "010010010", 433 => "010010010", 434 => "010010001",

- 39 -

435 => "010010001", 436 => "010010000", 437 => "010010000", 438 => "010001111", 439 => "010001111", 440 => "010001110", 441 => "010001101", 442 => "010001101", 443 => "010001100", 444 => "010001100", 445 => "010001011", 446 => "010001011", 447 => "010001010", 448 => "010001010", 449 => "010001001", 450 => "010001000", 451 => "010001000", 452 => "010000111", 453 => "010000111", 454 => "010000110", 455 => "010000110", 456 => "010000101", 457 => "010000100", 458 => "010000100", 459 => "010000011", 460 => "010000011", 461 => "010000010", 462 => "010000001", 463 => "010000001", 464 => "010000000", 465 => "010000000", 466 => "001111111", 467 => "001111110", 468 => "001111110", 469 => "001111101", 470 => "001111101", 471 => "001111100", 472 => "001111100", 473 => "001111011", 474 => "001111010", 475 => "001111010", 476 => "001111001", 477 => "001111001", 478 => "001111000", 479 => "001110111", 480 => "001110111", 481 => "001110110", 482 => "001110110", 483 => "001110101", 484 => "001110100", 485 => "001110100", 486 => "001110011", 487 => "001110010", 488 => "001110010",

- 40 -

489 => "001110001", 490 => "001110001", 491 => "001110000", 492 => "001101111", 493 => "001101111", 494 => "001101110", 495 => "001101110", 496 => "001101101", 497 => "001101100", 498 => "001101100", 499 => "001101011", 500 => "001101011", 501 => "001101010", 502 => "001101001", 503 => "001101001", 504 => "001101000", 505 => "001100111", 506 => "001100111", 507 => "001100110", 508 => "001100110", 509 => "001100101", 510 => "001100100", 511 => "001100100", 512 => "001100011", 513 => "001100011", 514 => "001100010", 515 => "001100001", 516 => "001100001", 517 => "001100000", 518 => "001100000", 519 => "001011111", 520 => "001011110", 521 => "001011110", 522 => "001011101", 523 => "001011100", 524 => "001011100", 525 => "001011011", 526 => "001011011", 527 => "001011010", 528 => "001011001", 529 => "001011001", 530 => "001011000", 531 => "001011000", 532 => "001010111", 533 => "001010110", 534 => "001010110", 535 => "001010101", 536 => "001010101", 537 => "001010100", 538 => "001010011", 539 => "001010011", 540 => "001010010", 541 => "001010001", 542 => "001010001",

- 41 -

543 => "001010000", 544 => "001010000", 545 => "001001111", 546 => "001001110", 547 => "001001110", 548 => "001001101", 549 => "001001101", 550 => "001001100", 551 => "001001011", 552 => "001001011", 553 => "001001010", 554 => "001001010", 555 => "001001001", 556 => "001001001", 557 => "001001000", 558 => "001000111", 559 => "001000111", 560 => "001000110", 561 => "001000110", 562 => "001000101", 563 => "001000100", 564 => "001000100", 565 => "001000011", 566 => "001000011", 567 => "001000010", 568 => "001000001", 569 => "001000001", 570 => "001000000", 571 => "001000000", 572 => "000111111", 573 => "000111111", 574 => "000111110", 575 => "000111101", 576 => "000111101", 577 => "000111100", 578 => "000111100", 579 => "000111011", 580 => "000111011", 581 => "000111010", 582 => "000111010", 583 => "000111001", 584 => "000111000", 585 => "000111000", 586 => "000110111", 587 => "000110111", 588 => "000110110", 589 => "000110110", 590 => "000110101", 591 => "000110101", 592 => "000110100", 593 => "000110100", 594 => "000110011", 595 => "000110010", 596 => "000110010",

- 42 -

597 => "000110001", 598 => "000110001", 599 => "000110000", 600 => "000110000", 601 => "000101111", 602 => "000101111", 603 => "000101110", 604 => "000101110", 605 => "000101101", 606 => "000101101", 607 => "000101100", 608 => "000101100", 609 => "000101011", 610 => "000101011", 611 => "000101010", 612 => "000101010", 613 => "000101001", 614 => "000101001", 615 => "000101000", 616 => "000101000", 617 => "000100111", 618 => "000100111", 619 => "000100110", 620 => "000100110", 621 => "000100101", 622 => "000100101", 623 => "000100100", 624 => "000100100", 625 => "000100011", 626 => "000100011", 627 => "000100010", 628 => "000100010", 629 => "000100001", 630 => "000100001", 631 => "000100001", 632 => "000100000", 633 => "000100000", 634 => "000011111", 635 => "000011111", 636 => "000011110", 637 => "000011110", 638 => "000011101", 639 => "000011101", 640 => "000011101", 641 => "000011100", 642 => "000011100", 643 => "000011011", 644 => "000011011", 645 => "000011010", 646 => "000011010", 647 => "000011010", 648 => "000011001", 649 => "000011001", 650 => "000011000",

- 43 -

651 => "000011000", 652 => "000011000", 653 => "000010111", 654 => "000010111", 655 => "000010110", 656 => "000010110", 657 => "000010110", 658 => "000010101", 659 => "000010101", 660 => "000010100", 661 => "000010100", 662 => "000010100", 663 => "000010011", 664 => "000010011", 665 => "000010011", 666 => "000010010", 667 => "000010010", 668 => "000010010", 669 => "000010001", 670 => "000010001", 671 => "000010000", 672 => "000010000", 673 => "000010000", 674 => "000001111", 675 => "000001111", 676 => "000001111", 677 => "000001110", 678 => "000001110", 679 => "000001110", 680 => "000001110", 681 => "000001101", 682 => "000001101", 683 => "000001101", 684 => "000001100", 685 => "000001100", 686 => "000001100", 687 => "000001011", 688 => "000001011", 689 => "000001011", 690 => "000001011", 691 => "000001010", 692 => "000001010", 693 => "000001010", 694 => "000001001", 695 => "000001001", 696 => "000001001", 697 => "000001001", 698 => "000001000", 699 => "000001000", 700 => "000001000", 701 => "000001000", 702 => "000000111", 703 => "000000111", 704 => "000000111",

- 44 -

705 => "000000111", 706 => "000000110", 707 => "000000110", 708 => "000000110", 709 => "000000110", 710 => "000000110", 711 => "000000101", 712 => "000000101", 713 => "000000101", 714 => "000000101", 715 => "000000101", 716 => "000000100", 717 => "000000100", 718 => "000000100", 719 => "000000100", 720 => "000000100", 721 => "000000100", 722 => "000000011", 723 => "000000011", 724 => "000000011", 725 => "000000011", 726 => "000000011", 727 => "000000011", 728 => "000000010", 729 => "000000010", 730 => "000000010", 731 => "000000010", 732 => "000000010", 733 => "000000010", 734 => "000000010", 735 => "000000001", 736 => "000000001", 737 => "000000001", 738 => "000000001", 739 => "000000001", 740 => "000000001", 741 => "000000001", 742 => "000000001", 743 => "000000001", 744 => "000000001", 745 => "000000000", 746 => "000000000", 747 => "000000000", 748 => "000000000", 749 => "000000000", 750 => "000000000", 751 => "000000000", 752 => "000000000", 753 => "000000000", 754 => "000000000", 755 => "000000000", 756 => "000000000", 757 => "000000000", 758 => "000000000",

- 45 -

759 => "000000000", 760 => "000000000", 761 => "000000000", 762 => "000000000", 763 => "000000000", 764 => "000000000", 765 => "000000000", 766 => "000000000", 767 => "000000000", 768 => "000000000", 769 => "000000000", 770 => "000000000", 771 => "000000000", 772 => "000000000", 773 => "000000000", 774 => "000000000", 775 => "000000000", 776 => "000000000", 777 => "000000000", 778 => "000000000", 779 => "000000000", 780 => "000000000", 781 => "000000000", 782 => "000000000", 783 => "000000000", 784 => "000000000", 785 => "000000000", 786 => "000000000", 787 => "000000000", 788 => "000000000", 789 => "000000000", 790 => "000000000", 791 => "000000001", 792 => "000000001", 793 => "000000001", 794 => "000000001", 795 => "000000001", 796 => "000000001", 797 => "000000001", 798 => "000000001", 799 => "000000001", 800 => "000000010", 801 => "000000010", 802 => "000000010", 803 => "000000010", 804 => "000000010", 805 => "000000010", 806 => "000000010", 807 => "000000010", 808 => "000000011", 809 => "000000011", 810 => "000000011", 811 => "000000011", 812 => "000000011",

- 46 -

813 => "000000011", 814 => "000000100", 815 => "000000100", 816 => "000000100", 817 => "000000100", 818 => "000000100", 819 => "000000101", 820 => "000000101", 821 => "000000101", 822 => "000000101", 823 => "000000101", 824 => "000000110", 825 => "000000110", 826 => "000000110", 827 => "000000110", 828 => "000000110", 829 => "000000111", 830 => "000000111", 831 => "000000111", 832 => "000000111", 833 => "000001000", 834 => "000001000", 835 => "000001000", 836 => "000001000", 837 => "000001001", 838 => "000001001", 839 => "000001001", 840 => "000001001", 841 => "000001010", 842 => "000001010", 843 => "000001010", 844 => "000001010", 845 => "000001011", 846 => "000001011", 847 => "000001011", 848 => "000001100", 849 => "000001100", 850 => "000001100", 851 => "000001100", 852 => "000001101", 853 => "000001101", 854 => "000001101", 855 => "000001110", 856 => "000001110", 857 => "000001110", 858 => "000001111", 859 => "000001111", 860 => "000001111", 861 => "000010000", 862 => "000010000", 863 => "000010000", 864 => "000010001", 865 => "000010001", 866 => "000010001",

- 47 -

867 => "000010010", 868 => "000010010", 869 => "000010010", 870 => "000010011", 871 => "000010011", 872 => "000010011", 873 => "000010100", 874 => "000010100", 875 => "000010101", 876 => "000010101", 877 => "000010101", 878 => "000010110", 879 => "000010110", 880 => "000010111", 881 => "000010111", 882 => "000010111", 883 => "000011000", 884 => "000011000", 885 => "000011001", 886 => "000011001", 887 => "000011001", 888 => "000011010", 889 => "000011010", 890 => "000011011", 891 => "000011011", 892 => "000011011", 893 => "000011100", 894 => "000011100", 895 => "000011101", 896 => "000011101", 897 => "000011110", 898 => "000011110", 899 => "000011110", 900 => "000011111", 901 => "000011111", 902 => "000100000", 903 => "000100000", 904 => "000100001", 905 => "000100001", 906 => "000100010", 907 => "000100010", 908 => "000100011", 909 => "000100011", 910 => "000100100", 911 => "000100100", 912 => "000100100", 913 => "000100101", 914 => "000100101", 915 => "000100110", 916 => "000100110", 917 => "000100111", 918 => "000100111", 919 => "000101000", 920 => "000101000",

- 48 -

921 => "000101001", 922 => "000101001", 923 => "000101010", 924 => "000101010", 925 => "000101011", 926 => "000101011", 927 => "000101100", 928 => "000101100", 929 => "000101101", 930 => "000101101", 931 => "000101110", 932 => "000101110", 933 => "000101111", 934 => "000110000", 935 => "000110000", 936 => "000110001", 937 => "000110001", 938 => "000110010", 939 => "000110010", 940 => "000110011", 941 => "000110011", 942 => "000110100", 943 => "000110100", 944 => "000110101", 945 => "000110101", 946 => "000110110", 947 => "000110110", 948 => "000110111", 949 => "000111000", 950 => "000111000", 951 => "000111001", 952 => "000111001", 953 => "000111010", 954 => "000111010", 955 => "000111011", 956 => "000111100", 957 => "000111100", 958 => "000111101", 959 => "000111101", 960 => "000111110", 961 => "000111110", 962 => "000111111", 963 => "000111111", 964 => "001000000", 965 => "001000001", 966 => "001000001", 967 => "001000010", 968 => "001000010", 969 => "001000011", 970 => "001000100", 971 => "001000100", 972 => "001000101", 973 => "001000101", 974 => "001000110",

- 49 -

975 => "001000110", 976 => "001000111", 977 => "001001000", 978 => "001001000", 979 => "001001001", 980 => "001001001", 981 => "001001010", 982 => "001001011", 983 => "001001011", 984 => "001001100", 985 => "001001100", 986 => "001001101", 987 => "001001110", 988 => "001001110", 989 => "001001111", 990 => "001001111", 991 => "001010000", 992 => "001010001", 993 => "001010001", 994 => "001010010", 995 => "001010010", 996 => "001010011", 997 => "001010100", 998 => "001010100", 999 => "001010101", 1000 => "001010101", 1001 => "001010110", 1002 => "001010111", 1003 => "001010111", 1004 => "001011000", 1005 => "001011000", 1006 => "001011001", 1007 => "001011010", 1008 => "001011010", 1009 => "001011011", 1010 => "001011100", 1011 => "001011100", 1012 => "001011101", 1013 => "001011101", 1014 => "001011110", 1015 => "001011111", 1016 => "001011111", 1017 => "001100000", 1018 => "001100000", 1019 => "001100001", 1020 => "001100010", 1021 => "001100010", 1022 => "001100011", 1023 => "001100011", others => "000000000"); begin process(rst,clk)

- 50 -

begin if (rst='1') then address <= "0000000000"; sinee <= "000000000"; elsif rising_edge(clk) then address <= (address) + (tune); sinee <= mem(conv_integer(address)); end if; end process; end behavior;

3.4.2.2 Test bench for DDS --TEST-BENCH FOR DDS --------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity dds_tb is end dds_tb; architecture structure of dds_tb is component dds_final is port ( clk : in std_logic; rst : in std_logic; tune : in std_logic_vector(7 downto 0); sinee : out std_logic_vector(8 downto 0) ); end component; signal tune : std_logic_vector(7 downto 0); signal sinee : std_logic_vector(8 downto 0); signal clk, rst : std_logic ; begin u1 : dds_final port map ( clk=>clk, rst=>rst, tune=>tune, sinee=>sinee );

tune <= "01000000"; process begin clk <= '0'; wait for 500 ns; loop clk <= '1', '0' after 500 ns; wait for 1000 ns; end loop; end process; rst <= '1','0' after 1 us; end structure;

- 51 -

3.4.2.3 Code for FIR filter -------------------------------------------------------

--FIR FILTER IMPLEMENTATION ---------------------------- --fc = 80 KHz , 16 - Tap library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_signed.all; entity fir_filter is --Define the Entity Port ( clk, reset : in std_logic; xin : in std_logic_vector(18 downto 0); yout : out std_logic_vector(29 downto 0)); end fir_filter; architecture Behavioral of fir_filter is signal y1,y2,y3,y4,y5,y6,y7,y8 : std_logic_vector(28 downto 0); signal s1,s2,s3,s4,s5,s6,s7,s8 : std_logic_vector(18 downto 0); signal r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15 : std_logic_vector(18 downto 0); --Shift Registers signal q : std_logic_vector(29 downto 0); --Coefficients of FIR filter constant h0 : std_logic_vector(9 downto 0) := "0000001000"; constant h1 : std_logic_vector(9 downto 0) := "0000001101"; constant h2 : std_logic_vector(9 downto 0) := "0000011010"; constant h3 : std_logic_vector(9 downto 0) := "0000101110"; constant h4 : std_logic_vector(9 downto 0) := "0001000111"; constant h5 : std_logic_vector(9 downto 0) := "0001011111"; constant h6 : std_logic_vector(9 downto 0) := "0001110011"; constant h7 : std_logic_vector(9 downto 0) := "0001111110"; begin process(clk) begin if (reset = '1') then r0 <= "0000000000000000000"; r1 <= "0000000000000000000"; r2 <= "0000000000000000000"; r3 <= "0000000000000000000"; r4 <= "0000000000000000000"; r5 <= "0000000000000000000"; r6 <= "0000000000000000000"; r7 <= "0000000000000000000"; r8 <= "0000000000000000000"; r9 <= "0000000000000000000";

- 52 -

r10 <= "0000000000000000000"; r11 <= "0000000000000000000"; r12 <= "0000000000000000000"; r13 <= "0000000000000000000"; r14 <= "0000000000000000000"; r15 <= "0000000000000000000"; elsif (clk'event and clk = '1') then r0 <= xin; r1 <= r0; r2 <= r1; r3 <= r2; r4 <= r3; r5 <= r4; r6 <= r5; r7 <= r6; r8 <= r7; r9 <= r8; r10 <= r9; r11 <= r10; r12 <= r11; r13 <= r12; r14 <= r13; r15 <= r14; end if; end process; process(clk) begin if (clk'event and clk = '1') then s1 <= signed(r0) + signed(r15); s2 <= signed(r1) + signed(r14); s3 <= signed(r2) + signed(r13); s4 <= signed(r3) + signed(r12); s5 <= signed(r4) + signed(r11); s6 <= signed(r5) + signed(r10); s7 <= signed(r6) + signed(r9); s8 <= signed(r7) + signed(r8); end if; end process; process(clk) begin if (clk'event and clk = '1') then y1 <= signed(s1) * signed(h0); y2 <= signed(s2) * signed(h1); y3 <= signed(s3) * signed(h2); y4 <= signed(s4) * signed(h3); y5 <= signed(s5) * signed(h4); y6 <= signed(s6) * signed(h5); y7 <= signed(s7) * signed(h6); y8 <= signed(s8) * signed(h7);

- 53 -

q <= '0'&(signed(y1) + signed(y2) + signed(y3) + signed(y4) + signed(y5) + signed(y6) + signed(y7) + signed(y8)); end if; end process; yout <= q; end Behavioral;

3.4.2.4 Test Bench for FIR filter ------------------------ --FIR FILTER TEST-BENCH ------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_signed.all; entity fir_tb is end fir_tb; architecture structure of fir_tb is component fir_filter is Port ( clk, reset : in std_logic; xin : in std_logic_vector(9 downto 0); yout : out std_logic_vector(21 downto 0)); end component; signal xin : std_logic_vector(9 downto 0) := "0000000000"; signal yout : std_logic_vector(21 downto 0); signal rset : std_logic ; signal clkk : std_logic := '0' ; constant period1 : TIME := 100 ns; --CLK constant period2 : TIME := 5000 ns; --I/P Square wave begin u1 : fir_filter port map ( clkk, rset, xin, yout ); rset <= '1', '0' after 200 ns; process (clkk) begin clkk <= not clkk after period1/2; end process; process (xin) begin xin <= not xin after period2/2; end process; end structure;

- 54 -

3.4.2.5 Code for Decimator ------------ --DECIMATOR ------------ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_signed.all; entity decimator is Port ( clk, reset : in std_logic; xin : in std_logic_vector(29 downto 0); yout : out std_logic_vector(29 downto 0)); end decimator; architecture Behavioral of decimator is signal count : std_logic_vector(2 downto 0); begin process(reset,clk) begin if (reset = '1') then count <= "000"; yout <= "000000000000000000000000000000"; elsif rising_edge(clk) then count <= (count) + '1'; if count = "000" then yout <= xin; end if; end if; end process; end Behavioral;

- 55 -

4 Observations and Results The following graphs were obtained during various simulations of the codes given above.

Figure 12: Single sided amplitude spectrum after DDS. Fc=10MHz

Figure 13: Single sided amplitude spectrum after DDS fc=40 MHz

0 1 2 3 4 5

x 106

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1Single-Sided Amplitude Spectrum of y(t) after dds. fc = 10 MHz

Frequency (Hz)

|Y(f)

|

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

x 107

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1X: 2.505e+006Y: 0.9966

Single-Sided Amplitude Spectrum of y(t) after dds. fc = 40 MHz

Frequency (Hz)

|Y(f)

|

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Figure 14: Single sided amplitude spectrum after DDS fc=80 MHz

Figure 15: Single sided amplitude spectrum after multiplier

0 0.5 1 1.5 2 2.5 3 3.5 4

x 107

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1Single-Sided Amplitude Spectrum of y(t) after dds. fc = 80 MHz

Frequency (Hz)

|Y(f)

|

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

x 107

0

0.2

0.4

0.6

0.8

1

1.2

1.4

X: 3.914e+004Y: 0.2579

Single-Sided Amplitude Spectrum of mul(t) after multiplier

Frequency (Hz)

|Y(f)

|

X: 5.01e+006Y: 0.4925

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Figure 16: Single sided amplitude spectrum after filter

Figure 17: Single sided amplitude spectrum after decimator

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

x 107

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

X: 7.828e+004Y: 0.1442

Single-Sided Amplitude Spectrum of fout(t) after filter

Frequency (Hz)

|Y(f)

|

X: 0Y: 0.7085

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

x 107

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

X: 0Y: 0.7149

Single-Sided Amplitude Spectrum of d(t) after decimator

Frequency (Hz)

|Y(f)

|

X: 9770Y: 0.01792

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Figure 18: Waveforms obtained during simulation of vhd code for DDS

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Figure 19: Waveforms obtained during simulation of vhd code for DDC

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5 Conclusion The digital receiver has a front end ADC followed by a Down Converter. A DDC has been

designed and implemented in VHDL. The same was analysed using MATLAB. The ADC

used in the configuration is AD9042. During the completion of this project, we gained

considerable knowledge on the working of a DDC and Digital Receiver. We also gained

hands on experience of a number of softwares such as ACTEL LIBERO IDE, and

MODELSIM. We were also exposed to the programming and testing of FPGAs while

implementing the DDS on the FPGA.

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6 Discussion

Why would we use a DDC over Analogue Techniques?

Plainly a DDC is implementing something which could be done in analogue – it’s sometimes

good to stop and check why we’d want to do this. The DDC is typically used to convert an

RF signal down to baseband. It does this by digitising at a high sample rate, and then using

purely digital techniques to perform the data reduction. Being digital gives many advantages,

including:

• Digital stability – not affected by temperature or manufacturing processes. With a DDC, if

the system operates at all, it works perfectly – there’s never any tuning or component

tolerance to worry about.

• Controllability – all aspects of the DDC are controlled from software. The local oscillator

can change frequency very rapidly indeed – in many cases a frequency change can take place

on the next sample. Additionally, that frequency hop can be large – there is no settling time

for the oscillator.

• Size. A single ADC can feed many DDCs, a boon for multi-carrier applications. A single

DDC can be implemented in part of an FPGA device, so multiple channels can be

implemented – or additional circuitry could also be added.

However, there are some disadvantages:

• ADC speeds are limited. It is not possible today to digitise high-frequency carriers directly.

There are techniques to extend the range of ADCs, but often it is simpler to use analogue

circuits to bring the carrier down to an IF that digital circuits can then manage.

• ADC dynamic range is limited. In many communications systems, the signal’s amplitude

can vary greatly. Fast ADCs often only have 12bits of resolution – giving an absolute

maximum dynamic range of 72dB. It is often better to use analogue circuits in conjunction

with the ADC to implement AGC functions to ensure that this range is best used. In time,

more and more systems will use predominantly digital technology. However, the high speeds

of many communication systems will ensure that a hybrid approach, using analogue and

digital, will be the best route for many systems for a long time to come. The quest for more

spectral space will ensure that new systems will use ever higher frequencies, ensuring that

analog approaches will be around for a long time to come.

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7 BIBLIOGRAPHY

[1] Skolnik, Merill, Introduction to Radar Systems 3e, IE McGraw, 1981 .

[2] DDS HandBook 6e, Stanford Telecom.

[3] www.actel.com

[4] en.wikipedia.org

[5] www.google.com

[6] The Book On Direct Digital Synthesis, Goldberg.

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APPENDIX

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