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Watch Design

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ModelSim VHDL Simulation Tutorial www.xilinx.com UG102 (v1.1) July 21, 20001-800-255-7778

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of the following U.S. Patents: 4,642,487; 4,695,740; 4,706,216; 4,713,557; 4,746,822; 4,750,155; 4,758,985; 4,820,937; 4,821,233; 4,835,418;

4,855,619; 4,855,669; 4,902,910; 4,940,909; 4,967,107; 5,012,135; 5,023,606; 5,028,821; 5,047,710; 5,068,603; 5,140,193; 5,148,390;

5,155,432; 5,166,858; 5,224,056; 5,243,238; 5,245,277; 5,267,187; 5,291,079; 5,295,090; 5,302,866; 5,319,252; 5,319,254; 5,321,704;

5,329,174; 5,329,181; 5,331,220; 5,331,226; 5,332,929; 5,337,255; 5,343,406; 5,349,248; 5,349,249; 5,349,250; 5,349,691; 5,357,153;

5,360,747; 5,361,229; 5,362,999; 5,365,125; 5,367,207; 5,386,154; 5,394,104; 5,399,924; 5,399,925; 5,410,189; 5,410,194; 5,414,377;

5,422,833; 5,426,378; 5,426,379; 5,430,687; 5,432,719; 5,448,181; 5,448,493; 5,450,021; 5,450,022; 5,453,706; 5,455,525; 5,466,117;

5,469,003; 5,475,253; 5,477,414; 5,481,206; 5,483,478; 5,486,707; 5,486,776; 5,488,316; 5,489,858; 5,489,866; 5,491,353; 5,495,196;

5,498,979; 5,498,989; 5,499,192; 5,500,608; 5,500,609; 5,502,000; 5,502,440; 5,504,439; 5,506,518; 5,506,523; 5,506,878; 5,513,124;

5,517,135; 5,521,835; 5,521,837; 5,523,963; 5,523,971; 5,524,097; 5,526,322; 5,528,169; 5,528,176; 5,530,378; 5,530,384; 5,546,018;

5,550,839; 5,550,843; 5,552,722; 5,553,001; 5,559,751; 5,561,367; 5,561,629; 5,561,631; 5,563,527; 5,563,528; 5,563,529; 5,563,827;

5,565,792; 5,566,123; 5,570,051; 5,574,634; 5,574,655; 5,578,946; 5,581,198; 5,581,199; 5,581,738; 5,583,450; 5,583,452; 5,592,105;

5,594,367; 5,598,424; 5,600,263; 5,600,264; 5,600,271; 5,600,597; 5,608,342; 5,610,536; 5,610,790; 5,610,829; 5,612,633; 5,617,021;5,617,041; 5,617,327; 5,617,573; 5,623,387; 5,627,480; 5,629,637; 5,629,886; 5,631,577; 5,631,583; 5,635,851; 5,636,368; 5,640,106;

5,642,058; 5,646,545; 5,646,547; 5,646,564; 5,646,903; 5,648,732; 5,648,913; 5,650,672; 5,650,946; 5,652,904; 5,654,631; 5,656,950;

5,657,290; 5,659,484; 5,661,660; 5,661,685; 5,670,896; 5,670,897; 5,672,966; 5,673,198; 5,675,262; 5,675,270; 5,675,589; 5,677,638;

5,682,107; 5,689,133; 5,689,516; 5,691,907; 5,691,912; 5,694,047; 5,694,056; 5,724,276; 5,694,399; 5,696,454; 5,701,091; 5,701,441;

5,703,759; 5,705,932; 5,705,938; 5,708,597; 5,712,579; 5,715,197; 5,717,340; 5,719,506; 5,719,507; 5,724,276; 5,726,484; 5,726,584;

5,734,866; 5,734,868; 5,737,234; 5,737,235; 5,737,631; 5,742,178; 5,742,531; 5,744,974; 5,744,979; 5,744,995; 5,748,942; 5,748,979;

5,752,006; 5,752,035; 5,754,459; 5,758,192; 5,760,603; 5,760,604; 5,760,607; 5,761,483; 5,764,076; 5,764,534; 5,764,564; 5,768,179;

5,770,951; 5,773,993; 5,778,439; 5,781,756; 5,784,313; 5,784,577; 5,786,240; 5,787,007; 5,789,938; 5,790,479; 5,790,882; 5,795,068;

5,796,269; 5,798,656; 5,801,546; 5,801,547; 5,801,548; 5,811,985; 5,815,004; 5,815,016; 5,815,404; 5,815,405; 5,818,255; 5,818,730;

5,821,772; 5,821,774; 5,825,202; 5,825,662; 5,825,787; 5,828,230; 5,828,231; 5,828,236; 5,828,608; 5,831,448; 5,831,460; 5,831,845;

5,831,907; 5,835,402; 5,838,167; 5,838,901; 5,838,954; 5,841,296; 5,841,867; 5,844,422; 5,844,424; 5,844,829; 5,844,844; 5,847,577;

5,847,579; 5,847,580; 5,847,993; 5,852,323; 5,861,761; 5,862,082; 5,867,396; 5,870,309; 5,870,327; 5,870,586; 5,874,834; 5,875,111;

5,877,632; 5,877,979; 5,880,492; 5,880,598; 5,880,620; 5,883,525; 5,886,538; 5,889,411; 5,889,413; 5,889,701; 5,892,681; 5,892,961;

5,894,420; 5,896,047; 5,896,329; 5,898,319; 5,898,320; 5,898,602; 5,898,618; 5,898,893; 5,907,245; 5,907,248; 5,909,125; 5,909,453;

5,910,732; 5,912,937; 5,914,514; 5,914,616; 5,920,201; 5,920,202; 5,920,223; 5,923,185; 5,923,602; 5,923,614; 5,928,338; 5,931,962;5,933,023; 5,933,025; 5,933,369; 5,936,415; 5,936,424; 5,939,930; 5,942,913; 5,944,813; 5,945,837; 5,946,478; 5,949,690; 5,949,712;

5,949,983; 5,949,987; 5,952,839; 5,952,846; 5,955,888; 5,956,748; 5,958,026; 5,959,821; 5,959,881; 5,959,885; 5,961,576; 5,962,881;

5,963,048; 5,963,050; 5,969,539; 5,969,543; 5,970,142; 5,970,372; 5,971,595; 5,973,506; 5,978,260; 5,986,958; 5,990,704; 5,991,523;

5,991,788; 5,991,880; 5,991,908; 5,995,419; 5,995,744; 5,995,988; 5,999,014; 5,999,025; 6,002,282; and 6,002,991; Re. 34,363, Re. 34,444,

and Re. 34,808. Other U.S. and foreign patents pending. Xilinx, Inc. does not represent that devices shown or products described herein are free

from patent infringement or from any other third par ty right. Xilinx, Inc. assumes no obligation to correct any errors contained herein or to advise

any user of this text of any correction if such be made. Xilinx, Inc. will not assume any liability for the accuracy or correctness of any engineering

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ModelSim VHDL Simulation TutorialUG102 (v1.1) July 21, 2000

The followin g table shows the revision history for this docu men t.

Date Version Revision

06/ 01/ 00 1.0 Initial Xilinx release.

07/ 21/ 00 1.1 Accu mu lated miscellan eou s u pd ates an d bu g fixes.

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UG102 (v1.1) July 21, 2000 www.xilinx.com ivModelSim VHDL Simulation Tutorial 1-800-255-7778

ModelSim VHDL Simu lation Tutorial

D esign D escription ........................................................................................................... 1Before Beginning the Tutorial ..................................................................................... 2

Tutorial Installation .......................................................................................................... 2Tuto ria l Directo ry and Files ............................................................................................ 2

VHD L Design Files .......................................................................................................... 2

Scrip t Files ......................................................................................................................... 3

Simulat ion Mod els for MTI ............................................................................................ 3

Including CoreGen Components ................................................................................ 3Crea ting th e Tenth s CORE Generato r Com ponent ..................................................... 3

Instan tiat ing th e CO RE Genera tor Mod u le .................................................................. 5

Using th e config ura tion declarat ion .............................................................................. 5

RTL Sim ulation ................................................................................................................... 6Cop ying Source Files to the Fun ctional Simu lation Directory .................................. 6

Star tin g Mod elSim ........................................................................................................... 6

Creating th e Work Directo ry .......................................................................................... 6

Com piling th e Sou rce Files ............................................................................................. 7

Inv oke th e Simulator ....................................................................................................... 7

Runn ing th e Simulat ion .................................................................................................. 8

Synthesizing/Implemen ting the Watch D esign ................................................... 8

Timing S imulation ............................................................................................................ 9

Contents
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UG102 (v1.1) July 21, 2000 www.xilinx.com 1ModelSim VHDL Simulation Tutorial 1-800-255-7778

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ModelSim VHDL Simulat ion Tutorial

This tutorial shows you how the VHDL simu lation flow w orks for Xilinx FPGA design s

using M TIs Mod elsim simu lator. The design, w atch, targets a Virtex dev ice an d

imp lements the fun ctionality of a typical runn er s stopw atch. This tutorial contains the

following sections.

Design Descript ion

Before Beginning the Tutor ial

Tutorial Installation

Including CoreGen Components

Creating the Tenths CORE Generator Com pon ent

Synthesiz ing/ Implementing the des ign

Timing Simu lation

Design DescriptionThrough out th is tutorial, the d esign is referred to as Watch wh ich is a design for a runn er s

stop wa tch. The tutorial assumes th at you have a working kn owledge of VHDL.

The Watch design is a counter that coun ts up from 0 to 59, then resets to zero, and starts

over. There are three external inp uts an d th ree external outp uts in the completed d esign.

The Watch design inpu ts, outpu ts, and m acros are summ arized below.

Inputs

STRTSTOPThe start/ stop bu tton of the stopwat ch. This is an active-low signal that

mu st be depressed then released to start or stop the counting.

RESETForces the signals TENSOUT and ON ESOUT to be 00 after it has been

stopped.

CLOCKSystem clock p rovided externally by the d esigner.

Outputs

TENSOUT[6:0]7-bit bus w hich represents the tens-digit of the stopw atch value.

This is viewable on the 7-segmen t LED d isplay of the Xilinx dem o board . ONESOUT[6:0]Similar to TENSOUT bus abo ve, but rep resents the on e-digit of the

stopwatch value.

TENTHSOUT[9:0]10-bit bus w hich represents th e tenths-digit of the stopw atch

value. This bus is one-hot encod ed. The outp ut is d isplayed to th e LED bar.

Macros

The top level of the Watch d esign consists of the followin g functional blocks.

STATMACHA statema chine that controls starting, stopp ing, and clearing the

counters (One-hot encoded).

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TENTHSA Coregen 10-bit one-hot coun ter macro w hich outp uts th e Tenths d igit as

10-bit one-hot va lue.

CNT60A Count er that ou tpu ts Ones and Tens d igits as 4-bit binary values. Counts 0

to 59 (d ecimal).

HEX2LEDConverts 4-bit values of Ones an d Tens to 7-segment LED format.

DECODEDecodes binary values to one-hot.

Before Beginning the TutorialBefore you begin th is tutorial, set up y our system to u se the Mod el Technology and Xilinx

software as follows.

1. Install the following software.

- Xilinx Development System 3.1i

- Model Technology ModelSim EE/ PE 5.3 or later

2. Verify that your system is properly configured. Consult the release notes and

installation notes that came with you r software package for more informa tion.

Tutorial InstallationThe Watch tutorial file is available for download from the Xilinx Web site at

http://www.xilinx.com/support/techsup/tutorials .

Tutorial Directory and Files

The tutorial directory and tu torial files needed to complete the d esign are provid ed for

you. Some files are not p resent since you w ill create them in later steps. The following tab le

lists the conten ts of the tu torial directories.

VHDL Design Files

Watch is the top level design. The tu torial uses the following VHDL files.

stopwatch.vhd

statmach.vhd

smallcntr.vhd

cnt60.vhd

hex2led.vhd

decode.vhd

testbench.vhd (VHDL testbench for simulation)

Note:The Tenths o ne-hot coun ter is a Coregen macro. The tent hs.vho file is ind irectly used

in RTL simu lation. To get familiarized w ith how the Coregen RTL simulation flow work s,

please consult the Coregen User Guide at

http://support.xilinx.com/support/techsup/journals/coregen/2.1i/docs.htm

Directory Description

mtivhdl_tut/ src VH DL source and script filesmtivhdl_tut/ soln VH DL solu tions d irectory

mtivhdl_tut/ watch VH DL Tutorial Directory
http://www.xilinx.com/http://www.xilinx.com/support/techsup/tutorialshttp://www.xilinx.com/support/techsup/tutorialshttp://support.xilinx.com/support/techsup/journals/coregen/2.1i/docs.htmhttp://support.xilinx.com/support/techsup/journals/coregen/2.1i/docs.htmhttp://www.xilinx.com/support/techsup/tutorialshttp://www.xilinx.com/

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Script Files

The following script files are provided to autom ate the steps in th is tutorial.

rtl_sim.do

stim.do

time_sim.do

Simulation Models for MTITo simu late Xilinx d esigns with Mod elSim in VHD L, you need the following simu lation

libraries wh ich you m ust comp ile.

UN ISIMS LibraryThe Unisim library is u sed for b ehavioral (RTL) simulation w ith

instantiated comp onen ts in the netlist, and for post-synthesis simu lation. The library

is VITAL com pliant, and it also ad ds th e d evice start-up comp onents ROC, ROCBUF,

TOC, TOCBUF, and STARTBUF, for sim ulation.

LogiBLOX LibraryThe LogiBLOX library is used for designs containing LogiBLOX

compo nents, du ring p re-synth esis (RTL), and post-synth esis simu lation. Since

LogiBLOX mod els are not sup port ed in Virtex, this library w ill not be u sed in th is

tutorial.

SIMPRIM LibraryThe SIMPRIM library is u sed for p ost Ngd build (gate level

functional), post-Map (partial timing), and post-place-and-rou te (full timing)

simulations. This library is architecture ind epen d ent.

COREGEN Library CORE Generator is a grap hical interactive d esign tool you use

to create high-level mod ules such a s counters, shift registers, RAM and mu ltiplexers.

The CORE Generator H DL library m odels are u sed for RTL simu lation, and t he

mod els do not u se library comp onents for global signals.The CHDL CORE Generator

source files are found in $XILINX/ vhd l/ src/ XilinxCoreLib.

For detailed instructions on compiling th ese libraries, see Xilinx Solution # 2561 wh ich is

available on th e Intern et at http://www.xilinx.com/techdocs/2561.htm .

After comp iling the libraries, notice that Mod elSim creates a file called mod elsim.ini. View

this file and n otice that th e up per p ortion d efines the locations of the comp iled libraries.

When d oing a simulation, the mod elsim.ini file mu st be provided either by copying th e file

directly to the d irectory w here the H DL files are to be compiled an d th e simulation is to be

run , or by setting the MODELSIM environm ent var iable to the location of your m aster .ini

file. You mu st set this v ariable since the ModelSim installation does n ot initially d eclare the

path for you. For UNIX, type the following.

setenv MODELSIM /path/to/the/modelsim.ini

Including CoreGen Components

Creating the Tenths CORE Generator Component

Since the Watch d esign contains a CORE Generator ma cro, you mu st create it before

perform ing RTL simulation or im plem entation. When creating th e CORE Generatorcompo nent, you will create a behav ioral simu lation netlist for RTL simu lation, as well as

the implementation n etlist.

In this section, you create a CORE Generator mo du le called Tenths. Tenths is a 4-bit binar y

encoded counter. The 4-bit nu mber is decod ed to count th e tenths d igit of the stop watch s

time value.

Creating the Core Generator m odu le

You select the type of mod u le you wa nt in the CORE Generator dialog box as well as the

specific features of th e mod ule.
http://www.xilinx.com/http://www.xilinx.com/techdocs/2561.htmhttp://support.xilinx.com/support/techsup/journals/coregen/2.1i/docs.htmhttp://www.xilinx.com/techdocs/2561.htmhttp://support.xilinx.com/support/techsup/journals/coregen/2.1i/docs.htmhttp://www.xilinx.com/

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To invoke the CORE Generator GUI, type coregen at the UNIX prom pt, or if you a re using

a PC, click on th e CORE Generator icon in the Xilinx Program group .

From Pro ject -> Project Options lin k, select VHDL and your synth esis vend or of choice

for your d esign entry.

In the Target Architectu re field, choose th e Virtex fam ily.

CORE Generator Setup Dialog

Click OK to close the d ialog box.

A list of p ossible COREs are ava ilable. Double Click on Basic Elemen ts - Coun ters.

Double Click on Binary Cou nter to op en th e Binary Cou nter d ialog. This dialog allows th e

user to custom ize the counter to th e design sp ecifications.

Fill in th e Binary Cou nter d ialog with the following settings.

Component N ame: tenths

Defines the name of the m odu le.

Outpu t Width: 4

Defines the width of the outp ut bu s.

Operation: Up

Defines how the coun ter will operate. This field is depend ent on the type of mod ule youselect.

Coun t Restrictions: Restrict Count to A.

This dictates the m aximu m count value.

Outpu t Op tions: Threshold0 set to A

Signal goes high wh en the value sp ecified h as been reached.

Output Options: Registered

CORE Generator Mod ule Selection

Click on the Register Op tions bu tton to op en the Register Options d ialog. Enter the

following settings.

Clock Ena ble: SelectedAsynchron ous Settings: Init with a va lue of 1.

Synchrono us Settings: Non e

Click Ok .

Check that only the following pins are used .

AINIT

CE

Q

Q_Thresh0

CLK

Click Generate. The mod ule is created.

Select Cancel and close Core Generator.

CORE Generator gen erates the follow ing outp ut Files.

tenths.edn

This file is the netlist that is used du ring the Translate p hase of implemen tation.

tenths.vho

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This is the instantiation temp late that is used to incorporate the CORE Generator m odu le

in you r source VHDL.

tenths.xco

This file stores the configuration inform ation for the Tenths m od ule.

coregen.prj

This file stores the CORE Generator configuration for the p roject.

Instantiating the CORE Generator Module

Open stopw atch.vhd in a text editor.

At the line that states:

-- Insert Coregen Count er Comp onent Declaration

Open the tenths.vho file, and cut-and-paste the component d eclaration to stopw atch.vhd.

The temp late comp onent d eclaration for the Coregen instant iation is inserted .

At the line that states:

--Place the CoreGen Coun ter Instant iation

Open t he tenth s.vho file, cut-and -paste from the line your_instance_name : tenths to

AINIT => AIN IT); to stopw atch.vhd .Change your_instance_name to XCOUNTER.

Edit this code to conn ect the signals in th e Stopw atch design to th e ports of the CoreGen

mod ule. The comp leted code is shown below.

XCOUN TER : ten ths p ort m ap (Q => Q, CLK => CLK, Q_THRESH0 => xtermcnt, CE =>

clkenable, AINIT => rstint);

From the tenth s.vho file, also cut and paste th e section beginnin g from line for all : tenth s

use entity to end for; and pa ste it to the bottom of the stopw atch.vhd file, after the en d

inside; line.

Save stopw atch.vhd .

Using the configuration declarationConfigurations are a primary design u nit used to bind component instances to entities. For

compo nent instan ces, the configur ation specifies from man y architectures for an en tity

wh ich architecture to u se for a specific instance. When t he configuration for an entity-

architectur e combination is comp iled into th e library, a simu latable object is created.

Xilinx Coregen VHDL simulation m ethod ology uses the configuration statem ent to bind

the Coregen mod el to the top level design un it. The configuration d eclaration is provided

below:

library XilinxCoreLib;

CONFIGURATION st opw atch_cfg O F testbench IS

FOR testbench_arch

FOR ALL : stopw atch u se configu ration w ork.cfg_tenths;

END FOR;

END FOR;

END stopw atch_cfg;

Copy an d p aste this cod e to the bottom of the testbench.vhd file, below the en d

testbench_arch; line. Save testbench.vh d and exit the ed itor.

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RTL SimulationIn RTL simulation, the t estbench.vhd file instantiates the top level file, stopw atch.vhd. The

testbench also passes stimu lus for the system clock and oth er inpu ts. Ad d itionally, the

testbench.vhd file contains a configurat ion statemen t. The configuration statem ent links

the Coregen tenths comp onen t to the testbench. Withou t this configura tion statement, the

Coregen compon ent will not simulate. To see furt her d etails on wh y the configuration

statement is needed for Coregen compon ents, please refer to the Coregen u ser guide at

http://support.xilinx.com/support/techsup/journals/coregen/2.1i/docs.htm .

Copying Source Files to the Functional Simulation Directory

Copy the following files from the / mtivhdl_tut/ src directory into the

/mtivhdl_tut/watch/func directory.

smallcntr.vhd

cnt60.vhd

hex2led.vhd

stopwatch.vhd

statmach.vhd

testbench.vhd

decode.vhd

rtl_sim.do

Starting ModelSim

If you are using th e PC, invoke th e simulator by selecting ProgramsModel Tech

ModelSim from the Start men u. For UNIX wor kstations, type the following at the p romp t.

vsim -i &

Set the p roject directory using th e File Change D irectory menu command and select

watch/func.

Creating the Work DirectoryBefore comp iling the VHDL/ Verilog source files, you m ust create a directory for u se as a

library. Type th e following a t the Mod elSim p romp t.

vlib work
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This action is echoed in the Tran scrip t wind ow a s shown in the following figure.

Compiling the Source Files

Since Xilinx Unified library comp onen ts are instantiated with in the VH DL source code, the

UNISIM simu lation m odels mu st be provided. The following lines mu st be add ed in the

files watch.vhd and .

library unisim;

use unisim.vcomponents.all;

As a key point, the u nisim library is for simulation on ly, and so th ese lines shou ld be

comm ented ou t for synthesis.

The Vcom comm and comp iles VHDL code for u se with Vsim RTL simulation. Also, to

enhance simulation, ModelSim su pp orts VHDL 93. The -93 switch is used to en able

sup por t for 1076-93. Type the following at th e Mod elSim p romp t.vcom -93 -explicit smallcntr.vhd

vcom -93 cnt60.vhd

vcom -93 decode.vhd hex2led.vhd statmach.vhd

vcom -93 stopwatch.vhd testbench.vhd

The -explicit is used to comp ile smallcntr.vhd since there is a d efinition of= in the

std_logic_1164 and std_logic_un signed libraries that are declared for the en tity. The op tion

resolves resolution conflicts in fav or of exp licit fun ction.

Invoke the Simulator

Type th e following at th e Mod elSim pro mp t to invoke the Mod elSim simu lator.

vsim stopwatch_cfg

Note: The file, rtl_sim_xilinx.do, runs th e above comma nd s; you can run it instead of

executing each comm and . The file is located in the src directory and you can copy it into

the w atch/ func d irectory. To execute th e file, typ e the following at th e ModelSim p romp t.

do rtl_sim.do

Op tionally, you may laun ch the macro via the MacroExecute Macro menu command .

Running the Simulation

To p erform simu lation using ModelSim, follow these steps.

Figure 1: MTI Transcript Window

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1. To view all the ModelSim debug w indows, type the following.view *

2. Add the signals from the selected region in the Structure window to the Wave and List

window s by issuing the following command s at the ModelSim p rompt.add wave *

add list *

3. In the Structure window, notice that VHDL design u nits are indicated by squares. You

can expand and collapse regions of hierarchy by clicking on the (+) and (-) notations.4. The signals window lists the signals in the VHDL design u nit currently

5. To run the simu lation for a specified amount of time at the ModelSim promp t, type the

following.run 20000 ns

The simu lation outpu t is displayed in the Wave window. You may have to zoom

in/ out to view the w aveforms.

6. In the Wave window, try adding or removing cursors with the Cursor Add |

Remove menu command . When multiple cursors are drawn , ModelSim add s a delta

measu remen t showing t he time difference between the cu rsors. The selected cursor is

draw n as a solid line and the values at the cursor location are shown to the right of the

signal name. All other cursors are d raw n as dotted lines. If you cann ot see the signa lvalue next to the signal nam e, select the bar separat ing the signal names from th e

waveforms and drag it to the right.

Note: The above comm and s have been combined into a m acro file called stim.do. You

can execute them at the Mod elSim prom pt.

Synthesizing/Implementing the Watch DesignThis tutorial only covers VHDL RTL and Back-annotated simulation. Please go to

http://support.xilinx.com/support/techsup/tutorials/31i_tutorials_ph.htm and select

tutorials for synth esis an d imp lementation to obtain th e VHDL files needed for back-

annotated simu lation.

While Implementing the d esign, make su re that the MODELSIM VHD L option is

selected for Simulation Options so that a b ack-annotated VHDL file comp atible with

Modelsim is created by Xilinx.

Figure 2: Simulation Output in Wave Window
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Timing SimulationFor VHDL tutorial, you need two files from the Xilinx core tools.

time_sim.vhd

time_sim.sdf

These files are created b y the Xilinx Implem entation tools, and are copied into t he

imp lementation d irectory w here all the place and route files are stored.

Now that the H DL netlist has been resolved into primitives, you n eed to m odify thetestbench configuration. The Unisim library w as referenced since the pre-synth esis netlist

contained instantiated Xilinx m acros.

To p erform timing simulation, follow these steps.

1. Copy time_sim.vhd , time_sim.sdf, and testbench.vhd to the following directory./mtivhdl_tut/watch/time

2. Launch ModelSim, and navigate to the following directory./mtivhdl_tut/watch/time

3. Create the work directory.vlib work

4. View the testbench.vhd file and notice that there are two sections at the bottom.

The configura tion statemen t is for RTL simulation. Comm ent ou t the configuration

statement by inserting -- at the start of all the lines after the end testbench_arch;

line.

5. After editing the testbench.vhd, save the changes and exit.

6. Compile the VHDL source files and the testbench.vcom time_sim.vhd testbench.vhd

7. Read in the SDF file for timing simulation.vsim -sdftyp uut=time_sim.sdf work.testbench

Altern atively, select FileLoad New D esign . Highlight testbench in the Design

Unit wind ow. Click the Add bu tton. To app ly the timing d ata, click on th e SDF tab on

the Load Design w indo w. Click the Add but ton. Browse an d select for thetime_sim .sdf file. Typ e uut in the App ly to Region field and click the Load bu tton.

8. View the necessary debugging windows by typing the following command at the

ModelSim promp t.view wave signals source

9. View and add the signals of the design to the waveform window.

10. At the ModelSim prompt type.run 20000 ns

11. Right click in the waveform wind ow and zoom in. Another way to zoom in, press and

hold the midd le mouse button and d raw a square around the area to zoom in on. After

simulating, you can then zoom in and view the d elay from the clock edge to the

TENSOUT, ONESOUT, and TENTHSOUT output change.

Note: The above comman ds hav e been combined into a m acro file, time_sim.do, and

can be executed at the Mod elSim p rompt.

The MTI-VHDL Tutorial is now complete
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