UCC28070 300W Interleaved PFC Pre-regulator Design Review

1 Design Goals

Application ReportSLUA479–August 2008

UCC28070 300-W Interleaved PFC Pre-Regulator DesignReview

MIchael O'Loughlin ........................................................................ PMP - Power Supply Control Products

ABSTRACTIn higher power applications to utilize the full line power and reduce line currentharmonics PFC Pre-regulators are generally required. In these high power applicationsinterleaving PFC stages can reduce inductor volume and reduce input and outputcapacitor ripple current. This results in smaller overall magnetic volume and filtercapacitor volume increasing the converters overall power density. This is madepossible through distributing the power over two interleaved boost converters and theinductor ripple current cancellation that occurs with interleaving, reference [5]. Thisapplication note will review the design of a 300W two-phase interleaved power factorcorrected (PFC) pre-regulator. This power converter achieves PFC with the use of theUCC28070 interleaved PFC controller, reference [7].

The specifications for this design were chosen based on the power requirements of a medium power LCDTV.

Table 1. Design SpecificationsPARAMETER MIN TYP MAX UNITS

85 265VIN RMS input voltage (VIN_MIN) (VIN_MAX) VVOUT Output voltage 390

47 HzLine frequency 63 Hz(fLINE)PF Power factor at maximum load 0.90POUT Output power 300 Wη Full load efficiency 90%fs Individual phase switching frequency 200 kHz

SLUA479–August 2008 Design Review 1Submit Documentation Feedback

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2 Schematic

+–

Vin VOUT

12V to 21VQ2

RB2

RA1

RB1

Q1

L2

L1

D2

D1

COUT

RA2

CPCA

RRDM

T2

CCDR

CB2

RPK1

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

CAOA

CAOBPKLMT

GND

VAO

VINAC

VSENSE

CSA

CSB

RT

CDR

SS

GDB

GDA

IMO VCC

RSYNTH

VREF

DMAX

RDM

RIMO

RPK2

CZCA

RZCA

CPCB

CZCB

RZCB

CPV

CZV

RZV

CB3

0.1uF 0.1uF

CSS

T1

T1

T2

RSYN

DRA

RSA

RSB

RR

RR

CFA

CFB

RFA

RFB

220pF

220pF

1k

1k

DRB

RDMX

RRT

DB

UCC28070

IIN I

L1

IL2

CB1

1.2nF

CB4

1.2nF

ROB

ROA

4.7pF

CFA

4.7pF

CFB

DPA2

DPB2

DPA1

DPB1

CTA

CTB

RTA

RTB

VCC=13V

GDA

GDB

Schematic www.ti.com

UCC28070 PFC controller in a two-phase average current mode control interleaved PFC pre-regulator.

Figure 1. Typical Average Current Mode Interleaved PFC Pre-Regulator

Design Review2 SLUA479–August 2008Submit Documentation Feedback


3 Inductor Selection

IN

L1

IK(D) =

I

D

D

1 2DK(D) = if D is < 05 = 0.5

1 D

-

-

2D 1K(D) = if D is > 0.5

D

-

D - Duty Cycle

K(D

)=D

I IN/D

I L1

www.ti.com Inductor Selection

One of the benefits of interleaved PFC boost pre-regulators is inductor ripple current reduction that is seenat the input of the converter. The following equations and Figure 2 show the ratio of input ripple current(ΔIIN) to individual inductor ripple current (ΔIL1) in a two-phase interleaved PFC as a function of duty cycle(D). Because of this inductor ripple current cancellation, the designer can allow each inductor to havemore inductor ripple current than in a single stage design.

Figure 2. Input Inductor Ripple Current Cancellation

The boost inductors (L1 and L2) are selected based on the maximum allowable input ripple current. Inuniversal applications (e.g., 85 V to 265 V RMS input) the maximum input ripple current occurs at thepeak of low line and for this design the maximum input ripple current was set to 30% of the peak nominalinput current at low line.



OUT IN_MINPLL

OUT

V V 2 390V 85V 2D = = 0.69

V 390 V

- -»

PLL

2 0.69 1K(D ) = = 0.55

0.69

´ -

OUT

IN_MIN PLL

P 2 × 0.3 300W 2 0.3IL = = 3.0 A

V K(D ) 85V 0.90 0.55h

´ ´ ´D »

´ ´ ´ ´

IN_MIN PLL

s

V 2 D 85V 2 0.69L1 = L2 = = 140 H

IL × 2.96A 200 kHz

´ ´ ´ ´»

D ´u

f

22

IN_MIN OUT IN_MINOUT

s OUTL1_RMS L2_RMS

0IN_MIN

V 2sin( ) V V 2sin( )PL1 V12I = I = +

V 12

p

q q

h p

æ ö-

æ ö ç ÷´ç ÷ ç ÷´ç ÷ òç ÷

´ç ÷ ç ÷ç ÷ç ÷è ø

è ø

f

22

L1_RMS L2_RMS0

85V 2sin( ) 390V 85V 2sin( )300W1 140 H 200kHz 390V2I = I = + 2A

85V 0.90 12

p

q q

p

æ ö-æ ö

ç ÷´ç ÷

´ç ÷ »ç ÷ òç ÷´ç ÷

ç ÷ ç ÷ç ÷è øè ø

u

MIN MINL1 = L2 = 140 Hu

MAX MAXL1 = L2 = 350 Hu

MIN MAXAVG AVG

L1 + L1 140 H + 350 HL1 = L2 = = = 245 H

2 2

u uu

Inductor Selection www.ti.com

The following calculations are used to select the appropriate inductance for L1 and L2. Where, variableDPLL is the converter’s duty cycle at the peak of low line operation. Variable K(DPLL) is the ratio of inputcurrent to inductor ripple current at the peak of low line operation. ∆IL is the boost inductor ripple currentat the peak of low line based on the converters input ripple current requirements.

The following equation can be used to calculate total inductor RMS current (IL1_RMS and IL2_RMS).

A 140-µH boost inductor from Cooper Electronic Technologies part number CTX16-18060 was chosen forthe design. The inductance during normal operation will swing from 140µH to 350µH.

The average inductance is calculated for current loop compensation purposes. This will be used in thecurrent loop compensation section of the application note:



4 Output Capacitor Selection

( )

OUT

LINEOUT 2 2 22

OUT OUT

2 P 2 300W

47 HzC = 192 FV (V 0.75) (390V) 292.5V

´ ´

³ »

- ´ -

f

u

OUTC = 200 μF

OUTRIPPLE

OUT LINE OUT

2 300W2 P 1 0.90V = = 14.5V

V 2 2 C 390V 2π 2 47Hz 200 μFh p

´

´»

´ ´ ´ ´ ´ ´ ´f

OUTCOUT_LF

OUT

P 300WI = = 0.604A

V 2 0.90 390V 2h

»

´ ´

( )

2

22OUT OUTCOUT_HF COUT_LF

OUT IN_MIN

P 16 VI = I

V 6 V 2h

h p

æ ö´

ç ÷- -ç ÷´è ø

( )

222

COUT_HF

300W 16 390VI = (0.90) 0.604 1.0A

0.90 390V 6 85V 2p

æ ö´- - »ç ÷

ç ÷´ ´è ø

www.ti.com Output Capacitor Selection

The output capacitor (COUT) is selected based on holdup requirements.

Two 100-µF capacitors were used in parallel for the output capacitor.

For this size capacitor the output peak to peak voltage ripple (VRIPPLE) is:

In addition to holdup requirements, a capacitor must be selected so that it can withstand both thelow-frequency RMS current (ICOUT_LF) and the high-frequency RMS current (ICOUT_HF). High-voltageelectrolytic capacitors generally have both low frequency (100 Hz to 120 Hz) and high frequency RMScurrent ratings on their data sheets.



5 Power Semiconductor Selection (Q1, Q2, D1, D2)

OUT L1PEAK

IN_MIN

P 2 I 300W 2 2.97AI = + 1.2 = + 1.2 5.1A

2 V 2 2 × 85V 0.90 2h

æ ö æ ö´ D ´»ç ÷ ç ÷

ç ÷ç ÷´ ´ ´è øè ø

OUT

IN_MINDS

OUTIN_MIN

P 300W16 V 2 16 85V 2η 0.90I = 2 = 2 1.685A3 V 3 390V2 V 2 2 85V 2p p

´ ´- - »

´ ´ ´ ´´ ´

OUTD

OUT

P 300WI = = 0.39A

V 2 390V»

´

Power Semiconductor Selection (Q1, Q2, D1, D2) www.ti.com

The selection of Q1, Q2, D1, and D2 are based on the power requirements of the design. Application note(SLUA369), UCC28528 350-W Two Phase Interleaved PFC Pre-regulator, explains how to select powersemiconductor components for interleaved PFC pre-regulators using average current mode controltechniques, reference [4]. To meet the power requirements of this design IRFB11N50A N channel FETsfrom IR were chosen for Q1 and Q2. To reduce reverse recovery losses SiC diodes CSD10060G fromCREE were chosen for the design.

Boost Diode (D1, D2) and FET (Q1, Q2) peak current (IPEAK) calculation:

A factor of 1.2 was added to the equation for added design margin.

Q1 and Q2 RMS current (IDS) calculation:

D1 and D2’s average current calculation (ID):


http://www-s.ti.com/sc/techlit/SLUA369


6 Current Sense Transformers Setup and Selection (T1, T2, DRA, DRB)

S PEAKCT

P RS

N I 5.1AN = = = 51

N I 0.1A³

CTN = 50

OUT IN_MINSM

PEAK OUTs

CT

V V 2V 3.7V 390V 85V 2L = 6.24mH

I 5.1AV 390V0.02 200kHz0.02

50N

- -³ ´ ´ »

´ ´´ ´ f

ML = 8.25 mH

SSA SB

PEAK

CT

0.9 V 0.9 3.7V 50R = R = = 32.5

I 0.102A

N

´ ´ ´» W

SR = 33.2 W

S MAXR

MAX

R D 33.2 × 0.97R = 1 k

1 D 1 0.97

´ W³ W

- -;

PR PEAK R

S

N 5.1A 1 kV = I R = 103V

N 50

´ W´ ´ ³

www.ti.com Current Sense Transformers Setup and Selection (T1, T2, DRA, DRB)

The current sense transformer is selected to handle IPEAK and have a peak current sense signal (IRS) ofroughly 100 mA.

For this design a current sense transformer with a turns ratio (NCT) of 50 was chosen for the design.

The magnetizing inductance (LM) of the current sense transformer should be selected or designed so themagnetizing current is less than 2% of the maximum current sense signal. The following equationcalculates the minimum LM where VS is the maximum current sense signal voltage. For this design acurrent sense transformer was designed by Cooper Electronic Technologies (CTX16-18294) with amagnetizing inductance of 8.25 mH.

Selection of the current sense resistors (RSA and RSB ) is based on the peak current limit signal (VS) andthe peak current on the secondary side of the current sense transformer. A factor of 0.9 was multiplied bythe current sense signal to leave room for the 10% PWM ramp that is used to make this design morenoise immune at lighter loads.

Select a standard resistor for the design:

Resistor RR is used to reset the current sense transformer:

Current sense transformer’s rectifying diodes (DR) need to be designed to withstand the current sensetransformers reset voltage (VR):

To improve noise immunity at extremely light loads, a PWM ramp with a dc offset is recommended to beadded to the current sense signals. Electrical components RTA, RTB, CTA, CTB, DPA1, DPA2, DPB1, and DPB2form a PWM ramp that is activated and deactivated by the gate drive outputs of the UCC28070. ResistorROA and ROB add a DC offset to the CS resistors (RSA and RSB).



OFFV = 0.2 V

( ) ( )VCC OFF SAOA OB

OFF

V V R 13V 0.2V 33.2R = R = = 2.1 k

V 0.2V

- - ´» W

OAR = 2.05 kW

( ) ( )VCC s OFF DPA2 SATA TB

s OFF

V (V 0.1 V +V R 13V (3.7V 0.1 0.2V)+0.6V 33.2R =R = = 2.62 k

V 0.1 V 3.7V 0.1 0.2V

- ´ - - ´ - ´» W

´ - ´ -

TA TBR = R = 2.49 kW

TA TBSA S

1C = C = 50 nF

R 3»

´ ´f

TAC = 47 nF

Current Sense Transformers Setup and Selection (T1, T2, DRA, DRB) www.ti.com

When the inductor current becomes discontinuous the boost inductors ring with the parasitic capacitancesin the boost stages. This inductor current rings through the CTs causing a false current sense signal.Refer to the following graphical representation of what the current sense signal looks like when theinductor current goes discontinuous. Note that the inductor current and VRSA may vary from this graphicalrepresentation depending on how much inductor ringing is in the design when the unit goes discontinuous.

Figure 3. False Current Sense Signal

To properly select the offset (VOFF) just requires adjusting resistors ROA and ROB to add a dc offset to thecurrent sense resistors, that is high enough to block DRA and DRB from conducting when a false currentsense signals is present. This occurs when the inductors are operating with discontinuous inductor currentand was described above in detail. Setting the offset to 200 mV is a good starting point and may need tobe adjusted based on individual design criteria and the amount of noise and parasitic elements present inthe system.


Chose a standard resistor for the design:

A standard capacitor needs to be chosen for the design:



7 Setting Up Peak Current Limiting (RPK1, RPK2)

S PK1PK2

REF S

V R 3.7V 3.65 kΩR = = 5.9 k

V V 6V 3.7V

´ ´» W

- -

9 9

RTs

7.5 10 Hz 7.5 10 HzR = = = 37.5 k

200 kHz

´ W ´ ´ W ´W

f

RTR = 37.4 kW

( ) ( )DMX RT MAXR = R 2 D 1 = 37.4 kΩ 2 0.97 1 = 35 k´ - ´ - W

DMXR = 34.8 kW

8 Programming VOUT

3A

R M= W

A

B

OUT

VREFR

3V 3MΩ2R = = 23.3 kVREF 390V 3V

V2

´´

» W-

-

BR = 23.2 kW

A BOVP

B

R + R 3M + 23.2 kV = 3.18V = 3.18V 414V

R 23.2 k

W W»

W

www.ti.com Setting Up Peak Current Limiting (RPK1, RPK2)

The UCC28070 has an adjustable peak current limit comparator that can be set up by selecting RPK1 andcalculating the required RPK2. For this design to keep the reset voltage of the current sense transformermanageable the peak current sense signal (VS) was set to 3.7 V.

Converter Timing and Maximum Duty Cycle ClampResistor RRT and RDMX set up converter timing and the maximum PWM duty cycle clamp:

A standard resistor was selected for the design:

Resistor RDMX was selected to set the maximum duty cycle clamp (DMAX) to 0.97:

Chose a standard resistor for the design:

Resistor RA is selected to minimize the error due to VSENSE input bias current and to minimize loadingon the power line when the PFC is disabled. Construct resistor RA from two or more resistors in series tomeet high voltage requirements. Resistor RB is sized to program the converters output voltage (VOUT).

A standard resistor was chosen for the design.

The resistor divider formed by RA and RB from the output voltage to the VSENSE pin also sets the overvoltage protection threshold (VOVP).



9 VINAC Divider Setup

10 Voltage Loop Configuration

Vgm = 70 Sm

VREF

OUT

V 3VH = = 0.0077

V 390V»

ORIPPLE V

VAO 0.03 3.2V 0.03Z = = 12.3 k

V H gm 14.5V 0.0077 70 Sm

D ´ ´» W

´ ´ ´ ´

PVLINE o

1 1C = = 138nF

2 2 Z 2 2 47Hz 12.3kp p»

´ ´ ´ ´ ´ ´ Wf

PVC = 150 nF

VAO = 3.2 VD

OUT

OUTCV V

OUT PV

1P

j 2 C 1η= H gm

VAO V 2 C

p

p

´ ´´ ´ ´ ´

D ´ ´f

CV

300W1 10.90= 0.0077 70 S 11Hz

3.2V 2 200 F 390V 2 150nFm

p m p´ ´ ´ ´ »

´ ´ ´ ´ ´f

ZVCV PV

1 1R = = 96.4 k

2 C 2 10.6Hz 150nFp p» W

´ ´ ´ ´f

VINAC Divider Setup www.ti.com

The UCC28070 also requires sensing the line input for proper operation. This requires a divider from therectified line voltage to the VINAC pin of the UCC28070. For simplicity the UCC28070 was designed touse the same resistor divider values as the VSENSE pin. Resistors RA and RB need to be the same ratiofor the VINAC voltage divider as thouse in the VSENSE voltage divider to ensure the UCC28070 controlleroperates correctly. Please refer to the applications schematic for proper component placement.

The methodology used to compensate the voltage loop is based on the compensation methodologydeveloped by Lloyd Dixon. A detailed explanation of this compensation scheme written by Mr. Dixon canbe found in the 1990 Unitrode Power Supply Design SEM700, High Power Factor Switching Pre-regulatorDesign Optimization, Topic 7, reference [2].

Capacitor CPV is sized to attenuate low frequency ripple to less than 3% of the voltage amplifier outputrange. This will ensure good power factor and low input current harmonic distortion.

Voltage Amplifier Transconductance Amplifier gain:

Voltage Divider Feedback Gain:

Output impedance (ZO) is required to attenuate the low frequency boost capacitor output ripple (VRIPPLE) toless than 3% of the effective voltage amplifier output range (ΔVAO). This impedance is set by properlyselecting feedback capacitor CPV:

Choose as standard capacitor for the design:

For the highest possible power factor the voltage loop crossover frequency (fCV) needs to be set based onthe following equation:

Voltage compensation resistor RZV is then sized to put a pole at the converter’s voltage loop crossoverfrequency:


10 Design Review SLUA479–August 2008Submit Documentation Feedback


ZVR = 100 kW

ZVCV

ZV

1 1C = = 1.5 F

11Hz2 100 k2 R

1010

m

pp

»

´ ´ W´ ´f

( )( )

VAO ZV ZVCV V

OUT ZV ZV PVZV PV

ZV PV

V j 2 R C +1G ( ) = = H gm

V j 2 f R C Cj 2 C + C +1

C +C

p

pp

D ´ ´ ´ ´´ ´

D æ ö´ ´ ´ ´ ´´ ´ ´ ç ÷

è ø

ff

f

OUT

OUTOUTPSV

VAO OUT

1P

j 2 CV ηG ( ) = =

V VAO V

p

æ ö

ç ÷´ ´ ´D è ø

´D D

ff

( )PSV CVTvdB( ) = 20log G ( ) G ( )´f f f

1 10 100 1 .10390

60

30

0

30

60

90

90

90-

TvdB f( )

1 103

´1 f

1 10 100 1 .1030

15

30

45

60

75

90

90

0

qv f( )

1 103

´1 f

www.ti.com Voltage Loop Configuration

Voltage compensation capacitor CZV is used to increase the dc gain of the voltage loop and gives someadded phase margin before crossover. The zero added to the voltage loop needs to be set at 1/10th thecrossover frequency.

The following equations can be used to estimate voltage compensation network gain, voltage loop powerstage gain and voltage loop gain. These equations can also be used to graphically check loop stability.

Voltage Compensation Network Gain (GCV(f)) as function of frequency:

Voltage Loop Power Stage Gain (GPSV(f)) as function of frequency:

Voltage Loop Gain in dB (TvdB(f)) as function of frequency:

Figure 4 shows the theoretical loop gain (TvdB(f)) as a function of frequency and Figure 5 shows thetheoretical loop phase (θv(f)) as a function of frequency. From these figures it can be observed that thevoltage loop crossed over at roughly 9 Hz with a phase margin of 60 degrees. Compensating the voltageloop is not an exact science and should be checked with a network analyzer and adjusted if necessary.

Figure 4. Theoretical Voltage Loop Gain Figure 5. Theoretical Voltage Loop Phase(TvdB(f)) (θv(f))



11 Current Loop Compensation

BCT MAX

A BSYN

S

R 23.2 kN L1 50 350 HR + R 3 M + 23.2 kR = = 40.5 k

R 0.1 nF 33.2 0.1nF

mW

´ ´ ´W W

» W´ W ´

SYNR = 38.3 kW

( ) ( )-6 -6

INAC VAOMAX

2VFF

17 10 A V V 1V 17 10 A 0.76V 5V 1VIMO = = 130 A

K 0.398Vm

´ ´ - ´ ´ -»

( )A BI

B

0.95V R + R 0.76V (3M + 23.2k )V = = 70V

R 2 23.2k 2

´ ´ W W»

´ W ´

2

1 1 2 1 1 1 300 2 133 2 2 458

2 1 2 0 92 72 50OUT

S

CT

. P . WV R . . V

V N . Vh

´ ´= ´ ´ = ´ ´ ´ W »

´ ´ ´

2IMO

V 1.93 VR = = 18.9k

IMO 130 Am» W

IMOR = 19.6 kW

OUT SCT

PSCs

AVG RAMP

1 1V R 390 V 33.2N 50G = = 2.1

200 kHz2 245 H 4.0V2 L1 V

1010p mp

´ ´ ´ W ´

»

´ ´ ´´ ´ ´f

Cgm = 100 Sm

ZC1 ZC2C PSC

1 1R = R = = = 4.8 k

gm G 100 S 2.1mW

´ ´

ZC1 ZC2s

ZC

1 1C = C = = 1.7nF

200 kHz2 4.8 k2 × R

1010pp

»

´ Wf

Current Loop Compensation www.ti.com

Setting up the current synthesizer is accomplished by correctly selecting RSYN:

The inductor used in this design example swings from 350 µH to 140 µH from no load to maximum load.When calculating RSYN the highest inductance value (L1MAX) should be used.

Chose a standard resistor:

The IMO resistor needs to be set with the following equation to center the digitized multiplier for universalline applications:

Choose a standard resistor close to the calculated value:

The current loop in a PFC converter is generally designed to crossover at between 1/10th and 1/6th theconverter’s switching frequency. The current loop in this design example is going to be designed tocrossover at 1/10th of the single stage’s switching frequency. In order to properly compensate the currentloop it is required to calculate the current loop's power stage gain (GPS) at the current loop's crossover andproperly select passive components RZC1/2, CZC1/2 and CPC1/2:

Variable gmC is the current amplifier Transconductance Current Amplifier Gain.



PC1 PC2

ZC

1 1C = C = = 333 pF

s 200 kHz2 R 2 4.8 k

2 2p p

»

´ ´ Wf

,ZC1 ZC1 PC1R = 4.02 k C = 2.2 nF, C = 330 pFW

( )( )

POUT

S ZC ZCC

RAMP ZC ZC PCZC PC

ZC PC

NV Rs

N j 2 R C +1TcdB( ) = 20log gm

j 2 L1 V j 2 R C Cj 2 C +C +1

C +C

p

p pp

æ ö

ç ÷´ ´´ ´ ´ ´ç ÷

´ ´ç ÷

´ ´ ´ ´ D æ ö´ ´ ´ ´ ´ç ÷´ ´ ´ ç ÷ç ÷

è øè ø

ff

f ff

1 10 100 1 .103

1 .104

1 .105

1 .106

200

133.33

66.67

0

66.67

133.33

200

200

200-

TcdB f( )

1 106

´1 f

1 10 100 1 .103

1 .104

1 .105

1 .106

0

30

60

90

120

150

180

180

0

qc f( )

1 106

´1 f

www.ti.com Current Loop Compensation

Standard components close to the calculated values are chosen for the current loop compensation:

Graphically Check Theoretical Current Loop Gain (TcdB(f)) and loop phase (θc(f)): From the plots inFigure 6 and Figure 7 it can be observed that the theoretical loop gain crossed over at roughly 20 kHzwith a phase margin of roughly 39 degrees.

Figure 6. Current Loop Gain (TdB(f)) Figure 7. Current Loop Phase (θc(f))



12 Soft Start

ZVSSMIN

2.25 V C 2.25V 1.5 Ft = = 338 ms

10 A 10 A

m

m m

´ ´»

SS ZVC C³

ssss

10 A t 10 A 200 msC = = 0.889 F

2.25V 2.25 V

m mm

´ ´»

ssC = 1.5 Fm

13 Spread Spectrum Reduces EMI

DM = 30 kHzf

10DRf kHz=

6 6

RDMDM

937.5 10 937.5 10R = = = 31.13 k

f 30 kHz

´ W ´ WW

-9 -9RDM

CDRRD

0.0667 10 F R 0.0667 10 F 31.13 kC = = = 208 pF

10 kHz

´ ´ ´ ´ W

f

RDMR = 31.6 kW

220CDR

C pF=

Soft Start www.ti.com

To have a controlled soft start the CSS capacitor needs to be set to at least the same value as the CZVcapacitor or larger. This means the design has a minimum soft start time based on the CZV capacitor

The soft-start timing can be set with timing capacitor CSS once the amount of soft start time (tSS) has beendetermined. Our original design requirement was to have 200 ms of soft-start time. The calculatedcapacitance needed for this soft-start time is less than the minimum required capacitance.

A CSS capacitor value equal to the CZV capacitor was chosen for the design.

It has been shown that dithering the converter’s switching frequency can reduce EMI. Resistor RRDM andCCDR program the frequency dithering magnitude and rate. For this design the frequency dither magnitude(fDM) was set to 30 kHz and the frequency dither rate (fDR) was set to 10 kHz. The frequency will ditheraround the typical frequency programmed by resistor RRT. In this example the frequency will dither fromroughly 185 kHz to 215 kHz at a 10 kHz rate.

A standard resistor and capacitor are chosen for the design:



14 Recommended PCB Device Layoutwww.ti.com Recommended PCB Device Layout

Interleaved PFC techniques dramatically reduce input and output ripple current caused by the PFC boostinductor, which allows the circuit to use smaller and less expensive filters. To maximize the benefits ofinterleaving, the output filter capacitor should be located after the two phases allowing the current of eachphase to be combined together before entering the boost capacitor. Similar to other power managementdevices, when laying out the PCB it is important to use star grounding techniques and to keep filter andhigh frequency bypass capacitors as close to the device pins and ground pin as possible. To minimize theinterference caused by magnetic coupling from the boost inductor, the device should be located at leastone inch away from the boost inductor. It is also recommended that the device not be placed underneathmagnetic elements. To verify the application a 300-W interleaved prototype was constructed andevaluated. This prototype consisted of mother board that was the power stage and a daughter board thatconsisted of the control circuitry. Refer to Figure 8 through Figure 13 for schematics and a recommendedlayout. The daughter board controller has two jumpers JP1 and JP2. If these jumpers are open theevaluation module is running with frequency dithering. If these jumpers are shorted frequency dither isdisabled and the EVM can be synchronized through the sync input.

Figure 8. 300-W Prototype Daughter Board Controller Schematic



+ +

+

UCC27324D

U1

Recommended PCB Device Layout www.ti.com

Figure 9. 300-W Prototype Mother Board Power Stage



www.ti.com Recommended PCB Device Layout

Figure 10. Daughter Board Layout Front

Figure 11. Daughter Board Layout Back



HS1

HS3 HS2

Q1 Q1

T1 T2

.

.

AC LINE AC NEUTRAL

VOUT RETURN

C6 C7

C5

L1 L2

F1

VAR1

RT

1

C2

C2

D5

D6

J1

VCCGND

SYNC

C11

J2

AC LINEAC NEUTRAL

VOUT

D9 D2

D1

JP2 JP2

D3

U1R10

R9

R1

9

R18 R5

R8

C8C12

D12

C1

0

D1

1R

16 R13 R1

D13 D7

R6

D8

C4

R15

R14

R1

1

R2

D10C9

R1

7

R12 R7

R3

R4

D4C3

J1

RETURN

Recommended PCB Device Layout www.ti.com

Figure 12. Mother Board Layout Front

Figure 13. Mother Board Bottom



15 Efficiency Curves

15.1 Prototype Efficiency

Efficiency

80%

82%

84%

86%

88%

90%

92%

94%

96%

98%

100%

10% 20% 30% 40% 50% 60% 70% 80% 90% 100%

% Output Power

%E

ffic

iency

Efficency at Vin 85V RMS

Efficency at Vin = 265V RMS

Efficiency

80%

82%

84%

86%

88%

90%

92%

94%

96%

98%

100%

10% 20% 30% 40% 50% 60% 70% 80% 90% 100%

% Output Power%

Eff

icie

ncy

Efficiency at VIN = 115V

Efficiency at VIN = 230V

Current Harmonics VIN

= 230V, POUT

= 300W

0.00001

0.23580

0.47159

0.70737

0.94316

1.17894

1.41473

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39

Harmonic

Am

plit

ude

(A)

EN61000-3-2 Class D Specif ications

www.ti.com Efficiency Curves

A 300-W prototype was built based on the design information presented in this application note. Thefollowing graphs show the performance of this EVM.

Figure 14. Figure 15.

Figure 16. Prototype Harmonic Content at VIN = 230 V, POUT = 300 W



15.2 Prototype Power Factor

Pow er Factor

0.900

0.910

0.920

0.930

0.940

0.950

0.960

0.970

0.980

0.990

1.000

20% 30% 40% 50% 60% 70% 80% 90% 100%

% Output Pow er

PF

PF VIN = 115V

PF VIN = 230V

Pow er Factor

0.900

0.910

0.920

0.930

0.940

0.950

0.960

0.970

0.980

0.990

1.000

20% 30% 40% 50% 60% 70% 80% 90% 100%

% Output Pow er

PF

PF VIN = 85V

PF VIN = 265V

Efficiency Curves www.ti.com

Figure 18. Input Current and Output RippleFigure 17.Voltage at Maximum Output Power

Ch2 = IIN, CH2 = VOUT

Figure 19. VIN = 85 V RMS Figure 20. VIN = 265 V RMS



15.3 Inductor Ripple Current Cancellation, CH2=IL1, CH3=IL2, M1=IL1+IL2www.ti.com Efficiency Curves

Figure 21. VIN = 85 V RMS, Peak of Line Figure 22. VIN = 265V RMS, Peak of Line

Figure 23. VIN = 265V RMS, Line Voltage at Figure 24. VIN = 85 V, POUT = 300 WHalf the Output Voltage



Efficiency Curves www.ti.com

Figure 25. VIN = 265 V, POUT = 300 W



15.4 Recovery from Line Dropout, CH1= Rectified Line Voltage, CH2=IL1, CH3=IL2, CH4 =

15.5 Startup, CH2 = IL1, CH3 = IL2, CH4 = VOUT

www.ti.com Efficiency Curves

VOUT

Figure 26. Brownout at VIN = 115V, POUT = 300 W

Figure 27. VIN = 85 V, POUT = 300 W Figure 28. VIN = 265 V, POUT = 300 W



15.6 EMI Measurements

16 References

References www.ti.com

When dithering was applied to the EVM a 4.35dBuV reduction in the Quasi Peak (QP) measurement wasobserved. Note a filter was added to the front end of the EVM to clean up some of the noise to take EMIdata. Depending on the filter the amount of EMI will vary. Also, this filter was not setup to pass EMIrequirements but to show frequency dither reduced EMI.

Figure 29. EMI Quasi Peak (QP) Measurement with out Frequency Dithering, No EMI Filter Present

Figure 30. EMI Quasi Peak (QP) Measurement with Frequency Dithering, No EMI filter Present

1. Lazlo Balogh and Richard Redi, Power Factor Correction with Interleaved Boost, APEC 1993, pp.168-174

2. Lloyd Dixon, High Power Factor Switching Pre-regulator Design Optimization, Unitrode Power SupplyDesign Seminar SEM-700, 1990, Topic 7

3. Brett Miwa, David Otten, Martin F. Schlecht, High Efficiency Power Factor Correction Using InterleavedTechniques IEEE 1992, pp. 557 to 568

4. Michael O’Loughlin, 350W, Two Phase Interleaved PFC Pre-regulator Design Review, TexasInstrument Literature Number SLUA369, 2006

5. Michael O’Louglin, An Interleaving PFC Pre-Regulator for High-Power Converters Unitrode/TI PowerSupply Design Seminar SEM-1700, Topic 5

6. P. Zumel, O. Garcia, J. A. Cobos, J. Uceda, EMI Reduction by Interleaving of Power ConvertersPresentation, APEC 2004

7. UCC28070 Data Sheet, Texas Instruments Literature Number SLUS794,http://focus.ti.com/lit/ds/symlink/ucc28070.pdf


http://www-s.ti.com/sc/techlit/SLUA369

http://www-s.ti.com/sc/techlit/SLUS794

http://focus.ti.com/lit/ds/symlink/ucc28070.pdf


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Documents

UCC28070 300W Interleaved PFC Pre-regulator Design Review