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UART2SPI Design Example

Date: June 2017

Revision: 1.1

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TABLE OF CONTENTS

1 INTRODUCTION .................................................................................................................................................................... 3

1.1 OVERVIEW ........................................................................................................................................................................... 3 1.2 TOP LEVEL ARCHITECTURE ................................................................................................................................................. 3

2 INSTALLING THE EXAMPLE DESIGN ............................................................................................................................. 4

3 SYSTEM REQUIREMENT .................................................................................................................................................... 5

3.1 HARDWARE REQUIREMENTS ............................................................................................................................................... 5 3.2 SOFTWARE REQUIREMENTS ................................................................................................................................................. 5

4 EXTERNAL INTERFACE ...................................................................................................................................................... 6

4.1 OVERVIEW ........................................................................................................................................................................... 6 4.2 PIN LIST TABLE ................................................................................................................................................................... 6

5 FUNCTIONAL BLOCK DESCRIPTION.............................................................................................................................. 7

5.1 SPI ...................................................................................................................................................................................... 7 5.2 UART_N ............................................................................................................................................................................. 7 5.3 AVALON_TRANSACTION ...................................................................................................................................................... 8

5.3.1 Typical UART control flow via SPI. ........................................................................................................................... 8 5.3.2 State Machine ............................................................................................................................................................. 8 5.3.3 SPI register structure .................................................................................................................................................. 9 5.3.4 Lead code.................................................................................................................................................................. 10

6 VERIFICATION PLAN ........................................................................................................................................................ 11

7 REVISION HISTORY ........................................................................................................................................................... 12

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1 Introduction

1.1 Overview

UART2SPI reference design works on Intel RTU board. It extends the UART port to 6 for Quark MCU.

1.2 Top Level Architecture

Figure 1-1 Top Level Block Diagram

Figure 1-2 FPGA Block Diagram

The Figure 1-1 shows the high level block diagram of Intel RTU board. Max10 FPGA works as a bridge between Quark MCU

and UART periphrals. FPGA works as slave device in SPI and as master in all 6 UART.

Figure 1-2 shows the block level diagram in FPGA design.

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2 Installing the Example Design

You can download the design example files from the UART2SPI web page.

Table 2-1 shows the files in the top-level directory:

Table 2-1 Top-Level Directory Files

File Name Description

uart_bridge.qpf Quartus II project file.

uart_bridge.qsf Quartus II settings file.

top.v Top-level file.

top.sdc Contains top-level clock requirements

system.qsys qsys file

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3 System Requirement

This section describes the hardware and software requirements to run UART2SPI design example.

3.1 Hardware Requirements

The UART2SPI Design Example requires:

➢ Intel RTU board

➢ 1 Mini USB cable

➢ 1 Altera USB Blaster cable

3.2 Software Requirements

Ensure that you have quartus 16.0.0 rightly installed in your PC.

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4 External Interface

The external interface of the reference design.

4.1 Overview

UART2SPI interface contains 2 set of interface : 6 groups of UART ports and 1 SPI interface..

4.2 Pin List Table

The Table 4-1 shows the interface pin list of inteface of UART2SPI Max10 FPGA.

Table 4-1 _Interface Pin List

LMS Interface Pin List

Signal Name Width IO standard Direction Description

Clock 1 2.5V input 50MHz clock input

RESET_N 1 2.5V input reset signal, low active.

uart[n]_rx 1 2.5V input n=0,1 ; RS 485 input data

uart[n]_tx 1 2.5V ouput n=0,1 ; RS 485 output data

uart[n]_oe 1 2.5V output n=0,1 ; RS 485 output enable

uart[m]_rx 1 2.5V input m=2,3,4,5 ; RS 232 input data

uart[m]_tx 1 2.5V Output m=2,3,4,5 ; RS 232 output data

spi_mosi 1 2.5V input SPI MOSI

spi_sclk 1 2.5V input SPI clock

spi_miso 1 2.5V output SPI MISO

spi_ss 1 2.5V input SPI SS

int_spi 1 2.5V output Interrupt output to Quark MCU

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5 Functional Block Description

5.1 SPI

SPI module is inside system.qsys. It is a Quartus IP block (SPI : 3 wire Serial) and works in slave mode. The register width is 32bit. This 32bit register is used to sync between SPI master(Quark) and SPI slave (FPGA). A special format is defined in this 32 bit register. Refer to SPI register structure section for detail.

For the SPI avalon-MM interface, refer to embedded_ip document for detail.

The “Insert synchronozers” option must be selected for eliminating metastability. This metastability brings when SPI IP block use local 50M Hz clock to asynchronously sample SPI clock and data. Note this option also limits the SPI speed to 8M Hz.

Figure 5-1 SPI Module setting

5.2 UART_n

UART_n module is inside system.qsys. It’s a Quartus IP block(Altera 16550 UART), this IP block is controlled via Avalon-MM interface. For the 16550 UART avalon-MM interface, refer to embedded_ip document for detail.

There are 6 UART module in the design, 2 for RS 485, 4 for RS 232. The FIFO depth is set to 256.

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Figure 5-2 16550 UART Setting

5.3 Avalon_transaction

Avalon transaction module is written by RTL and wrappered in Qsys as a component. Its main function is receiving the

command from Quark MCU via SPI, resolving these command, reading/writing UART avalon registers.

5.3.1 Typical UART control flow via SPI.

A typical UART write flow is:

1. Quark send write command via SPI which contain which UART port is allocated and what data is to be send out.

2. Avalon transaction module resolve the command, write the data to proper UART avalon register, then start the UART

output by setting UART avalon register.

A typical UART read flow is:

1. Quark send read command via SPI which contain which UART port is to be read.

2. Avalon transaction module resolve the command, read the data from UART avalon regsiter and put it into SPI register.

3. Quark send another dummpy SPI command, to get the read data from SPI register.

The typical flow is slow especially when continue read data from UART FIFO:

1. A typical UART read flow to check if there’s any data available in FIFO, this takes 2 SPI transaction.

2. A typical UART read flow to read out the UART data, this takes another 2 SPI transaction.

3. To speed up the speed, in the example we add some module to support continues read from UART FIFO.

5.3.2 State Machine

The actual State machine provide more function rather than simple UART read and write.

State Name Description Action

st_idle Idle state Move to st_wait_rrdy after 2 cycle

st_wait_rrdy Polling SPI rrdy register Move to st_cmd once rrdy is active

st_cmd Resovling SPI command

st_dma_rd Continous read from UART FIFO Move to st_dma_valid if there’s valid data in UART FIFO

st_dma_valid Assemble valid data to MISO register Move to st_spi_write

st_uart_read UART read, copy to MISO register Move to st_spi_write

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st_spi_write Write MISO data to SPI register

st_uart_write UART write command Move to st_idle once data is written to UART IP

Figure 5-3 Avalon Transaction State Machine

5.3.3 SPI register structure

SPI register refers to MISO register(32 bit) and MOSI register(32 bit).

MOSI field Bit

Command [31:30] [7:0] UART controller command

“01””xxxxxxxx”: UART controller write

“10””00”: UART controller read

“10””FD”: A dummy SPI command, use to sync MISO resgier

“10””FE”: Continues read command

“10””FF”: Read a special interrupt register, indicating which UART has valid data.

Address [27:16] UART register address

0x000 – 0x1ff UART0

0x200 – 0x3ff UART1

0x400 – 0x5ff UART2

0x600 – 0x7ff UART3

0x800 – 0x9ff UART4

0xA00 – 0xBff UART5

For continues read, only [27:25] is meaningful

Data [15:0] UART data

Valid when writing data to UART controller

Ignored during reading data from UART contoller

MISO field Bit

Command [31:18] Fixed as 0x“2000”, lead code

data [17:2] For UART read : 16 bit from UART IP register

For interrupt read : [17:8] is fixed to 0; [7:2] refer to interupt of 6 UART module

For continous read : [17] If the data is valid ; [16:2] data from UART FIFO

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Dummy [1:0] Fixed to Zero

5.3.4 Lead code

Note the MISO register may right shift 1 to 2 bit when arrived at quark MCU due to the 2 synchronozation stage added in SPI

IP. That’s why the lead code is used.

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6 Verification Plan

This example is first tested on Max10 Evaluation board, shown as below.

Figure 6-1 Evaluation Board Test

Then the design is migrated to 10M02 chip and tested on RTU board and PC RS232 port. Finally the design is tested on RTU board and various UART sensors.

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7 Revision History

Error! Reference source not found. shows the revision history for the Reference Design Document: SPI2UART Design Example.

Table 7-1 Reference Design Document Revision History

Version Date Change Summary

1.0 Sept. 2016 First release of this Reference Design Document.

1.1 June. 2017 Update Avalon transaction part