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6/9/1010 Ed Hungerford 1

COMET Comments---

Readout for the COMET e Tracker

Ed HungerfordUniversity of Houston

(for the COMET Collaboration)

With special THANKS tomy sponsors of this talk

Satoshi MiharaManobu TanakaMasaharu Aoki

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Introductionto

COMET

• COMET (Phase I) is a search for coherent, neutrino-less conversion of muons to electron (μ-e conversion) at a single event sensitivity of 0.5x10-16

• The experiment offers a powerful probe for new physics beyond the Standard Model.

• COMET will be undertaken at J-PARC. Phase I (COMET) uses a slow-extracted, bunched 8 GeV proton beam from the J-PARC main ring.

• A proposal was submit to J-PARC Dec. 2007, and a Conceptual Design Report submitted June 2009. COMET now has Stage-1 approval from the J-PARC PAC (July 2009), and is completing R&D for the TDR.

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• Electron ResolutionMinimal Detector Material – Thin, Low Z Vacuum EnvironmentREDUNDENT measurements of the electron track

• RatesUp to 500 kHZ single ratesLarge channel countR/O timing (~1 ns) and analog information

• Dynamic Range Protons 30-40 times Eloss for MIP Pileup and saturation Maintain MIP track efficiency

• Low-Power, Low-foot print electronicsHeatSignal Transmission through the vacuum wallsNoise

• Robust measurements • REDUNDANCY (Redundancy, Redundancy, Redundancy)

Ambiguous hits, dead channels, accidentalsReconstruction of ghost tracks

Design Considerations for COMET (and generally all high precision

measurements of zero)

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μ→eγ and μ-e Conversion

• μ→eγ : Accidental background is given by (rate)2. To push sensitivity the detector resolutions and timing must be improved. However, (in particular photon detection) it would be hard to do better than MEG. The ultimate sensitivity of MEG is about 10-14 (with a run of 108/sec).

• μe conversion : Improvement of a muon beam is possible, both in purity (no pions) and in intensity (muon collider R&D). Higher beam intensity can be used with present timing technology because no coincidence is required.

Background Challenge Beam Intensity

• e accidentalsgamma

resolutionlimited

• μ-e conversion

beame resolution

reconstructionLess limited

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COMET at J-PARC

•Modification of MECO/MELC•Requires slow extracted, pulsed beam ~8 GeV•Mu2e at FNAL is another MECO resurrection

B(Al) e + Al <10-

16

Pulsed Proton Beam

Source

Transport targetelectron Transport

Detection5 m

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Target and Detector Solenoids

•a muon stopping target, curved solenoid,tracking chambers, and a calorimeter/trigger and cosmic-ray shields.

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Comparison to MECO

• Proton Target - tungsten (MECO) - graphite (J-PARC)

• Muon Transport - Magnetic fields and solenoids are different. - Efficiency of the muon transport is equivalent

• Spectrometer - 1011 stopping muons/sec -Straight Solenoid (MECO) >500 kHz/wire - Curved (COMET) ~1kHz /wire• Planer Tracker

MECO

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COMET Tracker and Calorimeter Background

Total Tracker Rates/plane 600 kHz

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Muon-to-Electron (μ-e) Conversion Lepton Flavor Violation

Lepton Flavor Changes by one unit

Coherent Conversion

μ- + A → e-+ A

μ Decay in Orbit (DIO)

μ- → e- ν ν

Nuclear Capture

μ- + A →ν+ [N +(A-1)]

nucleus

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Background Rejection (~107 s) (preliminary)

Backgrounds Events Comments

(1)

Muon decay in orbitRadiative muon captureMuon capture with neutron emissionMuon capture with charged particle emission

0.05<0.001<0.001<0.001

230 keV resolution

(2)

Radiative pion capture*Radiative pion captureMuon decay in flight*Pion decay in flight*Beam electrons*Neutron induced*Antiproton induced

0.120.002<0.02

<0.0010.08

0.0240.007

promptlate arriving pions

for high energy neutronsfor 8 GeV protons

(3)Cosmic-ray inducedPattern recognition errors

0.10<0.001

10-4 veto efficiency

Total 0.4

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Tracking Array

5 Planes – 4 Arrays per plane

Each plane arranged in an

x,x’,y,y’ geometry of arrays

Each array composed of 13 straw

units of 16, 5mm diameter

straws

•16 straws/unit

•208 straws/array

•832 straws/plane

•4160 straws/detector

Mounted double-array

Unit

1.2 m

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Manifold

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Flex Ribbon Cable through Manifold to FEB Fused HV

15 ns LRC

Filter/channel

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Readout Architecture

•On-Detector amplification and digitizing – events passed by optical fiber in serial to an external DAQ (Parallel transfer is also possible)

• Electronics based on CMOS to conserve space and power (<65 Mw/ch) – radiation damage is not a problem

• Mounted on the detector frame

• A (MECO) system has been previously prototyped and demonstrated

• COMET Data rates are reasonable

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COMET Tracker FE Organization

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Straw Tubes Number of Straws

Readout (TDC)

Readout (ADC)

Per Array (13 x 16) 208 208 208

Per Plane (4 Array) 832 832 832

Per Detector

5 Planes (MECO 18)

4160 4160 4160

Manifold

(unit)

Array Plane Detector

PA(16) 1 13 52 260

Digitizer(16) 1 13 52 260

ROC 1/4 1 5

Module Controller

1/5 1

Assuming:60-125MHz clock and 10-20 clock ticks for an event (160 ns)(10-20+ 11) x 4x5x1.5 words for an event and 16 bits for a word1k/s event rate

The total data rate is ~10-15 Mb/s with zero suppression

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An ExampleThe MECO Readout Architecture

To External DAQ

Fro

m A

node

Wir

e

Sequencer

Separated PAAnd Digitizer

Plane ID for readout

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•6/9/1010 •Ed Hungerford •17•05-30-09• Ed Hungerford

for the COMET collaboration

•17

MECO Prototype

FEATURES•The number of data transfer lines is 24 (16 data + 6 control)•A system clock is regenerated by the local buss sequencer•A trigger input is associated with readout units•A trigger reset counter determines the data time stamp•A system reset to return to standard operating conditions•A slow control buss for control and monitoring•Low voltage power of +3.3V(300A) and -3.3V (100A)•Total Power < 1.8 kW (PA and Digitizer only)

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Drift Simulation

Gas – 80 %CF4/20% C6H10 Velocity - 8.5 cm/μsDrift Time - 45 ns

Trajectory

Wire

Trajectory

Wire

Pos

itio

n A

lon

g Y

(cm

)

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Measurements and Simulations

Simulated Anode

signalSimulated Charge

15 ns Filter

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The MECO Prototyped System

• A front-end board was developed to test the ASD-4 and a driver board is used to adapt the LVDS output to our lab CAMAC TDC.

Elefant Chips (2 x 8 channels)

Mother Board with FPGA

Memory and PCI controller

Digitizing Boards

• The Digitizing Board layout is completed, tested, and the digitizing ASIC designed.

FEB Board Connected by flex cable

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32 Channel MECO Prototype

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Specifications for COMETASIC preamp

Parameter Name Value Note

Polarity BipolarPositive input for

Colorimeter

Channel number 16Cover 8 cm with 5-mm

straws

Linear range <60 fC

Input capacitance 20 pF

Equivalent Noise Charge

0.5 fC

Peaking time 100 nsAmplitude

measurement

(250-ns signal width)

Coupling AC

Timing resolution <2 ns

Power consumption <5 mW/ch

Test input Yes

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ASIC Digitizer

• Digitizer ASIC Design based on the ELEFANT ASIC used in BABAR (8 channels/ASIC)

Work in collaboration with design engineers at LBL

Rescale ASIC to 0.25 m technology and 3.2 V interfaces

Solves identified problems with the ELEFANT design

Change clock frequency (20-60 Mhz)

Change from waveform sampling to time-slice integration

Increase ADC bits to 10

• ~5 s Latency, self or external trigger

• Power Consumption 65 mW/channel (Total Power 1,650 W)

Design (LBL Engineer) $518K; Fabrication (2prototypes) 2 x $45k;

Preproduction samples $50k; Production and packaging $231k, Testing $42k

=> $931k + 37% contingency

Several more modern Waveform (ADC Sampling) ASICS designs

are Possible for COMET -- e.g. Belle, PSI designs, ATLAS, etc

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Digital chip Redesign

• Benefits: reduce noise, simplify the system design, better technology, lower power consumption, lower system cost. Prediction of the production cost is ~$8-15 per channel.

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Items Upgraded Digitizer

Channel per Chip 8

System Input Clock 7.5~15MHz sine wave differential

PLL System Clock Divider 4 2 1

System Frequency 30~60MHz 15~30MHz 7.5~15MHz

ADC sampling Clock System Clock

ADC Resolution 8 bits 9 bits 10 bits

ADC Implementation Pipeline ADC

TDC DLL (PLL) Clock 30~60MHz (PLL divided Clock)

TDC resolution 0.26 to 0.52ns LSB

TDC Width (combine with PLL) 6 bits 7 bits 8 bits

TDC Implementation DLL (PLL)

Noise performance Digital feed back to the analog channel less than 0.5 LSB

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MECO Digitizer chip specs

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Elefant II ASIC

Time and amplitude samples stored together in a latency pipeline

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A More Modern DesignCDC – Belle Central Drift Chamber

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Other ExamplesReadout of ATLAS TRT

• Based on two ASICs: front-end + digitization• ASDBLR

– Front-end, 8-ch– Separate preamps

• Track detection• TR photon detection

– Ternary outputs• DTMROC

– Digitization, 16-ch– TDC + FIFO + Serialization– Each beam bunch has one slice in FIFO– Control and thresholds to ASDBLR

• Power consumption:

40 mW/ch

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ROC Board Design

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• Each ROC has a FPGA to control the readout sequence from the Elefant II chips.

• Data are stored on the board temporarily in the dual-port RAM.

• Configurations, like the number of channels connected to this board, readout mode (sparse mode, zero-suppression mode, etc.), are configured through the I2C bus.

CPLD

RJ-45 RJ-45

FPGA

Virtex-II pro

V3.3 REG

V2.5 REG

Pwr Conn.

Transmitter

CONN.

Dual Port

RAM

PROM

RJ-11

I2C

I2C

High SpeedSerial Bus

ClockTriggerReset

Distribution

To FE Board

CONN. CONN. CONN. CONN. CONN.

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Fast Control Signal

• Reset, Trigger, and Reference clock are provided by DAQ system (Trigger and Fast Control Fan-out ).

• These are transmitted as differential signals (LVDS).• Reference clock is 10MHz with reasonable jitter. On the module

controller or ROC, this clock frequency will be divided by PLL to the sampling frequency (40-60MHz) with much smaller jitter (~200ps) to satisfy ADC requirement.

• Event numbers are embedded in the trigger signal (real time trigger signal followed with the number) .

• The Control module feeds the fast control signal to each ROC Box through 4 pairs low skew differential, shielded cable. No matter how far the ROC is from the module controller, all these Fast Control lines must have the same length to reduce the time skew. This will also ensure the timing accuracy for the whole system.

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Data Transfer

• Data transfer from ROC to the module controller uses shielded twisted pair cable (low skew <150ps /10m).

• From the module controller, data passes feedthrough to the Event Builder of DAQ: differential copper wire or optic fiber.

• Differential copper wire:

• Easy to install from the vacuum wall.

• Can be 100Mb/s (CAT-5e) or 200Mb/s (CAT-6). Up to 100m

• Full bandwidth is not used due to protocols (handshaking).

• Cheaper.

• Optic fiber:

• Penetrations through the vacuum wall? Hermetic feed through

exits. No engineering experience.

• Fast. Can be ~Gb/s. ~km long.

• Radiation hardness of the transceiver should be considered.

• Costs more.

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Data Package to the Event Builder

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Squencer Header

Sequencer Trailer 1

ROC Header

ROC Trailer 1

Channel Header

Channel Trailer

Data

Data

Data

Repeat Channels

Repeat ROCs

Sequencer Trailer 2

0000 Sequencer ID Event ID

0010 ROC ID Event ID

0110 Channel ID Event ID

Data 00111 Data 1

Data ...0111 Data ...

Data n-20111 Data n-1

1110

1010

Channel ID DWord Length Event ID

ROC ID Event ID

1000 Sequencer ID Event ID

1001 Sequencer ID DWord Length

31 28 27 25 24 23 22 20 19 12 11 0

FE Header 0100 FE ID Event ID

FE Trailer 1 1100 FE ID Event ID

Repeat FEs

FE Trailer 2 1101 FE ID DWord Length

ROC Trailer 1 1011 ROC ID DWord Length

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2nd Coordinate Readout

Possible Methods of 2nd Coordinate Measurements in Wire Detectors

1) Induction on the cathodea) Strips (pads)b) Delay lines parallel to the anode wires

2) Anode readouta) Charge division on a resistive anode (NIM A479(02)591) or

Cathode b) Signal timing between the straw ends c) Signal rise time

Tracking with multiple hits in the detector planes can produce ghost trajectories. A 2nd readout might reduce ambiguities.

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Charge Division Readout(IEEE 42(95)1430)

Signal Division

L/L ~0.6%

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Charge Division Issues

Charge division might provide a 2nd coordinate readout with resolution on the order of L/L 1%; BUT 1) The resolution deteriorates with background rate 2) Reducing the integration gate, implementing base line restoration reduces the collected charge (resolution)3) Maintaining calibration requires special data runs and pulser inputs (automated)4) Careful design of all electronics to reduce noise and termination of lines (frequency dependence) 5) Precision wire resistance and analog preamp 6) Shaping amp is a compromise between noise reduction (very sensitive) and rate handling5) Both ADC and TDC readout7) Charge integration within a time gate

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Delay Line Readout NIM A479(02)591

L = 6.5mm1.7 m long drift-cell

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Straw Delay Line

~1m straw delay line is presently under construction Strip width is 1mm spaced by 1mm Expected time delay for 1m is 45 ns one-way.Differential readout to remove common mode propagation

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Delay Line Issues

Delay Line Timing might provide a 2nd coordinate readout with resolution on the order of L ~ 5 mm. The time sum equals propagation delay + drift time, better signal stability, and anode wire hit ID’ed. BUT 1) Requires additional material2) More difficult to construct3) More electronics to build and install in a limited space4) Capacitive and inductive coupling between channels5) Careful electronic design 6) Calibration

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Summary

• COMET is a Phase I search for coherent, neutrino-less conversion of muons to electron (μ-e conversion) at a single event sensitivity of 10-16

• The experiment offers a powerful probe for new physics beyond the Standard Model.

• The experiment will be undertaken at the J-PARC NP Hall using a slowly-extracted, bunched proton beam from the J-PARC main ring.

• The Experiment is developing a TDR and refining design details. The experiment has completed a CDR and has Stage-1 approval of the J-PARC PAC.

• The electronic readout of the tracker (and calorimeter) is challenging, requiring new ASIC development that have low power, excellent timing, reasonable resolution, and rate handling, and are robust.

• The system design requires on detector digitization, storage, buffering, and latency.

• The event builder must reconstruct events from asynchronous buffer reads

• We need expert engineering experience with the technical designs