Types of Pentium Processors

• Pentium

• Pentium MMX

• Pentium Pro

• Pentium II

Standard Pentium Parts

BIUBus

InterfaceUnit

8K Code Cache

8K Data Cache

Instruction Prefetch Buffer & Decode Unit

ALUALU

Registers

FloatingPointUnit

Branch Predictor

Unit

To RAM

Pentium MMX Technology

• Designed for better multimedia abilities.

• Bigger caches for more readily available code & data

• TLB’s for faster addressing

• MMX unit for multimedia functions.

Pentium MMX

BIUBus

InterfaceUnit

Instruction Prefetch Buffer & Decode Unit

ALUALU

Registers

FloatingPointUnit

Branch Predictor

Unit

To RAM

8K Code Cache

8K Data Cache16K Data Cache

16K CodeCacheThe caches are

bigger, each with a Translation Lookaside Buffer (TLB) which convert the address codes used by the caches to a kind that the processor can use.

BIUBus

InterfaceUnit

8K Code Cache

8K Data Cache

Instruction Prefetch Buffer & Decode Unit

ALUALU

Registers

Branch Predictor

Unit

To RAM

Pentium MMX unit

FloatingPointUnit

MMX

The MMX unit does 57 functions for multimedia.It uses some of the registers in the FPU, which are bigger than the ones in the ALU’s. This allows the MMX unit to function faster than the main processor.

The Pentium Pro Processor

• Designed to minimize downtime of the processor, thereby speeding up the CPU.

• Adds a Level 2 Cache.

• Adds a BTB.

• Adds a ROB.

ROB

The Pentium Pro Level 2 Cache

BIU

8K L1 I-Cache

8K L1 D-Cache

IPB & Decode

Unit

ALU

ALU

FPU

BranchTargetBuffer

L2Cache

JEU

D/E

RU

SB

The L2 Cache is another way to have data immediately available for the processor.

ROB

The Pentium Pro ROB

BIU

8K L1 I-Cache

8K L1 D-Cache

IPB & Decode

Unit

ALU

ALU

FPU

BranchTargetBuffer

L2Cache

JEU

D/E

RU

SB

The ROB is like a pool for processing.

Pentium II Processor

• Combines the MMX technology with the Pro setup.

• The L2 Cache, however, is not integrated into the CPU in the same way.

ROB

The Pentium II L2 Cache

BIU

16K L1 I-Cache

16K L1 D-Cache

IPB & Decode

Unit

ALU

ALU

MMX

BranchTargetBuffer

L2Cache

JEU

D/E

RU

SB

The L2 relocation is cheaper to make, but creates a slower connection to the processor.

FPU

ROB

The Pentium II L1 Caches

BIU

16K L1 I-Cache

16K L1 D-Cache

IPB & Decode

Unit

ALU

ALU

MMX

BranchTargetBuffer

L2Cache

JEU

D/E

RU

SB

This is compensated for by increasing the L1 caches to 16K.

FPU

ROB

The Pentium II MMX module

BIU

16K L1 I-Cache

16K L1 D-Cache

IPB & Decode

Unit

ALU

ALU

MMX

BranchTargetBuffer

L2Cache

JEU

D/E

RU

SB

The Pentium II also has the MMX module near the FPU.

FPU