TYao RF TX Circuits

8/14/2019 TYao RF TX Circuits

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RF Transmitters

Architectures for Integration and

Multi-Standard Operation

Terry Yao

ECE


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Outline Motivation Transmitter Architectures

Current Trends in Integration State-of-the-Art Examples (3)Direct Conversion2-Stage

Future Challenges References


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Motivation

Increase in demand for low-cost, small-

form-factor, low-power transceivers

Proliferation of various wireless standardspushes for multi-standard operation

CMOS is well suited for high levels of

mixed signal radio integration [2] End goal: a low cost single chip radio

transceiver covering multipleRF

standards


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RF Transmitters

Function

Modulation

Frequency

Translation

Power

Amplification

Performance

Specification

Accuracy

Spectral

Emission

Output

Power Level


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Transmitter Architectures

Mixer-BasedDirect Conversion (Homodyne)2-Stage Conversion (Heterodyne)

Both architectures can operate with constant and

non-constant envelope modulation Well-suited for multi-standard operation

PLL-Based Show promise with respect to elimination of

discrete components Fundamentally limited to constant-envelope

modulation schemes not suitable for multi-standard operation


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Direct Conversion Attractive due to simplicity of the signal path suitable

for high levels of integrationOutput carrier frequency = local oscillator (LO)

frequency Important drawback: LO disturbance by PA output


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Direct Conversion LO Pulling Noisy output of PA corrupts

VCO spectrum -injection

pulling or injection locking

VCO frequency shifts towardfrequency of external stimulus

If injected noise frequency

close to oscillator natural

frequency, then LO output

eventually locks onto noise

frequency as noise level

increases


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Transmitter Architectures Direct Conversion LO Frequency Offset Technique

LO pulling can be alleviated by moving the PA outputspectrum sufficiently far from the LO frequency

LO offset can be achieved by mixing 2 VCO outputs 1 and2 and filtering the result; leading to a carrier frequency of1+ 2, far from either 1 or 2

BPF1 must have high selectivity to suppress spurs of theform m1+m2 to avoid degradation in quadraturegeneration and spurs in the up-converted signal


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Transmitter Architectures 2-Stage Up-Conversion

Another approach to solving the LO pulling problem Up-convert in 2 stages so PA output spectrum is far from VCO

frequency Quadrature modulation at IF (1), up-convert to 1+ 2 by

mixing and filtering

BPF1 suppresses the IF harmonics, while BPF2 removes theunwanted sideband 1- 2

Advantages: no LO pulling; better I/Q matching (lesscrosstalk between the 2 bit streams)


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Current Trends in Integrated

Transceivers Both direct and 2-stage architectures are used(with modifications for better integration andmulti-standard operation)

Direct architecture achieves a low-costsolution with a high level of integration[3],[4],[6],[8]

2-stage results in better performance (ie.reduced LO pulling) at the expense of increasedcomplexity and hence higher cost ofimplementation [5],[7],[9],[10],[11]

Transmitter and receiver designed concurrentlyto enable hardware and possibly power sharing


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Direct Conversion Example

Homodyne architecturefor better integration,lower cost and lowerpower consumption

Uses on-chipquadrature VCO andbuffers to improvefrequency purity

On-chip VCO minimizesradiation leakage from

strong PA output backto core oscillator Buffers isolate sensitive

VCO circuit from high-power, large voltage orcurrent swing circuitblocks

A 5-GHz CMOS transceiver frontend chipset [6]


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2-Stage Conversion Example A Dual Band (GSM 900-MHz/DCS1800 1.8-

GHz) CMOS Transmitter [7] Exploits similarities of

GSM and DCS1800standards (modulation,channel spacing,

antenna duplexing) toreduce hardware

2 quadratureupconverters driven by450MHz LO to generatequadrature phases of IF

signal IF signal routed to

single-sideband mixersdriven by a 1350MHz LO,producing either 900MHz

or 1800MHz signal


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Future Challenges

Implementation of highly integrated radiotransceivers will remain as one of the greatestchallenges in IC technology

New architectures and circuit techniques shouldbe investigated for higher flexibility in CMOStransmitters

Further improvement needed in the design ofon-chip inductors, filters and oscillators in astandard CMOS process

Continued improvement in high frequencyCMOS device modeling and simulation


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References[1]. B. Razavi, RF Transmitter Architectures and Circuits, IEEE CICC, pp. 197-204, 1999.

[2]. A. Abidi, et. al., The Future of CMOS Wireless Transceivers, ISSCC, pp. 118-119, Feb. 1997.[3]. J. Rudell, et. al., Recent Developments in High Integration Multi-Standard CMOS Transceivers

for Personal Communication Systems, IEEE 1998.

[4]. S. Kim, et. al., A Single-Chip 2.4GHz Low-Power CMOS Receiver and Transmitter for WPAN

Applications, IEEE 2003.

[5]. J. Weldon, et. al., A 1.75-GHz Highly Integrated Narrow-Band CMOS Transmitter With

Harmonic-Rejection Mixers, IEEE Journal of Solid-State Circuits, Vol. 36, No. 12, Dec. 2001.

[6]. T. Liu, et. al., 5-GHz CMOS Radio Transceiver Front-End Chipset, IEEE Journal of Solid-State

Circuits, Vol. 35, No. 12, Dec. 2000.

[7]. B. Razavi, A 900-MHz/1.8-GHz CMOS Transmitter for Dual-Band Applications, IEEE Journal of

Solid-State Circuits, Vol. 34, No. 5, May 1999.

[8]. R. Point, et. al., An RF CMOS Transmitter Integrating a Power Amplifier and a Transmit/Receive

Switch for 802.11b Wireless Local Area Network Applications, IEEE RF IC Symposium, pp 431-

434, 2003.

[9]. S. Aggarwal, et. al., A Highly Integrated Dual-Band Triple-Mode Transmit IC for CDMA2000

Applications, IEEE BCTM 3.1, pp 57-60, 2002.

[10]. X. Li, et. al., A CMOS 802.11b Wireless LAN Transceiver, IEEE RF IC Symposium, pp. 41-44,

2003.

[11]. S. Mehta, et. al., A CMOS Dual-Band Tri-Mode Chipset for IEEE 802.11a/b/g Wireless LAN,

IEEE RF IC Symposium, pp 427-430, 2003.

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TYao RF TX Circuits