Two-dimensional hydrodynamic simulation of submicrometer dual gate MODFETs

So/M-SRI& Ekrronics Vol. 38. No. 4. pp. 917-929. 1995 Copyright i‘ 1995 Elsevier Science Ltd

0038-1101(94)00171-5 Printed in Great Britain. All rights reserved 0038-I 101195 $9.50 + 0.00

Pergamon

TWO-DIMENSIONAL HYDRODYNAMIC SUBMICROMETER DUAL GATE

KHALED SHERIF’, ADEL REFKY’, TAREK SHAWKI’, GEORGES SALMER’

SIMULATION OF MODFETs

OSMAN EL-SAYED? and

‘Institut d’Electronique et de Microelectronique du Nerd, UMR CNRS 9929, UniversitC des Sciences et Technologies de Lille, 59655 Villeneuve d’Ascq, France and ‘Electronics and Telecommunication

Department, Faculty of Engineering, Cairo University, Cairo, Egypt

(Received 16 June 1993; in revised form 28 July 1994)

Abstract-A hydrodynamic energy model is efficiently used for the simulation of a dual-gate lattice matched MODFET at room temperature. The results obtained give a good insight of the device physics and permit through the systematic use of the model to predict the equivalent circuit elements. A simplified model is suggested where these elements as well as d.c. and a.c. characteristics could be precisely characterized depending only on electrodes potential.

NOTATION

unit vector in the .Y direction bottom of the conduction band deep DX center level donor ionization energy Fermi level for electrons reference energy level Planck’s constant Boltzmann’s constant electron equivalent effective mass electron concentration total incorporated donor density ionized donor density momentum in the x direction G mzv, electronic charge absolute lattice temperature equivalent electronic temperature electron velocity average potential energy measured from the bottom of the local conduction-band r minimum average kinetic energy of an electron permittivity electrostatic potential electron mobility total-energy relaxation time average total electron energy = IZ? + Up electron affinity

1. INTRODUCTION

For a long time, it has been well known that dual gate field effect transistors can be useful in a variety of microwave circuits with very interesting performance. Among these applications, there are amplifiers[l], phase shifters[2] and up or down converters[3-51.

This device takes advantage of its very compact structure that allows one to integrate very closely two independent field effect transistors with very small parasitic elements. When used as an amplifier, it has all the advantages of cascade configuration: high

output impedance and small feedback capacitance. Dual gate mixers can present very interesting performance such as high local oscillator input signal isolation and good conversion gain.

On the other hand, single gate MODFETs have shown excellent performance as a very low noise device (1.3 dB at 94 GHz) with current gain cut-off frequencies higher than 300 GHz[6]. However, only a small number of studies have been devoted to dual gate MODFETs.

For the design of microwave circuits, accurate models of active devices are needed. However, the equivalent circuit of dual gate MODFETs is very complicated and it is very difficult to evaluate the dependence of its elements on d.c. bias and technological parameters. Moreover, the exact topology of the equivalent circuit is subject to controversy and it may be interesting to derive a simpler configuration. Although structural optimization is wished, the huge number of technological parameters will hinder the effectiveness of experimental approaches.

In this context, only a physical simulation can give an accurate knowledge of device behaviour and determine its dynamic characteristics and elements of the equivalent circuit. In this field, 2D hydrodynamic models[7-91 constitute an interesting solution; they need less computational effort than Monte Carlo simulations[lO, 111, and they are more accurate than quasi 2D models[l2]. Such models have been devel- oped for MESFETs[8] and conventional MOD- FETs[9]. In this context, we have used the later model[9] in order to treat dual gate MODFETs.

In the first part of this paper we will recall the main features of the model and the main problems encoun- tered in conceiving this simulation tool. Then, we will present the main results obtained concerning the physical behaviour of the device and mainly the

917

918 Khaled Sherif et al.

influence of d.c. btas (I’,,,. V 825, Vds). Finally, we will show the dependence of the equivalent circuit elements (transconductances, capacitances, .) on d.c. bias.

2. MODEL DFSCRlPTlON

The main physical basis of this model has been presented elsewhere[9,13]. It is a hydrodynamic single equivalent electron gas energy model which is based on the particle, momentum and energy t conservation equations Boltzmann transport equation:

L’ +n --r-=n V(q +I)-

p(5) (

+uIVlogm*(<) ‘aY >

a< dr=r+!V(cp+x-5)

average electrons derived from the

(1)

(2)

(3)

(with the other equation, which is similar to (2) for the momentum conservation in the y direction), in addition to Poisson equation:

V. (cVcp) = -q (NA - n).

The average kinetic energy w is given by:

1 3 w =-m*v2+-k T

2 2 B et:1

and the number of ionized donors N & by:

allowing to take into account the existence of DX centers considered as a single deep donor level located at 160 meV below the conduction band L minimum[ 141.

The main assumption in this model is that all the physical parameters ( p, T,, T<) are taken to be dependent on the electrons average total energy 5 in the material and that the dependence can be obtained from steady three valley Monte Carlo simulations performed in our laboratory. The total average energy (kinetic plus potential) constitutes a relevant quantity of our model; it is necessary to introduce it in order to be able to treat the whole carrier dynamics and mainly the consequence of carrier transfer in the upper valleys with a single equivalent electron gas model. Note that all the main physical phenomena are included because the dependence of the

physical parameter are deduced from Monte Carlo simulation.

Several other assumptions were introduced and discussed by Shawki et a1.[9,13]. In this work and for simplification purposes, we neglect:

l quantization effects in the quantum well assuming 3D electrons;

l rate of heat flux by thermal electron conduction assuming no cooling;

l spatial gradients in the momentum relaxation equation thus eliminating inertial effects;

l degeneracy of electrons.

At the heterojunction, the variation in composition is assumed to occur gradually (typically over 40 A) in order to limit the gradient of electron affinity.

Conventional boundary conditions are applied:

l Neumann boundary conditions (BCs) on free surfaces.

l Dirichlet BC’s are assumed on ohmic contacts: T, = T,,, n = N,, v, is given.

l For Schottky barrier: Veff = Vgs - (P,, , and conduction current is taken equal to zero.

l Surface effects: introduction of equivalent de- pletion electric field normal to the surface.

The above equations are discretized in space using finite differences. A non uniform mesh is used with a minimum mesh size of 2OA in the y direction and 100 8, in the x direction. Poisson’s equation is solved using the matrix double sweep method, which is a modified LU technique[ 151. The energy and continu- ity equations are solved by the SOR-Newton method. The discretization in time is accomplished using variable time steps between 0.5 and 2.5 fs. In all cases, a transient simulation is carried out until steady state is reached: the small signal parameters are extracted either by the incremental charge partitioning method or transient excitation followed by FFT[8,16].

This model initially elaborated for the simulation of conventional single gate MODFET[9,13] is used to treat dual gate MODFETs. Not only has a second gate been introduced with boundary conditions similar to those used for the first one, but also various kinds of intergate zones have been considered. Of course, only the internal part of the device is mod- elled, but due to the existence of the second gate and the inter gate zone, the lateral dimension mcreases by about 50-60%. Then the number of points are typically 7500 instead of 3000 for a single gate MODFET. Thus, the computational effort has be- come more important and various techniques for reducing the computational time presented in [16] were extremely useful.

The simulations were done on an IBM-3090-600E machine with vectorial processors. For the device simulated, we had 12 cpu min for 1 ps of simulation time as a performance figure. This simulator gives a record time of 1 cps min/l ps for a classical single gate MODFET at 300 K[l9].

Hydrodynamic simulation of dual gate MODFETs

0.2 Km 0.3 pm 0.5 pm 0.3 pm 0.3 pm I 1 I I I 1 , I

Gate I Gate 2 r-1

Drain

GaAs

919

: 4

paler 40A

t -z

z

I

Fig. I. Typical structure of dual gate MODFET.

3. PHYSICAL BEHAVIOUR OF DUAL GATE MODFETs MODFETs. Typical device structure is presented in

3.1. Device considered

The above model is the physical behaviour

(a)

Fig. 1. It consists of a 360 A n +-doped AlGaAs layer (lO’*cm-‘) followed by a 40 bi undoped AlGaAs

used in order to predict spacer then an undoped GaAs layer. The correspond- of 0.3 pm gate dual gate ing low field mobilities are 1750, 4000 and

SOWlX Gate I Gate 2 Drair

Gate 1 bias (V) = 0.0

Gate 2 bias (V) = I.0 GaAs

Drain bias (V) = 3.0

f

40A

1

T 2 8 I

(b) SOlIKe Gate I Gate 2 Drain

Gate I bias (V) = 0.4

Gate 2 bias (V) = I.0 GaAs


Fig. 2. Typical current Row lines (50 mA/mm line) in a dual gate MODFET for two values of V,,,: (a) 0, (b) 0.4 V. - V,, = 3 V; V,?, = I V.

SSE ,X,&L


f %

40A f

T 72 E 1

40A 1

T

0) 0.2 p’m 0.3 p 0.5 pm 0.3 pm 0.3 pm

I I I 1 I I I 1 1 I


Gate 2 bias (V) = 1 .O

Drain bias (V) = 3.0 0

40A 1

T

Potential (V)

(b) Gate 1


Potential (V)

Gate 2 Vratn

ain Gate 1 Gate 2

Potential (V) Gate 1 bias (V) = 0.4



Fig. 3. hflUenCe of v,, . on equipotential contours in a dual gate MODFET (V,, = 3 V and Vgzq = I V): (a) V,,,= -0.4V; (b) V,,,=oV; (c) VP,,= +0.4v.

Hydrodynamic simulation of dual gate MODFETs 921

7500 cm2/V . s respectively. The GaAs layer thickness considered is limited to 1000 A in order to save

behaviour. Two intergate distances (0.2 and 0.5 pm) have been considered. In fact, as it will be seen later,

computational time; in a preceding study[ 181, we have this intergate distance has been chosen large enough shown that it is not necessary to consider thicker in order to allow for the cooling of carriers again layers in order to obtain a good description of device before reaching the second gate; in practice this

(a) Source Gate 1 Gate 2 Drain

z- z

40A _F.

T

40A

p

T 4 8 ,o

I AlGaAs

I GaAs I II


Gate 2 bias (V) = 1.0 u Drain bias (V) = 3.0

_. llll, I I111111 I IT7111 I I I

Potential (V)

Source Gate 1

I AlGaAs R

I GaAs \ \ \I\\\\ d




Potential (V)

Source Gate 1 _“... . Drain --

AlGaAs

Gate 1 bias(V) = 0.4



Potential (V)

Fig. 4. Influence of Vs,. on equienergy contours (given in eV) in a dual gate MODFET (V,, = 3 V and VP,,= IV): (a) Vs,_= -0.4V; (b) V,,,=OV; (c) v,,,= +0.4V.

922 Khaled Sherif ef al.

distance can be larger, but the supplementary zone planar structure. It has been previously shown[l] that (not considered in this work) acts as an additional to consider planar structures when neglecting surface intergate resistance. potential is equivalent to considering a recessed one

The device considered and simulated here has a with edges of recessed zones very close to the gate.

(a) 0.20 v 0.30 p 0.20 p 0.30 F 0.23 p

I I I I 1 I 1 I I I i

40A

Source Gate 1 Gate 2 Drain

te 1 bias (V) = 0.0

te 2 bias (V) = 1.0

in bias (V) = 3.0

Current flow lines (50mh/mmlline)

0) Source Gate 1 Gate 2 Drain




-Potential (V)

Cc) Source Gate 1 Gate 2 Drain

40A

f

T 4 8 2 1 Gate Gate 2 1 bias bias (V) (V) = = 0.0 1.0

Energy (cV)

Fig. 5. Distribution of current lines, potential and energy for a reduced inter-gate spacing (0.2pm).

3.2. Current Jrow lines channel midway between the gates is that of an

Figure 2 represents typical current flow lines imagery electrode drain 1 (or source 2) and its value

(50 mA/mm line) in a dual gate MODFET for typical linearly dependent on VgS, . This does not remain valid

d.c. bias values ( VdS = 3 V; VP,, = 1 V) and two values when one equivalent transistor operates in its linear

of Vglr (0 and + 0.4 V), corresponding to two different regime, e.g. for VB, = 0.4V. In this case channel

operating regimes of the first transistor (saturated potential varies continuously in this zone, which

and linear) as we will see later. From these figures we behaves as a resistance; Vc does not remain a

can draw several conclusions: significant concept.

l Under the gates, the current flow lines are 3.4. Infruence of Vg26

located in the GaAs layer, elsewhere the Examples of typical results obtained are given in majority of the current flows in the AlGaAs Figs 7 and 8. Figure 7 represents equipotential con- layer.

l Charge injection and real space transfer occur at the inlet and the exit of each gate.

tours for VgzS varying from 0.5 to 2V and Fig. 8 equienergy contours for two extreme values of Vg15

l Whatever the biasing point is, carriers injection (0.5 and 2 V), VgS, being set to 0 V corresponding to usual bias for such devices. From these figures,

into the buffer layer occurs under each gate. several conclusions can be drawn:

3.3. Injhence of VP,, l In all cases, a high energy and high field

Figures 3 and 4 represent equipotential and domain settles at the exit of each of the two

equienergy contours for the same VdS (3 V) and V,,, gates.

(1 V) values and three different VP,, values l The relative magnitudes of the two domains, in

(-0.4,0, +0.4 V). These plots point out several as- term of maximum values of energy and

pects about the device behaviour. potential differences strongly depends on the

l Gate 1 voltage allows the operating regime of potential of the second gate VgzS.

l The channel potential in the intergate regions, transistor 1 to be controlled: as can be seen from the equipotential and equienergy con-

Vc, follows the variations of VgSS. In fact,

tours, transistor 1 operates in a saturated Vg,Vc remains always close to V.S, ; this can

regime at VBs = -0.4 and 0 V and under be easily understood by considering that the current is conservative in the channel and as

quasi linear regime at V, = f0.4 V. a consequence, the potential drop under the l Carriers are cold in the intergate region, due to

the relatively large spacing-it is true for gates must be similar (as long as the two “transistors” are identical).

the two intergate distances considered (0.2-0.5 pm). At an intergate spacing of 3.5. Influence of VdS 0.2 pm, in Fig. 5, we find that the carriers are still cold when injected under the second gate. The current path is generally similar to

By comparing the equipotential contours shown in

that of a larger intergate spacing. For Fig. 9 for V,, = 3.6 V with those previously given in

smaller ones, the behaviour could be Fig. 7(b) (with VdS = 3 V), it is possible to have a

different as it was shown previously for better understanding of the influence of drain to

MESFET[20]: carriers could remain hot source voltage on device behaviour. It clearly appears

when they enter under the second gate. This that if the other bias voltages remain constant, an

could result in a decrease of the output increase of Vdr has repercussions only on the equipo-

conductance. tential contours in the region beyond the exit of the

l The intergate potential remains almost con- 3.5 r-

stant when transistor 1 operates in the saturated regime. This is not the case for Vg,$ 2.1 -

higher than 0 V.

The effect of VgS, on channel potential is also clearly shown in Fig. 6 that represents the evolution of channel potential from source to drain for VgS, values ranging from -0.4 to +0.4 V. The main interesting results concern the intergate zone. The potential remains uniform in this part of the channel as long I I I I I I 1 I

as the two equivalent transistors operate in the 0 0.2 0.4 0.6 0.8 I.0 1.2 1.4 1.6 1.8 2.0

saturated regime: in this case, it is possible to consider X (km) that the dual gate field effect transistor behaves as two transistors in cascade configuration, and that the

Fig. 6. Spatial variations of channel potential for various values of V,,, in a dual gate MODFET ( Vds = 3 V and

potential Vc as calculated at the point C in the _.

vg2s = 1 Vh


SOUPS? Gate 1 Gate 2 Drain

-0.2

3 b

Gate 1 bias (V) = 0.0 ‘&


qrain bias (V) = 3.0 I

Gate 1 bias (V) = O.Oi;



Gate 1 Gate 2 Drain

Gate 1 Gate 2 Drain

7. Influence of V,?$ on equipotential contours in a dual gate MODFET ( vds = 3 V, vels = 0 V): (a) V,,$ = 0.5 V; (b) V,,, = I V; (c) v,_ = 1.5 v; (d) vg2s = 2 v.

924


(a) Source Gate I Gate 2 Drain




(b) SOUKC Gate 1 Gate 2 Drain

Gabs




Energy (eV) D

Fig. 8. Influence of V,,, on equienergy contours (given in eV) in a dual gate MODFET (Vdr = 3 V; V,,, = 0 V): (a) Vos = 0.5 V; (b) V,:, = 2 V.

Gate 1 Gate 2 Drain

3 B

4oA _L

T j 1

AlGaAs

GaAs

Potential (V)

1 Iillillll I

Fig. 9. Equipotential contours in a dual gate MODFET for a higher value of Vdr [as compared to 7(b)] vg,* = 0 v; - V8>’ = I v; V& = 3.6 v.

926 Khaki Sherif ef al.

0.5

0.1

V g2n "dc

2.0 3.6 2.0 3.0

I .5 3.6 1.5 3.0

I.0 3.6 I.0 3.0

0.5 3.0

Fig. IO.

S

Equivalent d.c. scheme of a dual gate MODFET, including two transistors in cascade.

second gate. This electrode acts as a kind of screen between the first gate and the drain; as a consequence, vd, has only a very small influence on drain current and the output conductance of the device is very small. This remains true even for very small gate lengths, and can be used in the future for sub 0.1 pm devices.

4. STATIC AND DYNAMIC CHARACTERISTICS

Our model allows the static and dynamic characteristics of the dual gate MODFET to be deduced. From these results, it is possible to improve our knowledge of device behaviour, to calculate the elements of the equivalent circuit and to predict the performance.

4.1. Static characteristics

We have calculated not only the d.c. characteristics of the entire device but also those of each equivalent

600

500 /

*-*-* v g,s = 0.5 v

,* -*--*

-0 0.5 1 .o 1.5 2.0 2.5

vcs (V) Fig. 1 I. Id =f( V,) static characteristic for the first equivalent transistor of a dual gate MODFET: V,, = 3 V, VBls ranging from - 0.4 to 0.5 V with 0. I V voltage step and V,,.

ranging from 0.5 to 2V.

Fig. 12. Dependence of V,, upon VBls for several values of V,?. and Vds for a 0.3ym dual gate MODFET.

device associated in cascade to constitute the dual gate FET (Fig. 10). For instance, Fig. 11 represents typical 1, =f( V,,) of the first transistor. These results are in good agreement with those obtained exper- imentally for a single gate FET.

Figures 12 and 13 give interesting information on device behaviour that can be used to conceive simpler device model. They show the variation of intergate channel voltage Vc as a function of Vglr and V,,$. Except when the first transistor operates in its linear regime (VP,, > 0.3 V and V,,, < 1 V), we can observe a linear dependence of Vc on VB2s and Vg, in the form:

v, = k, v,,, + k2 Vg2sr+k3Vdsr

where k, x - I, k, = - 0.84 for the device considered here. With simple physical reasoning, this relation could be soon extended to all dual gate devices provided the inter-gate spacing stays large enough not to permit hot electrons injection under the second gate. It should be pointed out also that the generality of this relation is subject to the conditions afore mentioned upon the different electrode potentials. Similar results have been obtained for other device dimensions. These results were confirmed by another

2.1 V gls t

-0.4 v 1.7

&

E 1.3 z

p

!p&

At 0.9

ii@ s

z ;_,.3 v

* + 0.5 v * *

0.5 ;

0.1 r 0.5

I I

1 .o 1.5 2.0

Vgzs (V)

Fig. 13. Dependence of V,, upon Vgzl for several values of Vg,s ( VBls ranging from -0.4 to 0.5 V) for a 0.3 pm dual gate

MODFET.


I .o

0.8

0.6

z

a 0.4

0.2

step response L glg2 = 0.5 w

V & step = I v v gls = 0.0 v

V& step = 3 v With F.0.C

0 0 I 2 3 4 5

Ps

Fig. 14. Transient response of a dual-gate MODFET.

type of simulation performed in our laboratory: the quasi 2D simulations[21].

4.2. Dynamic characteristics

By means of our hydrodynamic model, it is possible to calculate the elements of the equivalent circuit using two methods:

l a quasi static approach where the device is being submitted to incremental variations in the various bias voltages;

l a transient approach from which the frequency response is deduced using a fast Fourier transform of a typical time domain behaviour as the one shown in Fig. 14.

It has been previously shown[8,16] that for single gate FETs, these two methods give very similar results.

We have used the first method to calculate the elements of the equivalent circuit shown in Fig. 15. We will now give some typical results obtained using this method.

700

600

500

2

E 400 z

z 300

‘Ei 04

200

100

0

0 *

Fr V g2c = 2.0 v

0 b- m /

0 V g25

= I.5 v

B V

g25 = I.0 v

o vg2< = 0.5 v

\ 0

\ I I 1

-0.4 -0.2 0 0.2 0.4

“gls (“)

Fig. 16. Variations with V,,, of the transconductance g,,,, for the first equivalent transistor of a dual gate MODFET with

V,,$ varying from 0.5-2 V and Vdr = 3 V.

First of all, Fig. 16 shows the variation of the transconductance g,,,, (of the first equivalent transistor) with VBIS for various values of V,,, and of VcS (equivalent drain to source voltage). These curves are similar to those obtained for single gate MODFETs. Note that the dependence of the transconductance on V BZsr is only appreciable when the first transistor operates in its linear regime (VplS < 1 V). The corresponding variations of the input capacitances C,, 5 are shown in Fig. 17. C,,, increases with V,,S and with VgzS (and consequently with V,,). Note that the corresponding values of intrinsic current gain cut off frequencies (f, z gm/2nC,) are of the same order of magnitude (f, g 130 GHz) as those of the equivalent single gate MODFET.

Figures 18 and 19 represent variations of the “output” conductance gd, and feedback capacitance C,,, (first equivalent transistor) with V8,S for various values of VBIS which affects VCS. When the first transistor operates in the saturated regime, the usual behaviour of a conventional MODFET can be observed. On the other hand, a strong increase with VP,,

gd2

Fig. 15. Equivalent electrical circuit of a dual gate MODFET including the intrinsic elements. Note that the typical values of the access resistances are: source and drain resistances: R, = R, = 0.2-0.3 Rmm: gate

resistance: R, = SO-100 R/mm. Internal resistance R,? is typically 0.5-I a/mm.


0.95

z

i.z a” 0.75

2 0.55

V g2\ (“’

i

2

I.

/

1

0.5

0.35 -0.4 -0.2 0 0.2 0.4

“gls (“)

Fig. 17. Variations with V,, s of the input capacitance Cs, \ for the first equivalent transistor of a dual gate MODFET with

Vgzq varying from 0.5 to 2 V and V,, = 3 V.

of both output conductance and feedback capacitance occurs when the first transistor operates in the linear regime: in this case, the feedback capacitance becomes of the same order of magnitude as the input capacitance.

Interesting results can also be deduced concerning equivalent circuit elements of the second equivalent transistor. Figure 20 shows the variation of the input capacitance C,,, with V..,s for several V,,, values. It can be seen that C,,, is strongly dependent on V8,$ and not on VgzS. However, these results can be easily explained by remembering that V, follows the variations of Vgls as mentioned earlier hence Vgzc is almost independent of V,,,. On the other hand, V,, depends on Vg,s (Fig. 12): as a consequence, VP,, varies with Vals even when Vazr remains constant.

We have also observed that the “input” capacitance Cgzc is independent of V,, and that the feedback capacitance C,,, decreases slowly with V,,, and is independent of VP,, . Moreover, typical values of gm2

are always smaller than gm, This can be explained

100

’ 60 3j E

L

0 -0.4 -0.2 0 0.2 0.4

V g,s (“)

Fig. 18. Variations with Vg,, of the output conductance g,, for the first equivalent transistor of a dual gate MODFET

with V,,, varying from 0.75 to 1.75 V and V,, = 3 V.

100

0 -0.4 -0.2 0 0.2 0.4

V gt< (“)

Fig. 19. Variations with VgIs of the feedback capacitance C,,, for the first equivalent transistor of a dual gate MODFET

with Vg2s varying from 0.75 to 1.75 V and Vds = 3 V.

by considering that the second transistor has higher equivalent access resistances than the first one.

5. CONCLUSION

Simulation of submicron dual gate MODFET has been presented using a transient model that includes all the main effects that govern device performance such as overshoot phenomena, carrier injection into the buffer layer and transfer across the heterojunction. It allows us to improve our physical knowledge of device behaviour and to determine the conditions for which the DG MODFET can be considered as a cascade connection of two devices. Moreover, it gives a lot of practical information concerning potential variations inside the device and mainly in the intergate regions.

Finally, we are able to deduce the elements of the equivalent currents and to study their dependence on d.c. bias values.

1.15

0.95

g iz Q, 0.75

% L,

0.55

0.35

Vgzs i

/

0.5 v IV

/

/

1.5 v

/

/ 2”

-0.4 -0.2 0 0.2 0.4

V gl, (“)

Fig. 20. Variations with V,,, of the input capacitance C,?, for the second equivalent transistor of a dual gate MODFET

with V,_ varying from 0.5 to 2 V and V,,, = 3 V.


Acknowledgemen/-We wish to thank the reviewers for IO. M. Ravaioli and F. R. Ferry, IEEE Trans. E/ec/ron extremely constructive and useful remarks. Devices 33, 671 (1986).

1.

2.

3.

4.

5.

6.

7.

8.

9.

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I I. R. Fauquembergue, M. Pernisek, J. L. Thobel and P. Bourel. ESSDERC Conf.. Boloana (1987).

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13. T. Shawki, G. Salmer and 0. El Sayed, /EEE Trans. CAD of KAS (1990).

14. T. N. Theis, Proc. Int. Phys. Conf: Ser No. 91. pp. I -6 (1987).

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Documents

Two-dimensional hydrodynamic simulation of submicrometer dual gate MODFETs