IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 44, NO. 7, JULY 1997 1143

Tunneling Source-Body Contact forPartially-Depleted SOI MOSFET

Vincent M. C. Chen and Jason C. S. Woo,Senior Member, IEEE

Abstract—In this paper, a novel self-aligned asymmetric source-body contact is proposed based on the tunneling effect. Thefabrication is relatively simple with only one extra angle implantstep. Test structures have been fabricated and good electricalresults were obtained. The improvements of this new approachin both device performance and manufacturing compared tofully-depleted SOI MOSFET’s will be discussed.

I. INTRODUCTION

T HE continuous advancement in ULSI technology andthe widespread interest in low-power electronics have

accelerated the scaling of MOSFET channel lengths into thedeep subquarter micron regime. One key factor that allows thepossibility of further scaling is the relaxation of the supply biaslimit. However, for digital circuit applications, the criterion

should be maintained so that the switchingspeed performance of the device will not deteriorate. Unfortu-nately, a lower threshold voltage will lead to a higher off-stateleakage current Under these circumstances, the subthresholdslope becomes particularly important. For a deep submicrondevice, the subthreshold slope is not only dependent on thecapacitance between the gate oxide-silicon interface and thewell contact, but is also strongly affected by the short-channeleffects (SCE). A lower threshold voltage also requires a stricterdemand on uniformity. This implies the need for better processcontrol and structures that have a threshold voltage with betterimmunity to doping and geometry fluctuation.

Recently, a number of deep subquarter micron bulk sili-con MOSFET have been proposed and demonstrated [1]–[6].Although they were fabricated with different process tech-nologies, most of them share the same design considerationsand hence have similar device structures. A typical 0.1-

m MOSFET device structure has shallow source and drainextensions to minimize the junction depth at the channel edge.Deep source and drain junctions are then implemented with aself-aligned process to reduce the junction resistance. A thingate oxide of less than 50A is used to improve gate control,reduce the SCE, and increase the transconductance. A thinnergate oxide also implies a lower thermal budget and makes iteasier to implement a sharp retrograded channel doping. Sharpretrograded channel doping reduces the SCE and improvesthe immunity of the threshold voltage to doping fluctuations.However, this usually requires the use an additional mask to

Manuscript received March 18, 1996; revised February 27, 1997. Thereview of this paper was arranged by Editor D. A. Antoniadis.

The authors are with the Department of Electrical Engineering, Universityof California, Los Angeles, CA 90095 USA.

Publisher Item Identifier S 0018-9383(97)04679-0.

Fig. 1. Schematic cross section for a direct implementation of bulk silicondeep subquarter micron MOSFET structure on thin-film silicon-on-insulatorsubstrate with a self-aligned asymmetric source-body contact.

localize the channel doping and keep the junction capacitancelow. For these devices, the typical supply voltage is in therange of 1–1.5 V and the threshold voltage is in the range of0.2–0.4 V.

There has been much interest in fully-depleted MOSFET’s(FD MOSFET’s) fabricated on thin-film silicon-on-insulator(SOI) substrates. It is commonly believed that for longerchannel length ( m), the FD SOI MOSFET willout-perform a conventional bulk silicon MOSFET. However,a thin SOI film thickness of 500A or less [7] demands morestrict process uniformity control and improved salicidation toreduce the junction contact and series resistance [8]. Untilrecently, there have only been a few publications addressingthe optimization of SOI MOSFET in the deep submicronregime [7]–[9].

A new approach is proposed to implement a deep subquartermicron MOSFET on an SOI substrate [9]. The same designas a typical bulk silicon device structure is directly transferredand implemented on a 1000–1500A SOI substrate. However,the device will be working in the nonfully-depleted modeand hence will exhibit the kink effect, which will resultin a low output resistance, an increased threshold voltagefluctuation, and a reduced power gain. In this paper,a self-aligned asymmetric tunneling source-body contact(shown inFig. 1) was proposed to effectively reduce the kink effect.Compared to other asymmetric source-body contacts proposed[10], this self-aligned structure is more manufacturable andcan be fabricated with minimum additional effort and processvariation. One advantage of using an SOI structure is that eachtransistor is located in an isolated Si island, hence the sourcecan be biased with a nonzero voltage reducing backgating

0018–9383/97$10.00 1997 IEEE

1144 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 44, NO. 7, JULY 1997

effect. However, the asymmetric design is not consistent withpass transistor devices which, if implemented on the samedie, can only be fabricated without the angle implant, hencean additional mask may be needed.

II. DEVICE STRUCTURE AND PRINCIPLE OF OPERATION

The device will be implemented on an SOI substrate witha silicon film thickness of 1000A, which is thick enough toachieve the sharp retrograded channel doping within the siliconfilm. The retrograded channel doping is self-aligned in the SOIdevice fabrication as the deep junctions extend to the silicon-buried oxide interface. Shallow source and drain extensionsand a thin gate oxide are employed for the same purpose ofreducing SCE as in the optimized bulk device structure. Thedeep source and drain junctions extend all the way to thesilicon-buried oxide interface.

In such devices, if the body is left floating, the accumu-lation of holes that come from impact ionization will alterthe threshold voltage and result in the “kink” effect. Thisphenomenon is difficult to control and will severely reduce theoutput resistance and hence result in a lower gain. Therefore,a body contact is needed.

A schematic diagram of the proposed device structure witha self-aligned source body contact is shown in Fig. 1. A

cm p region is asymmetrically introduced beneaththe source extension. Since the pregion is located belowthe channel region and the source current is conducted in thesource extension, the pregion will not affect the device–characteristics. The p region, however, has a high dopingconcentration such that the source and the body are electricallyconnected by tunneling.

One major advantage of this approach is that the fabricationof the device is almost identical to the optimized bulk SiMOSFET. The only extra process step is a 45large angletilted boron implant to implement the halo-like pregion.This is a self-aligned step as the spacer that defines the deepsource/drain implant is also used to define the angle implant.The implant is carried out after the deep junction implantand before the annealing, which is a noncritical stage in thefabrication process.

III. EXPERIMENT

In order to investigate the design of the tunneling source-body contact, test structures similar to that shown in Fig. 1was fabricated. To simplify the process, the deep retrogradedchannel implant was omitted. Both the extension and the pregion were fabricated with large tilted angle implant. Thedevices were fabricated on Ibis SIMOX wafers with a 350-nm buried oxide and have a final film thickness of 100 nm.MESA isolation was performed using RIE, followed by theformation of a 200-nm sidewall oxide. The substrate profilewas defined by a 35 keV, cm boron implant, resultingin an effective channel doping of cm . A dryoxidation was done to form a 15-nm gate oxide, immediatelyfollowed by a 400-nm n in situ doped poly deposition. Afterthe gate lithography and the gate-define etch, the source/drain

(a)

(b)

Fig. 2. Leakage current versus drain bias of a self-aligned asymmetricsource-body contact test structure operated in (a) reverse mode and (b) normalmode,L

drawn= 1:0 �m, W = 100 �m, VG varies from (VTH � 2 V)

to (VTH � 3 V).

were doped with a 170 keV, cm As implant. Thesource extension was formed with a 80 keV, /cmphosphorous implant tilted at 60, resulting in an extensionregion on the order of 50 nm. The halo-like pregion wasformed with a 75 keV, /cm boron implant tiltedat 45 . This RTA condition was chosen to ensure minimumboron diffusion across the gate oxide into the silicon film.

IV. ELECTRICAL RESULTS

Measurements of the fabricated test structures were car-ried out to study the source-body contact. Since the sourceis connected to the p-type body, the source-to-drainhas diode-like characteristics. In Fig. 2, the – and

– of the same device are measured with the gate biasvarying from ( V) to ( V). In Fig. 3, thelinear relation between and the channel width shows thatthe source-body contact is uniform along a channel width upto 100 m. Shown in Fig. 4 is a comparison of thecharacteristics of a MOSFET with the asymmetric implantworking in the normal mode and the reverse mode (source anddrain interchanged), and compared to a control device. Notethat in an SOI device, the source and drain currents are alwaysthe same, since there is not a separate current path throughthe substrate. The source-body contact is demonstrated to beeffective in providing a higher breakdown voltage comparedto a FD SOI MOSFET. It also substantially reduces the–kink compared to a nonfully-depleted SOI MOSFET without abody contact. The subthreshold characteristics are shownin Fig. 5. Shifting of the curve in Fig. 5(b) is due to theasymmetric body contact and can be considered as a bodyeffect. The subthreshold slope can be improved with a thinnergate oxide and a sharp retrograded channel doping as usedin the structure proposed. These results demonstrate that the

CHEN AND WOO: TUNNELING SOURCE-BODY CONTACT FOR PD SOI MOSFET 1145

Fig. 3. Leakage current versus channel width of a self-aligned asym-metric source-body contact test structure operated in reverse mode.Ldrawn

= 1:0 �m, W = 100 �m, VG = (VTH � 3 V); VD = 3 V.

(a)

(b)

(c)

Fig. 4. I–V characteristics of a self-aligned asymmetric source-body contacttest structure operated in (a) normal mode and (b) reverse mode; andI–Vcharacteristics of (c) a fully-depleted SOI MOSFET,L

drawn= 1 �m,

W = 5 �m, VG varies fromVTH to (VTH + 3 V) in step of 0.5 V.

tunneling source-body contact is effective and independent ofthe channel width.

V. DEVICE PERFORMANCE

The device characteristics of the proposed device struc-ture were studied and its performance was compared to amatrix of uniformly doped FD SOI MOSFET’s based ontwo-dimensional (2-D) simulations. The doping profiles inthe retrograded channel and the source/drain extensions wereobtained from published data [9]. A 40A gate oxide, 0.1 meffective channel length, 1 V supply bias and 0.25 V thresholdvoltage were assumed for both the proposed device structureand the FD SOI MOSFET. The FD SOI MOSFET’s have twoburied oxide thicknesses of 3000 and 800A, while their silicon

(a)

(b)

Fig. 5. Subthreshold characteristics of a self-aligned asymmetricsource-body contact test structure operated in (a) normal mode and(b) reverse mode.L

drawn= 1 �m, W = 5 �m, VD /VS varies from

0.1–0.5 V in step of 0.1 V.

Fig. 6. SOI Film doping versus film thickness of the FD SOI MOSFETdevices used in the 2-D simulation.

film thickness varies from 500A down to 50 A. For eachFD SOI device geometry, two sets of uniform body dopingconcentrations were used. First, the threshold doping, in whichthe body is doped uniformly so that V. Second,the optimum doping, in which the body is uniformly doped sothat the subthreshold slope is minimum. Here, a maximumdoping concentration of cm , and a optimized gateelectrode work function were assumed. The relations of thebody doping used in the simulation versa SOI film thicknessis shown in Fig. 6.

As discussed in the previous section, for lower thresholdvoltages, the subthreshold slope will be an important factor.The optimum subthreshold slopes at V of theproposed device and the FD SOI MOSFET with different

1146 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 44, NO. 7, JULY 1997

Fig. 7. Subthreshold slope versus SOI film thickness for various FDSOI MOSFET compared to the proposed SOI MOSFET.tox = 40 A,L = 0:1 �m.

film thickness are compared. As shown in Fig. 7, the FD SOIMOSFET has a higher subthreshold swing (smaller mV/decade

). Nevertheless, the difference is not significant. Under thesecircumstances, DIBL may be a more meaningful factor forcomparing the SCE of both structures. In our study, the DIBLis defined by V

V . As shown in Fig. 8, for the FD SOI MOSFET’sto have a comparable DIBL, a SOI film thickness of 150A is needed, which is difficult to control. These trade-offshave been reported by several groups in the past [11], [12].Our proposed device has reduced DIBL due to optimizedchannel and source/drain extension dopings. From a circuitpoint of view, a more realistic assessment is given by

. As shown in Fig. 9, the pro-posed device in general has an improvedthan the FD SOIMOSFET’s.

Both devices have a low junction capacitance as thesource/drain junctions are isolated by the buried oxide. TheFD SOI MOSFET has a lower junction capacitance dueto a thinner Si film and a smaller junction area. However,the thin-film FD SOI MOSFET may suffer from a higherseries resistance and junction contact resistance. These twoparameters are strongly dependent on the process technologyand are usually high enough to offset the advantage of thereduced junction capacitance.

Besides device performance, another important factor to beconsidered is the sensitivity of the device characteristics toprocess variations. From the above discussions, a FD SOIMOSFET with a silicon film thickness of 200A will givethe most comparable results to the proposed structures. Hence,this device geometry is used for the comparison of thresholdvoltage sensitivity. The shift in the threshold voltage forboth structures is plotted in Fig. 10 versus the percentage ofvariation in both the doping concentration and the verticalgeometry (silicon film thickness for FD SOI MOSFET, andvertical dimension of the doping profile for the proposed

Fig. 8. DIBL [�VTH = VTH(VD = 0:1 V) � VTH(VD = 1:O V)]versus SOI film thickness for various FD SOI MOSFET compared to theproposed SOI MOSFET.tox = 40 A, L = 0:1 �m.

Fig. 9. IR[IOFF(VD = 1:O V)/ION(VD = 0:1 V)] versus SOI filmthickness for various FD SOI MOS FET compared to the proposed MOSFET.tox = 40 A, L = 0:1 �m.

device). It is clear that the proposed optimized SOI MOSFET,with a lower sensitivity to process variation, will be moremanufacturable.

VI. CONCLUSION

In this paper, instead of thinning down the silicon filmthickness, an alternative way to implement subquarter micronMOSFET on SOI substrates is discussed. This design employsthe recent achievements in optimized bulk silicon devicesand directly implement it on an SOI substrate with filmthicknesses of 1000 to 1500A, making it more manufac-turable.

To solve the problems associated with the floating body of anonfully-depleted SOI MOSFET, a novel self-aligned tunnel-

CHEN AND WOO: TUNNELING SOURCE-BODY CONTACT FOR PD SOI MOSFET 1147

(a)

(b)

Fig. 10. Threshold voltage variation versus percentage variation in substratedoping (implant dose for proposed SOI MOSFET) and vertical geometry(SOI film thickness for FD SOI MOSFET, implant depth for proposed SOIMOSFET).tox = 40 A, L = 0:1 �m, tsoi = 200 A, Dsoi = 1� 10

18 cm3

(threshold doping) and2 � 1018 cm3 (optimum doping).

ing source-body contact is proposed. It makes use of the factthat shallow source/drain extensions are already implementedfor reducing SCE for subquarter micron devices. Hence onlyone extra angle implant is involved at a noncritical phasein the fabrication process. Test structures were designed andfabricated. The measured results suggest a good source-bodycontact was formed. The effectiveness of the contacts is inde-pendent of the channel width. They improve the break-downvoltages and substantially reduce the– kink compared to astandard nonfully-depleted SOI MOSFET.

Detailed comparisons between the performance of the pro-posed structure and some possible short-channel SOI MOS-FET’s with uniformly doped silicon film were carried outwith 2-D simulations. Significant improvement in DIBL andthreshold voltage immunity to doping and geometry fluctuationwere obtained. These are important advantages for low-powersubquarter micron channel length devices. Hence, the proposedstructure can be considered as a alternative approach to fully-depleted structures to optimize SOI MOSFET’s for futurelow-power ULSI applications.

REFERENCES

[1] M. Saito, T. Yoshitomi, M. Ono, Y. Akasaka, H. Nii, S. Matsuda, H. S.Momose, Y. Katsumata, Y. Ushiku, and H. Iwai, “An SPDD p-MOSFETstructure suitable for 0.1- and sub-0.1–� channel length and its electricalcharacteristics,” inIEDM Tech. Dig.,1992, pp. 897–900.

[2] Y. Taur, S. Cohen, S. Wind, T. Lii, C. Hsu, D. Quinlan, C. Chang,D. Buchanan, P. Agnello, Y. Mii, C. Reeves, A. Acovic, and V. Kesan,“High transconductance 0.1-�m pMOSFET,” inIEDM Tech. Dig.,1992,pp. 901–904.

[3] M. Ono, M. Satio, T. Yoshitomi, C. Fiegna, T. Ohguro, and H. Iwai,“Sub-50-nm gate length n-MOSFET’s with 10-nm phosphorus sourceand drain junctions,” inIEDM Tech. Dig.,1993, pp. 119–122.

[4] Y. Taur, S. Wind, Y. Mii, Y. Lii, D. Moy, K. Jenkins, C. Chen, P.Coane, D. Klaus J. Bucchignano, M. Rosenfield, M. Thomson, and M.Polcari, “High-performance 0.1-�m CMOS devices with 1.5 V powersupply,” in IEDM Tech. Dig.,1993, pp. 127–130.

[5] K. Lee, R. Yan, D. Jeon, G. Chin, Y. Kim, D. Tennant, B. Razavi, H.Lin, Y. Wey, E. Westerwick, M. Morris, R. Johnson, T. Liu, M. Tarsia,M. Cerullo, R. Swartz, and A. Ourmazd, “Room temperature 0.1-�mCMOS technology with 11.8 ps gate delay,” inIEDM Tech. Dig.,1993,pp. 131–134.

[6] K. Takeuchi, T. Yamamoto, A. Tanabe, T. Matsuki, T. Kunio, M.Fukuma, K. Nakajima, H. Aizaki, H. Miyamoto, and E. Ikawa, “0.15-�m CMOS with high reliability and performance,” inIEDM Tech. Dig.,1993, pp. 883–886.

[7] N. Kistler, E. Ver Ploeg, J. Woo, and J. Plummer, “Subquarter-micrometer CMOS on ultrathin (400 A) SOI,”IEEE Electron. DeviceLett., vol. 13, pp. 235–237, May 1992.

[8] L. Su, M. Sherony, H. Hu, J. Chung, and D. Antoniadis, “Optimizationof series resistance in sub-0.2-�m SOI MOSFET’s,” in IEDM Tech.Dig., 1993, pp. 723–736.

[9] G. Shahidi, T. Ning, T. Chappell, J. Comfort, B. Chappell, R. French, C.Anderson, P. Cook, S. Schuster, M. Rosenfield, M. Polcari, R. Dennard,B. Davari, “SOI for a 1 V CMOS technology and application to a 512kb SRAM with 3.5 ns access time,” inIEDM Tech. Dig.,1993, pp.813–816.

[10] E. P. Ver Ploeg, T. Watanabe, N. A. Kistler, J. C. S. Woo, and J. D.Plummer, “Elimination of bipolar-induced breakdown in fully-depletedSOI MOSFET’s,” in IEDM Tech. Dig.,1992, pp. 337–340.

[11] B. Davari, R. H. Dennard, and G. G. Shahidi, “CMOS scaling for highperformance and low power—The next ten years,” inProc. IEEE,vol.83, pp. 595–606, 1995.

[12] L. Y. Su, J. B. Jacobs, J. Chung, and D. A. Antoniadis, “Deep-submicrometer channel design in silicon-on-insulator (SOI) MOS-FET’s,” IEEE Electron. Device Lett.,vol. 15, pp. 366–368, Sept.1994.

Vincent M. C. Chen, photograph and biography not available at the time ofpublication.

Jason C. S. Woo(S’83–M’87–SM’97) received the B.A.Sc. degree (Hons.) inengineering science from the University of Toronto, Toronto, Ont., Canada, in1981, and the M.S. and Ph.D. degrees in electrical engineering from StanfordUniversity, Stanford, CA, in 1982 and 1987, respectively.

In 1987, he joined the Department of Electrical Engineering at the Univer-sity of California, Los Angeles, where he is currently a Professor. From 1987to 1989, he received a faculty development from IBM. His research interestsare in the physics and technology of novel device and device modeling. Hehas authored or coauthored over 90 papers in technical journals and refereedconference proceedings in these areas.

Dr. Woo served on the IEEE IEDM program committee from 1989 to 1990and from 1994 to 1996, and was the publicity vice chairman in 1992 and thepublicity chairman in 1993. He has also been the workshop chairman and atechnical committee member of the VLSI Technology Symposium since 1992.