TUESDAY KEYNOTE - Design Automation Conference · 6 TUESDAY KEYNOTE Room: 102/103 General Interest SUMMARY: Comparing the original ARM design of 1985 to those of today’s latest

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TUESDAY KEYNOTERoom: 102/103 General Interest

SUMMARY: Comparing the original ARM design of 1985 to those of today’s latest microprocessors, Mike will look at how far has design come and what EDA has contributed to enabling these advances in systems, hardware, operating systems, and applications and how business models have evolved over 25 years. He will then speculate on the needs for scaling designs into solutions for 2020 from tiny embedded sensors through to cloud based servers which together enable the internet of things. He will look at what are the major challenges that need to be addressed to design and manufacture these systems and proposes some solutions.

BIO: Mike Muller was one of the founders of ARM. Before joining the Company, he was responsible for hardware strategy and the development of portable products at Acorn Computers and was part of the original ARM design team. He was previously at Orbis Computers who developed network computers. At ARM he was VP, Marketing from 1992 to 1996 and EVP, Business Development until October 2000 when he was appointed Chief Technology Officer. In October 2001, he was appointed to the board of ARM Holdings plc.

June 5, 8:30 - 9:30am

SCALING FOR 2020 SOLUTIONS

MIKE MULLER ARM, Inc., Cambridge, United Kingdom

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MARIE R. PISTILLI WOMEN IN EDA ACHIEVEMENT AWARDFor her significant contributions in helping women advance in the field of EDA technology. Dr. Belle W. Y. Wei - Don Beall Dean of the Charles W. Davidson College of Engineering, San Jose State Univ.

P.O. PISTILLI UNDERGRADUATE SCHOLARSHIPS FOR ADVANCEMENT IN COMPUTER SCIENCE AND ELECTRICAL ENGINEERINGThe objective of the P.O. Pistilli Scholarship program is to increase the pool of professionals in Electrical Engineering, Computer Engineering, and Computer Science from under-represented groups (women, African-American, Hispanic, Native American, and physically challenged). In 1989, the ACM Special Interest Group on Design Automation (SIGDA) began providing the program. Beginning in 1993, the Design Automation Conference provided the funds for the scholarship and a volunteer committee continues to administer the program for DAC. DAC funds a $4000 scholarship, renewable up to five years, to graduating high school seniors. The 2012 recipient is:Catherine Agor Mullings

A. RICHARD NEWTON GRADUATE SCHOLARSHIPSEach year the Design Automation Conference sponsors the A. Richard Newton Graduate Scholarship to support graduate research and study in Design Automation (EDA). Each scholarship is awarded directly to a University for the Faculty Investigator to expend in direct support of the project and students named in the application. The criteria are: the quality and applicability of the proposed research; the impact of the award on the EDA program at the institution; the academic credentials of the student(s); and financial need.This year’s scholarship goes to:Advisor: Prof. Yiran Chen – Univ. of Pittsburgh

Student: Wujie Wen – Univ. of Pittsburgh

Project: NVSim-VX: Variation Aware Emerging Nonvolatile Memory Simulator

2011 PHIL KAUFMAN AWARD FOR DISTINGUISHED CONTRIBUTIONS TO EDA Sponsored by the EDA Consortium and IEEE Council on EDADr. C. L. David Liu – William Mong honorary chair professor of Computer Science and former president of the NationalTsing Hua University in Hsinchu, Taiwan

Dr. C. L. David Liu received this award for his distinguished technical contributions, leadership skills, and business acumen in electronic design automation.Dave Liu is honored for his work in leading the transformation from ad hoc EDA to algorithmic EDA.

IEEE CEDA OUTSTANDING SERVICE CONTRIBUTIONFor significant services as DAC General Chair 2011.Leon Stok – IBM Corp.

IEEE FELLOWFor contributions to analysis and modeling of VLSI interconnects.Luis Miguel Silveira – Technical Univ. of Lisbon

IEEE FELLOWFor contributions to circuits, architectures, and software technology for field-programmable gate arrays.Steve Trimberger – Xilinx Inc.

IEEE FELLOWFor contributions to system-level power characterization, including thermal management.Naehyuck Chang – Seoul National Univ.

DONALD O. PEDERSON BEST PAPER AWARD FOR THE IEEE TRANSACTION ON CADFor the paper titled: “An Analytical Approach for Network-on-Chip Performance Analysis,” IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems, December 2010, Vol. 29, No. 12, pp. 2001-2013.Umit Ogras – Intel Corp.Paul Bogdan – Carnegie Mellon Univ.Radu Marculescu – Carnegie Mellon Univ.

ACM/IEEE A. RICHARD NEWTON TECHNICAL IMPACT AWARD IN ELECTRONIC DESIGN AUTOMATIONFor advancing the theory and implementation of model order reduction for efficient circuit analysis via dominant pole/zero methods.“PRIMA: Passive Reduced-Order Interconnect Macromodeling Algorithm,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, August 1998, Vol. 17, Issue 8, Pages 645-654.Altan Odabasioglu – Gear Design SolutionsMustafa Celik – Synopsys, Inc.Larry Pileggi – Carnegie Mellon Univ.

SIGDA OUTSTANDING NEW FACULTYOutstanding New Faculty for 2012. David Atienza – Ecole Polytechnique Fédérale de Lausanne

ACM/SIGDA OUTSTANDING PH.D. DISSERTATION AWARDIn recognition of the outstanding dissertation “Algorithmic Studies on PCB Routing.”Dr. Tan Yan – University of Illinois at Urbana-ChampaignProf. Martin D. Wong (Dissertation Advisor) – University of Illinois at Urbana-Champaign

OPENING REMARKS - Patrick Groeneveld - 49th DAC General ChairAWARDS PRESENTATIONS

GENERAL SESSIONTuesday, June 5, 8:30 - 9:45am Room: 102/103

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WEDNESDAY KEYNOTERoom: 102/103 User Track

BIO: Joshua Friedrich is a Senior Technical Staff Member and Senior Manager of POWERTM Technology Development in IBM’s Server and Technology Group. In his role, Josh leads the physical design, technology direction, and methodology of IBM’s future POWERTM processors. Josh has been part of the POWER development team since POWER4TM, and on past POWERTM designs, Josh has led multiple design disciplines including power estimation and reduction, hardware characterization, memory subsystem circuit development, and core execution units. Before joining IBM, Josh received his Bachelor of Science in Electrical Engineering from the University of Texas at Austin.

BIO: Brad Heaney is an Intel Architecture Group Project Manager and operates out of Intel’s Folsom Design Center. Brad is a 25 year veteran at Intel and started his career working on the design of the 80386 family of CPUs and is the holder of four patents for his design work. In the last few years, Brad has been managing the teams that deliver Intel’s lead vehicles for ramping new process technologies. Brad’s team developed the Penryn CPU, which was a lead vehicle for 45nm process technology. In April of this year, they launched the Ivy Bridge CPU (3rd Generation Intel Core Processor), which is the lead vehicle for Intel’s 22nm process technology. Brad received his Bachelor of Science degree from Drexel University in Philadelphia and his Master of Science in Electrical Engineering degree from Stanford University prior to joining Intel.

June 6, 10:45 - 11:45am

DESIGNING HIGH PERFORMANCE SYSTEMS-ON-CHIP

BRADHEANEY

JOSHUA FRIEDRICH

POWERTM Processor Design and Methodology Directions

Designing a 22nm Intel® Architecture Multi-CPU and GPU

Experience state-of-the art design through the eyes of two experts that help shape these advanced chips! In this unique dual-keynote, the design process at two leading companies will be discussed. The speakers will cover key challenges, engineering decisions and design methodologies to achieve

top performance and turn-around time. The presentations describe where EDA meets practice under the most advanced nodes, so will be of key interest to both designers and EDA professionals alike.

SUMMARY: Processor designs and the EDA tools that support them stand at a key inflection point. The era of Dennard scaling and exponential single thread performance growth is a distant memory. Multi-thread performance continues to grow. However, the gain from simply adding more cores to a die by stepping to the next process node is diminishing due to technology challenges, application bottlenecks, and power/packaging constraints. To continue to deliver the cost-performance gains that drive our industry, designers will need to bring significant innovation to bear by integrating heterogeneous system components and accelerating key portions of the software stack in hardware. This transformation from technology-driven design to innovation-driven design defines new priorities for EDA development compared to prior eras. While timing optimization, power reduction, and support for modular designs remain necessary, differentiation will be achieved by enabling designer productivity through technology simplification, design abstraction, and robust support for heterogeneous IP.

SUMMARY: With each new process technology node and integration of more system components on to a monolithic die, the design methodology challenges must advance to enable validation and implementation of these complex products. With Intel’s new 22nm technology, we are designing products with over 1.4 billion transistors and integrating hardware blocks that naturally want different process and design optimizations. The recently launched 3rd Generation Intel Core Process (codename Ivy Bridge) has an integrated Graphics Processing Unit that has different process and design demands than the CPU Core Processor. With the size and diversity of the product hardware, combined with new advanced process technology features, such as Intel’s new tri-gate transistor, more capabilities for silicon debug, coverage, and manufacturing need to be planned and incorporated into the architecture and design implementation. By close collaboration between the process development and design teams at Intel, we are able to develop design methods to ramp these large, complex products into high volume manufacturing at, or ahead of, the schedule on prior products.

IBM Server and Technology Group, Austin, TX

Intel Corp., Folsom, CA

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THURSDAY KEYNOTERoom: 102/103 General Interest

SUMMARY: It was June 1982 that I had my first technical paper in the EDA area presented at the 19th Design Automation Conference. It was exactly 20 years after I completed my doctoral study and exactly 30 years ago from today. I would like to share with the audience how my prior educational experience prepared me to enter the EDA field and how my EDA experience prepared me for the other aspects of my professional life.

BIO: C. L. Liu received his B. Sc. degree (1956) from the National Cheng Kung University in Taiwan, and his S. M. (1960) and Sc. D. (1962) degrees from the Massachusetts Institute of Technology. He taught at the Massachusetts Institute of Technology, the University of Illinois at Urbana-Champaign, and the National Tsing Hua University in Taiwan. He also served as the President of the National Tsing Hua University from 1998 to 2002.

He is currently the William Mong Honorary Chair Professor of Computer Science at the National Tsing Hua University, an industrial consultant, and the host of a weekly radio show (since 2005). He has published over 180 technical papers, eight technical textbooks and research monographs in the area of EDA, computer –aided instruction, real-time systems, combinatorial optimization, and discrete mathematics, and seven essay collections in the area of science and humanities.

June 7, 11:00am - 12:00pm

MY FIRST DESIGN AUTOMATION CONFERENCE - 1982

C. L. LIU National Tsing Hua Univ., Hinschu, Taiwan

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Organizer: Yervant Zorian - Synopsys, Inc., Mountain View, CA

The DAC 2012 Management Day provides managers with timely information to help them make decisions where business and technology intersect. This is a unique opportunity for managers to gain insights from their peers in the industry.

Today’s complex SoCs require different types of optimizations and the adoption of emerging solutions to meet such requirements. Optimizing for volume production, low power, and shrinking sizes necessitates accurate trade-off analysis and technical/business decision-making by management. Also, moving to new semiconductor technology nodes, such as 20nm or 28nm, can significantly affect the choices of suppliers. The Management Day sessions will discuss these changing needs and present corresponding management decision criteria that allow managers to make the right choices from a pool of alternate options for flows, methodologies, and suppliers.

The Management Day is comprised of two sessions, which will feature presentations by managers representing fab-less companies, systems houses and suppliers to the design ecosystem. Senior managers will discuss the latest and emerging solutions, along with their economic impact.

SESSION 2:

SESSION 1:10:00am - 11:30am General Interest

General Interest1:30 - 4:00pm

Speakers:Vincent Ratford – Senior Vice President, Xilinx, San Jose, CAChi-Feng Wu – Vice President Engineering, Realtek, Hsinchu, TaiwanNorbert Diesing – Director Engineering, PMC Sierra, Vancouver, BC, Canada

Speakers:Ajoy Bose – President CEO, Atrenta, San Jose, CAIndavong Vongsavady – Director Engineering, ST Microelectronics, Crolles, France Pankaj Mayor – Vice President, Cadence Design Systems, San Jose, CAJitendra Khare – Director Engineering, Applied Micro, Sunnyvale, CAWilliam Eklow – Distinguished Engineer, Cisco Systems, San Jose, CA

Decision Making for Complex ICsMoving to new semiconductor technology nodes for complex ICs can significantly affect the choices of design flow, methodologies and suppliers. This session will cover the challenges of complex chip design and present corresponding management decision criteria that allow managers to make the right choices from a pool of alternate options. This session feature presentations by senior managers representing a range of fab-less chip companies.

Trade-Offs and Choices for Emerging SoCsToday’s emerging SoCs require multiple types of optimizations and the adoption of advanced solutions to meet stringent design requirements. Optimizing for volume production, low-power, and shrinking sizes necessitates accurate trade-off analysis and technical/business decision making by management. This session will feature senior managers of today’s most complex nanometer chip design suppliers, fab-less companies, and system houses.

DAC 2012 MANAGMENT DAYTUESDAY, JUNE 5 10:00am - 4:00pmRoom: 309 Additional Registration Fees Apply

www.DAC.com Best Paper Nominees are Denoted in Orange. Perspective Papers are Denoted in Dark Gray. 11

TECHNICAL SESSIONSTUESDAY, JUNE 5

2 SPECIAL SESSION: E-HEALTH: A KILLER APPLICATION FOR ELECTRONIC DEVICES?

Chair: Rajesh Gupta - Univ. of California at San Diego, La Jolla, CA

New electronic systems for diagnostics and care are changing the practice of health management, opening the door to personalized medicine as well as to support for remote care of chronic patients. This session starts with a survey of the field, and then presents the latest inroads in bio-sensing and data acquisition chains, and finally terminates with a presentation of security aspects as a key design problem. Design challenges and design flows for the emerging biomedical electronic systems will be presented.

2.1 Biomedical Electronics Serving as Physical, Environmental, and Emotional Guardians?

Rudy Lauwereins - IMEC, Leuven, Belgium2.2 Integrated Biosensors for Personalized Medicine

Giovanni De Micheli, Cristina Boero, Camilla Baj-Rossi, Irene Taurino, Sandro Carrara - Ecole Polytechnique Fédérale de Lausanne, Switzerland

2.3 Design Challenges for Secure Implantable Medical DevicesWayne Burleson, Shane Clark, Ben Ransford, Kevin Fu - Univ. of Massachusetts, Amherst, MA

10:00 - 11:30am Bio Design AutomationRoom: 304

3 DESIGN AUTOMATION FOR THINGS WET, SMALL, SPOOKY, AND TAMABLE

10:00 - 11:30am

Chair: Tsung-Yi Ho - National Cheng Kung Univ., Tainan, Taiwan

The future of design automation may well be in novel technologies and in new opportunities. This session begins with design techniques that in the past may have applied exclusively to electronic design automation, but now are applied to the wet (microfluidics), the small (nanoelectronics), and the spooky (quantum). The papers cover routing and placement, pin assignment, cell design, and technology mapping applied to microfluidics biochips, quantum gates, and silicon nanowire transistors. The last paper, a perspective, details (tamable) challenges to solve energy arbitration, alternative energy sourcing and capacity provisioning for computational resources through dynamic deferral of energy loads.

3.1 Design of Pin-Constrained General-Purpose Digital Microfluidic Biochips (10:00am)

Yan Luo, Krishnendu Chakrabarty - Duke Univ., Durham, NC

3.2 Path Scheduling on Digital Microfluidic Biochips (10:15am)Daniel Grissom, Philip Brisk - Univ. of California, Riverside, CA

3.3 Realizing Reversible Circuits Using a New Class of Quantum Gates (10:30am)

Zahra Sasanian, Michael Miller - Univ. of Victoria, Victoria, BC, CanadaRobert Wille - Univ. of Bremen, Germany

3.4 Physical Synthesis onto a Sea-of-Tiles with Double-Gate Silicon Nanowire Transistors (10:45am)

Shashikanth Bobba, Michele De Marchi, Yusuf Leblebici, Giovanni De Micheli - Ecole Polytechnique Fédérale de Lausanne, Switzerland

3.5 A Microgrid View of Energy Efficient Systems (11:00am)Rajesh Gupta - Univ. of California at San Diego, La Jolla, CA

Emerging TechnologiesRoom: 300

1 PANEL: WILL RELIABILITY BE THE DEATH OF MOORE’S LAW?

10:00 - 11:30amChair:

Ana Hunter - Samsung, San Jose, CASpeakers:

Naresh R. Shanbhag - Univ. of Illinois at Urbana-Champaign, Urbana, ILJose Maiz - Intel Corp., Portland, ORSani Nassif - IBM Research, Austin, TXSubhasish Mitra - Stanford Univ., Stanford, CAGoeran Jerke - Robert Bosch GmbH, Reutlingen, Germany

Design for ManufacturabilityRoom: 305The latest technology roadmap cites “reliability and resilience” as key long-term challenges to continue the Moore’s Law scaling. How much will electromigration, aging, and thermal effects limit the benefits of smaller process geometries? Is the cost of reliability (margins, area, power) a showstopper? To what extent will new architectures and design tools mask unreliability? This panel discusses these issues and looks at how reliability challenges could limit product design over the coming decade.

www.DAC.com Best Paper Nominees are Denoted in Orange12


5 DESIGN AND DATA SECURITY: IS IT EVEN POSSIBLE?

Chair Mohammad Tehranipoor - Univ. of Connecticut, Mansfield, CT

Threats against IC design information and data integrity are on the rise. The potential costs of IP counterfeiting and secure data exposure motivate research activity in this area. As design processes are distributed physically, the vulnerable attack surface increases dramatically, necessitating robust security approaches. This session explores hardware design approaches to protecting design information from theft or modification, and securing sensitive data on-chip. The techniques investigated in the papers of this session include the design of physically unclonable functions, hardware trojan detection, dynamic power analysis defenses, and design obfuscation.

5.1 A Code Morphing Methodology to Automate Power Analysis Countermeasures (10:00am)

Gerardo Pelosi, Giovanni Agosta, Alessandro Barenghi - Politecnico di Milano, Milan, Italy

5.2 Security Analysis of Logic Obfuscation (10:15am)Jeyavijayan Rajendran, Ramesh Karri - Polytechnic Institute of New York Univ., Brooklyn, NYYoungok Pino - Air Force Research Lab, Rome, NYOzgur Sinanoglu - New York Univ., Abu Dhabi, United Arab Emirates

5.3 Hardware Trojan Horse Benchmark via Optimal Creation and Placement of Malicious Circuitry (10:30am)

Miodrag Potkonjak, Sheng Wei - Univ. of California, Los Angeles, CAKai Li, Farinaz Koushanfar - Rice Univ., Houston, TX

5.4* On Improving the Uniqueness of Silicon-Based Physically Unclonable Functions via Optical Proximity Correction (10:45am)

Domenic Forte, Ankur Srivastava - Univ. of Maryland, College Park, MD

10:00 - 11:30am Room: 308

6 SYSTEM SIMULATION: THE NEED FOR SPEED!

10:00 - 11:30amChair

Gunar Schirner - Northeastern Univ., Boston, MASimulation is an integral part of system design and exploration. There is a continued quest for speeding and improving the performance of full system simulation by either finding the right level of abstraction or accelerating the underlying simulation infrastructure. This session presents state of the art approaches from both domains ranging from hybrid MPSoC model to GPU platforms, focusing on optimizing synchronization, parallelizing, and accelerating full system simulation.

6.1 Transformer: A Functional-Driven CycleAccurate Multicore Simulator (10:00am)

Zhenman Fang, Qinghao Min, Keyong Zhou, Yi Lu, Yibin Hu, Weihua Zhang, Binyu Zang - Fudan Univ., Shanghai, ChinaHaibo Chen - Shanghai Jiao Tong Univ., Shanghai, ChinaJian Li - IBM Corp., Austin, TX

6.2 SAGA: SystemC Acceleration on GPU Architectures (10:15am)Sara Vinco, Franco Fummi - Univ. of Verona, ItalyDebapriya Chatterjee, Valeria Bertacco - Univ. of Michigan, Ann Arbor, MI

6.3 Synchronization for Hybrid MPSoC Full-System Simulation (10:30am)Luis Gabriel Murillo, Juan Eusse, Jovana Jovic, Sergey Yakoushkin, Rainer Leupers, Gerd Ascheid - RWTH Aachen Univ., Aachen, Germany

6.4 A Non-Intrusive Timing Synchronization Interface for Hardware-Assisted HW/SW Co-Simulation (10:45am)

Yu-Hung Huang, Yi-Shan Lu, Hsin-I Wu, Ren-Song Tsay - National Tsing Hua Univ., HsinChu, Taiwan

Room: 310

4 BE EFFICIENT: LOW-POWER DESIGN TECHNIQUES

10:00 - 11:30am

Chair Hamid Mahmoodi - San Francisco State Univ., San Francisco, CA

Power consumption is one of the critical challenges in advanced technologies. Exploiting power and sleep modes reduces power when the circuit is idle as in the first paper in the session, or to dynamically adjust voltage and frequency (DVFS) as in the second. Memories make up a large portion of current and future systems and it is important to accurately estimate their power consumption as in the third paper, or to reduce the energy of emerging memory technologies, as in the fourth paper.

4.1 A Semiempirical Model for Wakeup Time Estimation in Power-Gated Logic Clusters (10:00am)

Vivek D. Tovinakere, Olivier Sentieys, Steven Derrien - Univ. de Rennes 1, Lannion, France

4.2 Cost-Effective Power Delivery to Support Per-Core Voltage Domains for Power-Constrained Processors (10:15am)

Nam Sung Kim, Hamid Reza Ghasemi, Abhishek Sinkar - Univ. of Wisconsin, Madison, WIMike Schulte - Advanced Micro Devices, Inc., Austin, TX

4.3 A Hybrid and Adaptive Model for Predicting Register File and SRAM Power Using a Reference Design (10:30am)

Eric Donkoh, Alicia P. Lowery, Emily Shriver - Intel Corp., Hillsboro, OR4.4 Coding-Based Energy Minimization for Phase Change Memory (10:45am)

Azalia Mirhoseini, Farinaz Koushanfar - Rice Univ., Houston, TXMiodrag Potkonjak - Univ. of California, Los Angeles, CA

Room: 306 Low-Power Design and Power Analysis

Embedded System Validation and Verification

System Level Design and Communication

Best Paper Nominees are Denoted in Orange www.DAC.com 13


8 SPECIAL SESSION: CAN EDA COMBAT THE RISE OF ELECTRONIC COUNTERFEITING?

Chair Miodrag Potkonjak - Univ. of California, Los Angeles, CA

The Semiconductor Industry Association (SIA) estimates that counterfeiting costs the US semiconductor companies $7.5B in lost revenue, and this is indeed a growing global problem. Repackaging the old ICs, selling the failed test parts, as well as gray marketing, are the most dominant counterfeiting practices. Can technology do a better job than lawyers? What are the technical challenges to be addressed? What EDA technologies will work: embedding IP protection measures in the design phase, developing rapid post-silicon certification, or counterfeit detection tools and methods?

8.1 Can EDA Combat the Rise of Electronic Counterfeiting? Carl McCants - Defense Advanced Research Projects Agency, Arlington, VAWilliam Bryson - Analytical Solutions, Inc., Albuquerque, NMMatthew Sale - U.S. Naval Surface Warfare Center, Crane, INPeilin Song - IBM Research, Yorktown Heights, NYFarinaz Koushanfar - Rice Univ., Houston, TXSaverio Fazzari - Booz Allen Hamilton, Inc., Arlington, VAMiodrag Potkonjak - Univ. of California, Los Angeles, CA

1:30 - 3:00pm Room: 304

7 PANEL: SYSTEM MODELS - DOES ONE SIZE FIT ALL?

1:30 - 3:00pmChair

Brian Bailey - EETimes EDA Designline, Oregon City, ORSpeakers:

Stuart Swan - Cadence Design Systems, Inc., San Jose, CARick Higgins - Qualcomm, Inc., San Diego, CAJohn Goodenough - ARM, Inc., San Jose, CAFrederic Risacher - Research in Motion, Ltd., Waterloo, ON, CanadaAndrea Kroll - Tensilica, Inc., San Jose, CA

System-level modeling is a critical part of product design flows. Developing a single model that simultaneously satisfies the needs of software developers, system architects, hardware developers, and verification engineers is hard. Time of availability, usage models, accuracy requirements, development effort, and speed vary greatly. Is it possible for one size to fit all? Who will provide the models? Who will pay for them? The panelists will review different aspects of system modeling and discuss which abstraction levels best address specific user requirements.

Room: 305 System Level Design and Communication

General Interest

9 RELIABILITY: FROM ATOMS TO 3-D

1:30 - 3:00pmChair

Angan Das - Intel Corp., Santa Clara, CAWith shrinking device sizes and increasing design complexity, reliability has become a critical issue. Besides traditional reliability issues for power delivery networks and clock signals, new challenges are emerging. This session presents papers that cover a wide spectrum of reliability issues including long-term device aging, verification of power and 3-D ICs, and high-integrity, low-power clock networks.

9.1* Physics Matters: Statistical Aging Prediction under Trapping/Detrapping (1:30pm)

Jyothi Bhaskarr Velamala, Ketul B. Sutaria, Yu Cao - Arizona State Univ., Tempe, AZTakashi Sato - Kyoto Univ., Kyoto, Japan

9.2 Library-Aware Resonant Clock Synthesis (LARCS) (1:45pm)Xuchu Hu - Cadence Design Systems, Inc., Univ. of California, Santa Cruz, CAWalter Condley, Matthew Guthaus - Univ. of California, Santa Cruz, CA

9.3 Incremental Power Grid Verification (2:00pm)Abhishek, Farid N. Najm - Univ. of Toronto, Toronto, ON, Canada

9.4 Analysis of DC Current Crowding in Through-Silicon-Vias and its Impact on Power Integrity in 3-D ICs (2:15pm)

Sung Kyu Lim, Xin Zhao - Georgia Institute of Technology, Atlanta, GAMichael Scheuermann - IBM T.J. Watson Research Ctr., Yorktown Heights, NY

Room: 300 Verification and Test



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EDA FOR EMERGING APPLICATIONS AT THE KILOMETER, METER, MICRON, AND NANOMETER SCALES

FACING DEPENDABILITY: SYSTEM-LEVEL SOLUTIONS AND CYBERCAR CHALLENGES

VOLATILE OR NON-VOLATILE? THAT’S THE QUESTION

Chair Sai-Wang (Rocco) Tam - Marvell Semiconductor, Inc., Santa Clara, CA

The design automation community has traditionally been both active and successful in accelerating the realization of hardware for emerging application spaces. Of growing interest are energy-efficient living spaces and healthcare. The first two presentations in this session address cyber physical systems that could make home appliances more energy-efficient and improve human mobility. Also of significant interest are wireless communication and new display technologies. The last two presentations provide a discussion of MEMS-based filters that could enable software-defined radio, and techniques for managing Vth and mobility variations for improved LED displays.

Chair Hans-Joachim Wunderlich - Univ. of Stuttgart, Stuttgart, Germany

Dependability has became a major design constraint for embedded systems. Whereas early work on dependability has concentrated at lower abstraction levels, recent research increasingly explores system-level approaches. Run-time adaptivity is a promising approach to cope with the dependability challenges at the system level. This session addresses system-level dependability from several facets such as analysis, cure, and diagnosis. The last paper, a perspective, outlines how the arrival of Cybercars calls for novel abstractions, models, protocols, design methodologies, testing and evaluation tools to automate the integration, and analysis of the sophisticated critical dependeability and security requirements.

11.1 Towards Fault-Tolerant Embedded Systems with Imperfect Fault Detection (1:30pm)

Jia Huang, Kai Huang, Andreas Raabe, Christian Buckl - fortiss GmbH, Munich, GermanyAlois Knoll - Technische Univ. München, Germany

Chair Tei-Wei Kuo - National Taiwan Univ., Taipei City, Taiwan

Non-volatile memories are attractive because they retain information even when they are powered off. However, several challenges need to be addressed before they can be successfully deployed. One major problem is the limited number of writes that non-volatile memory cells can endure before they start failing. Papers in this session propose architectural schemes to improve the lifetime and reliability of non-volatile memories with minimal power and performance overheads.

12.1 Software Controlled Cell Bit-Density to Improve NAND Flash Lifetime (1:30pm)

Xavier Jimenez, David Novo, Paolo Ienne - Ecole Polytechnique Fédérale de Lausanne, Switzerland

10.1 Tracking Appliance Usage Information in Residential Settings Using Off-the-Shelf Low-Frequency Meters (1:30pm)

Deokwoo Jung - Advanced Digital Sciences Center, SingaporeAthanasios Bamis - Univ. of Connecticut, Storrs, CTAndreas Savvides - Yale Univ., New Haven, CT

10.2 Implementing an FPGA System for Real-Time Intent Recognition for Prosthetic Legs (1:45pm)

Xiaorong Zhang, He Huang, Qing Yang - Univ. of Rhode Island, Kingston, RI10.3 Statistical Design and Optimization for Adaptive Post-silicon Tuning of MEMS Filters (2:00pm)

Fa Wang, Gokce Keskin, Andrew Phelps, Jonathan Rotner, Xin Li, Gary K. Fedder, Tamal Mukherjee, Larry Pileggi - Carnegie Mellon Univ., Pittsburgh, PA

10.4 Generic Low-Cost Characterization of VTH and Mobility Variations in LTPS TFTs for Non-Uniformity Calibration of Active-Matrix OLED Displays (2:15pm)

Reza Chaji, Javid Jaffari - IGNIS Innovations, Inc., Waterloo, ON, Canada

11.2 Steady-State Dynamic Temperature Analysis and Reliability Optimization for Embedded Multiprocessor Systems (1:45pm)

Ivan Ukhov, Min Bao, Petru Eles, Zebo Peng - Linköping Univ., Linköping, Sweden

11.3 Considering Diagnosis Functionality during Automatic System-Level Design of Automotive Networks (2:00pm)

Michael Glass, Michael Eberl, Jürgen Teich - Univ. of Erlangen-Nuremberg, GermanyUlrich Abelein - Audi AG, Ingolstadt, Germany

11.4 Meta-Cure: A Reliability Enhancement Strategy for Metadata in NAND Flash Memory Storage Systems (2:15pm)

Yi Wang, Zili Shao - The Hong Kong Polytechnic Univ., Hong KongLuis Angel D. Bathen, Nikil Dutt - Univ. of California, Irvine, CA

11.5 EDA for Secure and Dependable Cybercars: Challenges and Opportunities (2:30pm)

Farinaz Koushanfar - Rice Univ., Houston, TXIng. Ahmad-Reza Sadeghi, Hervé Seudié - Technische Univ. Darmstadt, Germany

12.2 Observational Wear Leveling: An Efficient Algorithm for Flash Memory Management (1:45pm)

Chundong Wang, Weng-Fai Wong - National Univ. of Singapore, Singapore12.3 Cache Revive: Architecting Volatile STT-RAM Caches for Enhanced Performance in CMPs (2:00pm)

Adwait Jog, Cong Xu, Yuan Xie, Vijaykrishnan Narayanan, Chita R. Das - Pennsylvania State Univ., University Park, PAAsit K. Mishra, Ravishankar Iyer - Intel Corp., Hillsboro, OR

12.4 Point and Discard: A Hard-Error-Tolerant Architecture for Non-Volatile Last Level Caches (2:15pm)

Jue Wang, Xiangyu Dong, Yuan Xie - Pennsylvania State Univ., University Park, PA

1:30 - 3:00pm

1:30 - 3:00pm

1:30 - 3:00pm

Room: 306

Room: 308

Room: 310

Emerging Technologies

Embedded Design Methodology and Case Studies

Embedded Architecture & Platforms





13PANEL: WILL YOUR NEXT ASIC EVER BE AN FPGA?

Chair: Kevin Morris - EE Journal, Portland, OR

Speakers: Brent Przybus - Xilinx, Inc., San Jose, CAMisha Burich - Altera Corp., San Jose, CABill Lynch - Huawei Technologies Co., Ltd., Santa Clara, CADave Ofelt - Juniper Networks, Inc., Sunnyvale, CAJeanne Trinko Mechler - IBM Corp., Burlington, VTJohn Frediani - Advantest America, Inc., Cupertino, CA

As each technology node increases in cost, the economics for FPGAs become more compelling. FPGAs have gotten larger, faster, and cooler while still maintaining flexibility. Have these factors brought us to a tipping point? Alternatives in process node, shuttles, and 3-D IC offer choices in the cost, performance, and power tradeoffs. What products are on the precipice of a decision in favor of FPGAs? Witness our expert panelists define the tradeoff point between FPGAs and ASICs.

4:00 - 6:00pm Room: 305

14 SPECIAL SESSION: SELF-AWARE AND ADAPTIVE TECHNOLOGIES: THE FUTURE OF COMPUTING SYSTEMS?

4:00 - 6:00pmChair

Xiaoyun Zhu - VMware, Inc., Palo Alto, CAThis session will present contributions from industry and universities toward the realization of next-generation computing systems based on Self-Aware computing. Self-Aware computing is an emerging system design paradigm aimed at overcoming the exponentially increasing complexity of modern computing systems and improving performance, utilization, reliability, and programmability. In a departure from current systems which are based on design abstractions that have persisted since the 1960s which place significant burden on programmers and chip designers, Self-Aware systems mitigate complexity by observing their own runtime behavior, learning, and taking actions to optimize behaviors automatically.

14.1 Self-Aware Computing in the Angstrom ProcessorSrini Devadas, Henry Hoffman, George Kurian, Eric Lau, Jason E. Miller, Sabrina M. Neuman, Mahmut Sinangil, Yildiz Sinangil, Anant Agarwal, Anantha P. Chandrakasan - Massachusetts Institute of Technology, Cambridge, MAJim Holt - Massachusetts Institute of Technology, Freescale Semiconductor, Inc., Cambridge, MAMartina Maggio - Lund Univ., Lund, Sweden

14.2 The Case for Elastic Operating System Services in fosLamia Youseff - Google, Inc., Fremont, WANathan Beckmann, Harshad Kasture, Charles Gruenwald, Anant Agarwal - Massachusetts Institute of Technology, Cambridge, MADavid Wentzlaff - Princeton Univ., Princeton, NJ

14.3 A Compiler and Runtime for Heterogeneous ComputingRodric Rabbah, Joshua Auerbach, David F. Bacon, Ioana Burcea, Perry Cheng, Stephen J. Fink, Sunil Shukla - IBM T.J. Watson Research Ctr., Yorktown Heights, NY

14.4 The Helix Project: Overview and DirectionsSimone Campanoni, Glenn Holloway, Gu-Yeon Wei, David Brooks - Harvard Univ., Cambridge, MATimothy Jones - Univ. of Cambridge, United Kingdom

Room: 304

15 WHY MODEL? BECAUSE REALITY IS COMPLICATED ENOUGH!

4:00 - 6:00pmChair

Ibrahim Elfadel - Masdar Institute of Science and Technology, Abu Dhabi, United Arab Emirates

Models are an essential part of design. Good models capture the required details of the underlying physical system while abstracting away the unimportant behavior. They allow us to bridge between levels of representation, to account for new effects, and handle complexity, both in size as well as functionality, enabling reliable predictions of behavior and performance. The papers in this session address different aspects of the extremely important and challenging problem of developing compact and efficient models for current and future technologies ranging from thermal-mechanical stress in 3-D ICs, FINFETs, interconnect effects, circuit non-linearity, and delay sensitivity.

15.1 Exploring Sub-20nm FinFET Design with Predictive Technology Models (4:00pm)

Saurabh Sinha, Greg Yeric, Vikas Chandra, Brian Cline - ARM, Inc., Austin, TXYu Cao - Arizona State Univ., Tempe, AZ

15.2 Fast Nonlinear Model Order Reduction via Associated Transforms of High-Order Volterra Transfer Functions (4:15pm)

Ngai Wong, Yang Zhang, Haotian Liu, Qing Wang, Neric Fong - The Univ. of Hong Kong, Hong Kong

15.3 AMOR: An Efficient Aggregating Based Model Order Reduction Method for Many-Terminal Interconnect Circuits (4:30pm)

Xuan Zeng, Yangfeng Su, Fan Yang - Fudan Univ., Shanghai, China15.4 BLAST: Efficient Computation of Nonlinear Delay Sensitivities in Electronic and Biological Networks using Barycentric Lagrange Enabled Transient Adjoint Analysis (4:45pm)

Arie Meir, Jaijeet Roychowdhury - Univ. of California, Berkeley, CA15.5 DAE2FSM: Automatic Generation of Accurate Discrete-Time Logical Abstractions for Continuous-Time Circuit Dynamics (5:00pm)

Karthik V. Aadithya, Jaijeet Roychowdhury - Univ. of California, Berkeley, CA15.6* Chip/Package Co-Analysis of Thermo-Mechanical Stress and Reliability in TSV-based 3-D ICs (5:15pm)

Moongon Jung, Sung Kyu Lim - Georgia Institute of Technology, Atlanta, GADavid Z. Pan - Univ. of Texas, Austin, TX

Room: 300 Circuit and Interconnect Analysis

General Interest


EDA FOR EMERGING APPLICATIONS AT THE KILOMETER, METER, MICRON, AND NANOMETER SCALES

www.DAC.com Best Paper Nominees are Denoted in Orange. Perspective Papers are Denoted in Dark Gray.16


16

17

18

IS FORMAL VERIFICATION READY FOR THE SYSTEM LEVEL?

NOCS NEXT TOP MODEL: FROM SYSTEM-LEVEL TO PROTOTYPE

TIMING ANALYSIS AND SOFTWARE-CONTROLLED MEMORY: ARE WE SAFE?

Chair Erik Seligman - Intel Corp., Hillsboro, OR

Formal verification has largely displaced simulation for Combinational Equivalence Checking. Formal technology for Sequential Equivalence Checking has made inroads for applications such as retiming and power optimization. This session explores the application of formal techniques at the system level. The papers cover topics such as verification of SystemC designs, formally relating abstract models to synthesized RTL, equivalence checking for behaviorally synthesized pipelines, and a novel application in the domain of network security. The session also features a perspective paper on the interplay of induction and deduction in formal verification.

16.1 Symbolic Model Checking on SystemC Designs (4:00pm)Chun-Nan Chou, Yen-Sheng Ho, Chiao Hsieh, Chung-Yang (Ric) Huang - National Taiwan Univ., Taipei, Taiwan

Chair Fabien Clermidy - CEA-LETI, Grenoble, France

What do “Attackboards,” “Aging,” and “Wide-I/O” have in common? They represent some of the key new contributions highlighted in recent Network-on-Chip (NoC) research. This session is an exciting mix of innovative and more accurate methods for modeling NoC designs, new architectures for NoCs, and fabricated prototype chips at relevant technology nodes. All of these provide tremendous insights into future NoCs. This session also has a significant component of 3-D NoC design and prototyping.

17.1 Cost-Efficient Buffer Sizing in Shared-Memory 3-D MPSoCs using Wide I/O Interfaces (4:00pm)

Sahar Foroutan, Frédéric Pétrot - TIMA Laboratory, Grenoble Institute of Technology, Grenoble, FranceAbbas Sheibanyrad - TIMA Laboratory/CNRS, Grenoble, France

17.2 Attackboard: A Novel Dependency-Aware Traffic Generator for Exploring NoC Design Space (4:15pm)

Yoshi Shih-Chieh Huang, Yu-Chi Chang, Tsung-Chan Tsai, Yuan-Ying Chang, Chung-Ta King - National Tsing Hua Univ., Hsinchu, Taiwan

Chair Frank Slomka - Univ. of Ulm, Germany

The need to consider precise timing behavior is one of the key requirements of embedded systems integrated into a physical environment. However, the generation of tight and safe timing guarantees is very difficult. A second difficulty in the design of embedded systems results from the need to use multiple, heterogeneous memories. The corresponding memory architectures require explicit software control. The papers in this session provide novel contributions in worst-case execution-time estimation and software memory management.

18.1* WCET-Centric Partial Instruction Cache Locking (4:00pm)Huping Ding, Tulika Mitra - National Univ. of Singapore, SingaporeYun Liang - Advanced Digital Sciences Center, Singapore

18.2 Worst-Case Execution Time Analysis for Parallel Run-Time Monitoring (4:15pm)

Daniel Lo, G. Edward Suh - Cornell Univ., Ithaca, NY

16.2 System Verification of Concurrent RTL Modules by Compositional Path Predicate Abstraction (4:15pm)

Joakim Urdahl, Dominik A. Stoffel, Markus Wedler, Wolfgang Kunz - Univ. of Kaiserslautern, Germany

16.3 Equivalence Checking for Behaviorally Synthesized Pipelines (4:30pm)Kecheng Hao, Fei Xie - Portland State Univ., Portland, ORSandip Ray - Univ. of Texas, Austin, TX

16.4 Proving Correctness of Regular Expression Accelerators (4:45pm)Mitra Purandare, Kubilay Atasu, Christoph Hagleitner - IBM Research - Zurich, Switzerland

16.5 Sciduction: Combining Induction, Deduction, and Structure for Verification and Synthesis (5:00pm)

Sanjit A. Seshia - Univ. of California, Berkeley, CA

17.3 Towards Graceful Aging Degradation in NoCs Through an Adaptive Routing Algorithum (4:30pm)

Koushik Chakraborty, Kshitij Bhardwaj, Sanghamitra Roy - Utah State Univ., Logan, UT

17.4* Explicit Modeling of Control and Data for Improved NoC Router Estimation (4:45pm)

Siddhartha Nath, Andrew B. Kahng, Bill Lin - Univ. of California at San Diego, La Jolla, CA

17.5 Approaching the Theoretical Limits of a Mesh NoC with a 16-Node Chip Prototype in 45nm SOI (5:00pm)

Sunghyun Park, Tushar Krishna, Chia-Hsin O. Chen, Bhavya Daya, Li-Shiuan Peh, Anantha P. Chandrakasan - Massachusetts Institute of Technology, Cambridge, MA

17.6 High Radix Self-Arbitrating Switch Fabric with Multiple Arbitration Schemes and Quality of Service (5:15pm)

Sudhir K. Satpathy, Reetuparna Das, Ronald Dreslinski, Trevor Mudge, Dennis Sylvester, David Blaauw - Univ. of Michigan, Ann Arbor, MI

18.3 Conforming the Runtime Inputs for Hard Real-Time Embedded Systems (4:30pm)

Kai Huang, Gang Chen, Christian Buckl - fortiss GmbH, Munich, GermanyAlois Knoll - Technische Univ. München, Germany

18.4 STM Concurrency Control for Embedded Real-Time Software with Tighter Time Bounds (4:45pm)

Mohammed T. El-Shambakey, Binoy Ravindran - Virginia Polytechnic Institute and State Univ., Blacksburg, VA

18.5 HaVOC: A Hybrid-Memory-Aware Virtualization Layer for On-Chip Distributed ScratchPad and Non-Volatile Memories (5:00pm)

Luis Angel D. Bathen, Nikil Dutt - Univ. of California, Irvine, CA18.6 Age-Based PCM Wear Leveling with Nearly Zero Search Cost (5:15pm)

Pi-Cheng Hsiu - Academia Sinica, Taipei, TaiwanChi-Hao Chen, Chia-Lin Yang - National Taiwan Univ., Taipei, TaiwanTei-Wei Kuo - National Taiwan Univ., Academia Sinica, Taipei, TaiwanCheng-Yuan Michael Wang - Macronix International Co., Ltd., Hsinchu, Taiwan

4:00 - 6:00pm

4:00 - 6:00pm

4:00 - 6:00pm

Room: 306

Room: 308

Room: 310

Verification and Test


Embedded Software


TECHNICAL SESSIONSWEDNESDAY, JUNE 6

20 SPECIAL SESSION: ROUTING-DRIVEN DESIGN CLOSURE

Chair Shankar Krishnamoorthy - Mentor Graphics Corp., San Jose, CA

With each subsequent technology node, routing complexity increases exponentially to handle the explosion of design rules and routing constraints. Metal layer stacks are becoming increasingly complex, with varying degrees of wire widths and interconnect parasitics becoming the norm. This session discusses design closure from a routing-centric perspective from three angles: core routing technology, guiding physical design to create a friendlier hand-off to routing, and reducing routing complexity by changing the underlying methodology.

20.1 Algorithms and Data Structures for Fast and Good VLSI Routing Dirk Mueller, Michael Gester, Tim Nieberg, Christian Panten, Christian Schulte, Jens Vygen - Univ. of Bonn, Germany

20.2 Guiding a Physical Design Closure System to Produce Easier-to-Route Designs with More Predictable Timing

Zhuo Li, Gi-Joon Nam, Cliff Sze - IBM Research - Austin, TXCharles Alpert - IBM Corp., Cedar Park, TXNatarajan Viswanathan, Nancy Zhou - IBM Systems and Technology Group, Austin, TX

20.3 Rule Agnostic Routing by Using Design Fabrics Gyuszi Suto - Intel Corp., Hillsboro, OR

9:00 - 10:30am Room: 304

19

21

PANEL: HIGH-LEVEL SYNTHESIS PRODUCTION DEPLOYMENT: ARE WE READY?

STORING, COMPUTING, AND STORING WHILE COMPUTING: THE NEW FACE OF NON-VOLATILITY IN SYSTEMS

9:00 - 10:30am

9:00 - 10:30am

Chair Clem Meas - quickSTART Consulting, Boulder, CO

Speakers: Eli Singerman - Intel Corp., Haifa, IsraelKazutoshi Wakabayashi - NEC Corp., Tokyo, JapanMark Johnstone - Freescale Semiconductor, Inc., Austin, TXMark Warren - Cadence Design Systems, Inc., San Jose, CAVinod Kathail - Xilinx, Inc., San Jose, CAAndres Takach - Calypto Design Systems, Inc., Wilsonville, OR

Chair Charles Augustine - Intel Corp., Hillsboro, OR

As energy-efficient designs leverage non-volatility in logic and memory, serious challenges emerge in design and design automation. How can nanomagnets be efficiently used in logic? What new applications are driven using these disruptive technologies? This session is intended to provide insights into design philosophies using nanomagnetic and resistive technologies. The four papers encompass a wide spectrum of topics from energy optimization in spin-transfer-torque memories to efficient neural algorithms mapped onto RRAM arrays.

21.1 Making Non-Volatile Nanomagnet Logic Non-Volatile (9:00am)Aaron Dingler, Steve J. Kurtz, Michael T. Niemier, Xiaobo Sharon Hu, Gyorgy Csaba, Joseph Nahas, Wolfgang Porod, Gary H. Bernstein, Peng Li, Vijay Karthik Sankar - Univ. of Notre Dame, Notre Dame, IN

High-level synthesis has historically over-promised and under-delivered, but that is all about to change. Or, is it? Are we ready to climb the ladder up to the next level of design abstraction? Watch our panelists debate whether today’s technology can handle system validation, IP integration and optimization, power/performance constraints, and design verification challenges. Find out if we are about to connect the world of embedded software development to hardware design.

21.2 mLogic: Ultra-Low Voltage Non-Volatile Logic Circuits Using STT-MTJ Devices (9:15am)

Daniel Morris, David M. Bromberg, Jian-Gang (Jimmy) Zhu, Larry Pileggi - Carnegie Mellon Univ., Pittsburgh, PA

21.3 Future Cache Design using STT MRAMs for Improved Energy Efficiency: Devices, Circuits, and Architecture (9:30am)

Sang Phill Park, Sumeet K. Gupta, Niladri N. Mojumder, Anand Raghunathan, Kaushik Roy - Purdue Univ., West Lafayette, IN

21.4 Hardware Realization of BSB Recall Function with Memristor Crossbar Arrays (9:45am)

Miao Hu, Hai Li - Polytechnic Institute of New York Univ., Brooklyn, NYQing Wu, Garrett S. Rose - Air Force Research Lab, Rome, NY

Room: 305

Room: 300

High-Level and Logic Synthesis


Physical Design



22

23

24

YOU CAN COUNT ON ME: WHY IT’S OK TO BE IMPRECISE OR UNRELIABLE

OPTIMIZATION TO THE RESCUE OF ANALOG

XTERMINATING BUGS

Chair Qinru Qiu - Syracuse Univ., Syracuse, NY

For some applications, it is sometimes worth giving up a limited amount of precision or reliability if that leads to significant power savings. Similarly, being able to operate “off the grid” means one needs to give up the certainty of traditional power sources to enable power harvesting opportunities. The papers in this session illustrate the trade-offs inherent in operating in extreme low-power regimes.

22.1 A Methodology for Energy-Quality Tradeoff Using Imprecise Hardware (9:00am)

Jiawei Huang, John Lach, Gabriel Robins - Univ. of Virginia, Charlottesville, VA22.2 On the Exploitation of the Inherent Error Resilience of Wireless Systems under Unreliable Silicon (9:15am)

Georgios Karakonstantis, Andreas Burg - Ecole Polytechnique Fédérale de Lausanne, SwitzerlandChristoph Roth, Christian Benkeser - Eidgenössische Technische Hochschule Zürich, Zürich, Switzerland

Chair Trent McConaghy - Solido Design Automation, Inc., Saskatoon, CA

Today, analog circuit design is a daunting task even for seasoned designers, involving careful sizing of transistors, characterization of RF/microwave elements, and physical placement/routing with extra constraints, all under ever-worsening variabilities and uncertainties. The papers in this session demonstrate how optimization techniques can be leveraged to address these analog design challenges. Interestingly, the papers employ rather non-traditional approaches for analog, such as Gaussian process surrogate model from machine learning, robust optimization with non-fixed uncertainty budget, discrete grid-based optimization, and integer linear programming.

Chair Sharad Kumar - Freescale Semiconductor, Inc., Noida, India

Post-silicon debug impacts production cost and test times, calling for innovative work in on-line error detection. The papers in this session cover issues related to optimizing testing times and data volumes, detecting difficult bugs, and performing concurrent error detection in AES cryptographic circuitry.

24.1 X-Tracer: A Reconfigurable X-Tolerant Trace Compressor for Silicon Debug (9:00am)

Feng Yuan, Xiao Liu, Qiang Xu - The Chinese Univ. of Hong Kong, Shatin, Hong Kong

22.3 Near-Optimal, Dynamic Module Reconfiguration in a Photovoltaic System to Combat Partial Shading Effects (9:30am)

Xue Lin, Yanzhi Wang, Siyu Yue, Massoud Pedram - Univ. of Southern California, Los Angeles, CADonghwa Shin, Naehyuck Chang - Seoul National Univ., Seoul, Republic of Korea

22.4 Networked Architecture for Hybrid Electrical Energy Storage Systems (9:45am)

Younghyun Kim, Sangyoung Park, Naehyuck Chang - Seoul National Univ., Seoul, Republic of KoreaYanzhi Wang, Qing Xie, Massoud Pedram - Univ. of Southern California, Los Angeles, CA

23.1 A New Uncertainty Budgeting Based Method for Robust Analog/Mixed-Signal Design (9:00am)

Janet Roveda - Univ. of Arizona, Tucson, AZJin Sun - Orora Design Technologies, Inc., Issaquah, WAPriyank Gupta - Cirrus Logic, Inc., Tucson, AZ

23.2 Variability-Aware, Discrete Optimization for Analog Circuits (9:15am)Seobin Jung, Yunju Choi, Jaeha Kim - Seoul National Univ., Seoul, Republic of Korea

23.3 Efficient Multi-Objective Synthesis for Microwave Components Based on Computational Intelligence Techniques (9:30am)

Georges Gielen, Bo Liu, Hadi Aliakbarian, Soheil Radiom, Guy A. E. Vandenbosch - Katholieke Univ. Leuven, Belgium

23.4 Non-Uniform Multilevel Analog Routing with Matching Constraints (9:45am)

Hung-Chih Ou, Hsing-Chih Chang Chien, Yao-Wen Chang - National Taiwan Univ., Taipei, Taiwan

24.2 Quick Detection of Difficult Bugs for Effective Post-Silicon Validation (9:15am)

David H. Lin, Ted Hong, Farzan Fallah, Subhasish Mitra - Stanford Univ., Stanford, CANagib Hakim - Intel Corp., Santa Clara, CA

24.3 Test Data Volume Optimization for Diagnosis (9:30am)Hongfei Wang, Osei Poku, Xiaochun Yu, Sizhe Liu, Ibrahima Komara, Shawn Blanton - Carnegie Mellon Univ., Pittsburgh, PA

24.4 Invariance-Based Concurrent Error Detection for Advanced Encryption Standard (9:45am)

Xiaofei Guo, Ramesh Karri - Polytechnic Institute of New York Univ., Brooklyn, NY

9:00 - 10:30am

9:00 - 10:30am

9:00 - 10:30am

Room: 306

Room: 308

Room: 310

Low-Power Design and Power Analysis

Analog/Mixed-Signal/RF Design


19


www.DAC.com Best Paper Nominees are Denoted in Orange. Perspective Papers are Denoted in Dark Gray.

26

27

SPECIAL SESSION: BRAIN-INSPIRED AUTONOMOUS COMPUTING AND MODELING

DESIGN, THE NEXT GENERATION: FROM ROUTING TO CAPTURING DESIGN EXPERTISE

Chair Yiran Chen - Univ. of Pittsburgh, PA

A human brain weighs ~1.5kg, and is made up of 100 billion neurons connected via an incredibly dense and complex neuron network. The network contains 4km of wire in every cubic millimeter, offering >100-million MIPS computing capability and <20W power. The autonomous computing model inspired by brain structure (also known as neuromorphic computing) obtained the increased attentions from VLSI design and EDA communities following the recent device inventions like memristor, nanotube/wire, and CMOS/molecular circuitries. The three invited papers introduce the grand challenges of autonomous computing system and architecture, and discuss the-state-of-the-art neuromorphic computing systems, design methodologies, computing modeling, and applications.

Chair Charles Chiang - Synopsys, Inc., Mountain View, CA

A bottleneck for complex designs is routing: the wiring of billion-gate designs is staggeringly complex, and the problem will only get worse. Routing solutions must be high quality, meeting timing and manufacturability constraints. This session provides strides forward on some of today’s most important challenges, with triple patterning innovations, more accurate routability estimation, SAT-based cell routing for higher quality, and a novel obstacle-avoiding rectilinear Steiner tree approach for multiple layers. As the industry hurtles forward with process technology, routing remains the critical step. The last paper, both a historical and futuristic perspective, addresses increasing design complexity by embedding designer knowledge into systems we create, calling for creating constructors, and not design instances.

27.1* Triple Patterning Aware Routing and its Comparison with Double Patterning Aware Routing in 14nm Technology (1:30pm)

Qiang Ma, Hongbo Zhang, Martin D. F. Wong - Univ. of Illinois at Urbana-Champaign, Urbana, IL

26.1 Challenges Towards Brain-Inspired Autonomous Computing Architectures

Michael Hayduk, Robinson E. Pino - Air Force Research Lab, Rome, NY26.2 Accelerating Neuromorphic Vision Algorithms for Recognition

Vijaykrishnan Narayanan, Ahmed Al Maashri, Michael Debole, Matthew Cotter, Nandhini Chandramoorthy, Yang Xiao - Pennsylvania State Univ., University Park, PAChaitali Chakrabarti - Arizona State Univ., Phoenix, AZ

26.3 Statistical Memristor Modeling and Case Study in Neuromorphic Computing

Hai Li, Miao Hu - Polytechnic Institute of New York Univ., Brooklyn, NYRobinson E. Pino - Air Force Research Lab, Rome, NYYiran Chen, Beiye Liu - Univ. of Pittsburgh, PA

1:30 - 3:00pm

1:30 - 3:00pm

Room: 304

Room: 300

25 PANEL: IS EDA IN THE CLOUD JUST PIE IN THE SKY?

1:30 - 3:00pm

Chair Nitin Deo - Concept2Silicon Systems, Cupertino, CA

Speakers: Michael Buehler-Garcia - Mentor Graphics Corp., Fremont, CABruce Jewett - Synopsys, Inc., Mountain View, CAAlex Shubat - SiCAD, Inc., Cupertino, CAAnthony Hill - Texas Instruments, Inc., Dallas, TXPravin Desale - LSI Corp., Milpitas, CA

Promises of lower costs, seemingly infinite resources, and faster turnaround times make EDA in the cloud an attractive proposition, but skepticism is prevalent. Some object that EDA in the cloud is not new and failed a decade ago. Others worry about security, confidentiality, and data protection. Do traditional time-based licenses fit in this model? Find out whether design in the cloud is ready for primetime.

Room: 305 Business

Bio Design Automation

Physical Design27.2 GDRouter: Interleaved Global Routing and Detailed Routing for Ultimate Routability (1:45pm)

Yanheng Zhang - Cadence Design Systems, Inc., San Jose, CAChris Chu - Iowa State Univ., Ames, IA

27.3 Standard Cell Routing via Boolean Satisfiability (2:00pm)Nikolai Ryzhenko, Steven M. Burns - Intel Corp., Portland, OR

27.4 An Efficient Algorithm for Multi-Layer Obstacle-Avoiding Rectilinear Steiner Tree Construction (2:15pm)

Chih-Hung Liu, I-Che Chen - Academia Sinica, Taipei, TaiwanDer-Tsai Lee - National Chung-Hsing Univ., Taichung, Taiwan

27.5 Avoiding Game Over: Bringing Design to the Next Level (2:30pm)Mark Horowitz, Ofer Shacham, Megan Wachs, Andrew Danowitz, Sameh Galal, John Brunhaver, Wajahat Qadeer, Sabarish Sankaranarayanan, Artem Vassillev, Steve Richardson - Stanford Univ., Stanford, CA

20



28

29

30

STAYING COOL: MODELING THERMAL EFFECTS IN 3-D AND MULTICORE

SOS: SPECIFICATION, OPTIMIZATION, AND SYNTHESIS IN SYSTEM-LEVEL DESIGN

FUTURE OF IC RELIABILITY

Chair Dhireesha Kudithipudi - Rochester Institute of Technology, Rochester, NY

Power consumption and high junction temperatures are major challenges towards improving the performance of future computing devices. To address these challenges, new effective techniques are needed for design-time modeling and for runtime management. This session proposes new design techniques, such as thermal-sensor allocation and power-modeling validation. For runtime management, new techniques are proposed to improve the spatial thermal estimation from sensor measurements and for maximizing the performance of 3-D processors under thermal and power constraints.

28.1 PowerField: A Transient Temperature-to-Power Technique based on Markov Random Field Theory (1:30pm)

Seungwook Paek, Wongyu Shin, Jaehyeong Sim, Lee-Sup Kim - KAIST, Daejeon, Republic of KoreaSeok-Hwan Moon - Electronics and Telecommunications Research Institute, Daejeon, Republic of Korea

Chair Brett Meyer - McGill Univ., Montréal, QC, Canada

The need for ever-shorter turnaround design times calls for advancements in all aspects of system-level design, including formal modeling, optimization and synthesis. Memory hierarchy design and optimization is a key determinant of system-level performance and power consumption. This session presents a novel model of computation (MoC), synthesis and mapping approaches, as well as an innovative micro-architecture for system-level memory hierarchy design. The last presentation, a perspective, is a reality check for our EDA community: are we on track for embedded system and software development to effectively serve our society?29.1 Static Dataflow with Access Patterns: Semantics and Analysis (1:30pm)

Arkadeb Ghosal, Rhishikesh S. Limaye, Kaushik Ravindran, Ankita Prasad, Guoqiang Wang, Trung N. Tran, Hugo A. Andrade - National Instruments Corp., Berkeley, CAStavros Tripakis - Univ. of California, Berkeley, CA

Chair Alesandro Pinto - United Technologies Research Center, Berkeley, CA

Reliable computation of embedded devices mandates hardware to be trustworthy and protected from various issues: counterfeit and confidentiality attacks, performance failures, and manufacturing defects. The session includes current innovation techniques that address the above-mentioned issues. The papers in the session cover various advancements made using formal and statistical analysis: fingerprinting ICs, dependable computation using ultra-risc processors, obfuscating data for computation in un-trusted cloud, and performance verification.

30.1 A Hybrid Approach to Cyber-Physical Systems Verification (1:30pm)Pratyush Kumar, Kai Lampka, Lothar Thiele - Eidgenössische Technische Hochschule Zürich, Zürich, SwitzerlandDip Goswami, Samarjit Chakraborty - Technische Univ. München, GermanyAnuradha Annaswamy - Massachusetts Institute of Technology, Boston, MA

28.2 EigenMaps: Algorithms for Optimal Thermal Maps Extraction and Sensor Placement on Multicore Processors (1:45pm)

Juri Ranieri, Alessandro Vincenzi, Amina Chebira, David Atienza, Martin Vetterli - Ecole Polytechnique Fédérale de Lausanne, Switzerland

28.3 An Information-Theoretic Framework for Optimal Temperature Sensor Allocation and Full-Chip Thermal Monitoring (2:00pm)

Xin Li, Huapeng Zhou, Shi-Chune Yao - Carnegie Mellon Univ., Pittsburgh, PAChen-Yong Cher, Eren Kursun, Haifeng Qian - IBM T.J. Watson Research Ctr., Yorktown Heights, NY

28.4 Optimizing Energy Efficiency of 3-D Multicore Systems with Stacked DRAM under Power and Thermal Constraints (2:15pm)

Jie Meng, Katsutoshi Kawakami, Ayse K. Coskun - Boston Univ., Boston, MA

29.2 Executing Synchronous Dataflow Graphs on a SPM-Based Multicore Architecture (1:45pm)

Junchul Choi, Soonhoi Ha - Seoul National Univ., Seoul, Republic of KoreaHyunok Oh - Hanyang Univ., Seoul, Republic of KoreaSungchan Kim - Chonbuk National Univ., Jeonju, Republic of Korea

29.3 System-Level Synthesis of Memory Architecture for Stream Processing Sub-Systems of a MPSoC (2:00pm)

Glenn Leary, Weijia Che, Karam S. Chatha - Arizona State Univ., Tempe, AZ29.4 Courteous Cache Sharing: Being Nice to Others in Capacity Management (2:15pm)

Akbar Sharifi, Shekhar Srikantaiah, Mahmut Kandemir, Mary Jane Irwin - Pennsylvania State Univ., University Park, PA

29.5 Embedded Systems - The Neural Backbone of Society (2:30pm)Rolf Ernst - Technische Univ. Braunschweig, Germany

30.2 Reliable Computing with Ultra-Reduced Instruction Set Co-Processors (1:45pm)

Hiren D. Patel, Aravindkumar Rajendiran, Sundaram Ananthanarayanan, Mahesh V. Tripunitara, Siddharth Garg - Univ. of Waterloo, Waterloo, ON, Canada

30.3 Identification of Recovered ICs using Fingerprints from a Light-Weight On-Chip Sensor (2:00pm)

Xuehui Zhang, Nicholas Tuzzio, Mohammad Tehranipoor - Univ. of Connecticut, Storrs, CT

30.4 Confidentiality Preserving Integer Programming for Global Routing (2:15pm)

Azadeh Davoodi, Hamid Shojaei, Parameswaran Ramanathan - Univ. of Wisconsin, Madison, WI

1:30 - 3:00pm

1:30 - 3:00pm

1:30 - 3:00pm

Room: 306

Room: 308

Room: 310






32

33

SPECIAL SESSION: BREAKING OUT OF EDA: HOW TO APPLY EDA TECHNIQUES TO BROADER APPLICATIONS

THE RIGHT PLACEMENT AT THE RIGHT TIMING

Chair Jason Cong - Univ. of California, Los Angeles, CA

Throughout its history, myriads of innovations in EDA (Electronic Design Automation) have enabled high performance semiconductor products with leading edge technology. Lately we have observed several research activities where EDA innovations have been applied to broader applications with complex nature and the large scale of data sets. The session provides some tangible results of these multi-disciplinary works where non-traditional EDA problems directly benefit from the innovation of EDA research. The examples of non-EDA applications vary from bio-medical applications to smart water to human computing.

Chair Saurabh Adya - Magma Design Automation, Inc., Sunnyvale, CA

Great chips need great placements; without this, little else matters. The papers in this session push the state of the art forward, leveraging stacked TSVs to improve cooling, and better numerical techniques for analytic placement. Underlying structure and regularity is deciphered, giving new ways to tame large designs. The session concludes with new benchmarks and metrics for placement, and the results of the 2012 DAC placement contest, where teams from around the world compete head-to-head for the title of Best Placer Ever.

33.1 Exploiting Die-to-Die Thermal Coupling in 3-D IC Placement (4:00pm)Krit Athikulwongse, Mohit Pathak, Sung Kyu Lim - Georgia Institute of Technology, Atlanta, GA

33.2 ComPLx: A Competitive Primal-Dual Lagrange Optimization for Global Placement (4:15pm)

Myung-Chul Kim, Igor L. Markov - Univ. of Michigan, Ann Arbor, MI

32.1 Design Tools for Artificial Nervous SystemsLou Scheffer - Howard Hughes Medical Institute, Chevy Chase, MD

32.2 Dynamic River Network Simulation at Large ScaleFrank Liu - IBM Research - Austin, TXBen R. Hodges - Univ. of Texas, Austin, TX

32.3 Humans for EDA and EDA for HumansValeria Bertacco - Univ. of Michigan, Ann Arbor, MI

32.4 Application of Logic Synthesis to the Understanding and Cure of Genetic Diseases

Sunil P. Khatri, Pey-Chang Kent Lin - Texas A&M Univ., College Station, TX

33.3 PADE: A High-Performance Placer with Automatic Datapath Extraction and Evaluation through High-Dimensional Data Learning (4:30pm)

Samuel Ward, Duo Ding, David Z. Pan - Univ. of Texas, Austin, TX33.4 Structure-Aware Placement for Datapath Intensive Circuit Designs (4:45pm)

Sheng Chou, Meng-Kai Hsu, Yao-Wen Chang - National Taiwan Univ., Taipei, Taiwan

33.5 GLARE: Global and Local Wiring Aware Routability Evaluation (5:00pm)Yaoguang Wei, Sachin S. Sapatnekar - Univ. of Minnesota, Minneapolis, MNCliff Sze, Zhuo Li, Charles J. Alpert - IBM Research - Austin, TXNatarajan Viswanathan, Lakshmi Reddy, Andrew D. Huber, Gustavo E. Tellez, Douglas Keller - IBM Systems and Technology Group, Hopewell Jct., NY

33.6 The DAC 2012 Routability-Driven Placement Contest and Benchmark Suite (5:15pm)

Natarajan Viswanathan, Charles J. Alpert, Cliff Sze, Zhuo Li, Yaoguang Wei - IBM Corp., Austin, TX

4:00 - 6:00pm

4:00 - 6:00pm

Room: 304

Room: 300

31 PANEL: HOT APPS, COOL PHONES: POWER-EFFICIENT MOBILE DESIGN

4:00 - 6:00pmChair

Ed Sperling - Low Power Engineering, San Jose, CASpeakers:

Jan Rabaey - Univ. of California, Berkeley, CAEmily Shriver - Intel Corp., Hillsboro, ORAlan Gibbons - Synopsys, Inc., Mountain View, CANarendra Konda - NVIDIA Corp., Santa Clara, CABarry Pangrle - Mentor Graphics Corp., Fremont, CADavid Greenhill - Texas Instruments, Inc., Dallas, TX

Recently, we have focused on techniques for low-power hardware design. But it is not enough. With the advent of app-driven mobile devices, battery life is paramount. We must now consider the impact of software on power consumption, and the EDA industry must look to providing environments that enable modeling, measuring and optimizing the impact of hardware and software interaction on power consumption at the system level. Our panelists explore the technical challenges and potential solutions for designing and verifying these complex power efficient systems.

Room: 305 Low-Power Design and Power Analysis

Bio Design Automation

Physical Design



34

35

GLOBAL VIEWS OF SYNTHESIS: BROADENING THE SCOPE

ADAPTIVE COMPUTING: WHEN, WHERE, WHY, HOW?

Chair Herman Schmit - Altera Corp., Santa Clara, CA

Researchers are starting to investigate exciting avenues linking traditional synthesis to the global design environment. We present a selection of papers exploring several new directions. Static logic analysis can be used to simultaneously achieve both portable and efficient module interfaces, while logic synthesis is redirected to support approximate computing, and a high-level analysis presents new insights into the scalability of multi-function designs. For the early stages of the design flow, we present a method for RTL-based NBTI aging prediction, while for later in the flow we offer a new approach to post-mapping optimization and a new form of timing ECO optimization.

34.1 Removing Overhead from High-Level Interfaces (4:00pm)Kyle Kelley, Megan Wachs, John P. Stevenson, Stephen Richardson, Mark Horowitz - Stanford Univ., Stanford, CA

34.2 On the Asymptotic Costs of Multiplexer-Based Reconfigurability (4:15pm)

Johnathan A. York, Derek Chiou - Univ. of Texas, Austin, TX

Chair Philip Brisk - Univ. of California, Riverside, CA

Embedded systems are increasingly expected to support a dynamic and diverse application landscape under tight power-performance constraints, thus mandating runtime adaptivity. The need for adaptivity is multifarious: seamless hiding of variation induced errors, trading accuracy versus energy through approximate arithmetic, trading power versus performance via hybrid on-chip network, offloading computation to a rich set of accelerators for higher efficiency, satisfying QoS through adaptive resource management. This session addresses adaptivity at different layers of an embedded computing system starting from the silicon all the way to the system-level.

35.1 Accuracy-Configurable Adder for Approximate Arithmetic Designs (4:00pm)

Seokhyeong Kang, Andrew B. Kahng - Univ. of California at San Diego, La Jolla, CA

35.2* Recovery-Based Design for Variation-Tolerant SoCs (4:15pm)Vivek J. Kozhikkottu, Anand Raghunathan - Purdue Univ., West Lafayette, INSujit Dey - Univ. of California at San Diego, La Jolla, CA

34.3 SALSA: Systematic Logic Synthesis of Approximate Circuits (4:30pm)Swagath Venkataramani, Amit Sabne, Vivek Kozhikkottu, Kaushik Roy, Anand Raghunathan - Purdue Univ., West Lafayette, IN

34.4 Timing ECO Optimization Using Metal-Configurable Gate-Array Spare Cells (4:45pm)

Iris Hui-Ru Jiang - National Chiao Tung Univ., Hsinchu, Taiwan,Hua-Yu Chang, Yao-Wen Chang - National Taiwan Univ., Taipei, Taiwan

34.5 Early Prediction of NBTI Effects Using RTL Source Code Analysis (5:00pm)

Jayanand Asok Kumar, Heesoo Kim, Shobha Vasudevan - Univ. of Illinois at Urbana-Champaign, Urbana, ILKenneth M. Butler - Texas Instruments, Inc., Dallas, TX

34.6 Generalized SAT-Sweeping for Post-Mapping Optimization (5:15pm)Tobias Welp - Univ. of California, Berkeley, CASmita Krishnaswamy - Columbia Univ., New York, NYAndreas Kuehlmann - Coverity, Inc., San Francisco, CA

35.3 A Hybrid NoC Design for Cache Coherence Optimization for Chip Multiprocessors (4:30pm)

Hui Zhao, Ohyoung Jang, Wei Ding, Mahmut Kandemir, Mary Jane Irwin - Pennsylvania State Univ., University Park, PAYuanrui Zhang - Pennsylvania State Univ., University Park, PA

35.4 Architecture Support for Accelerator-Rich CMPs (4:45pm)Mohammad Ali Ghodrat, Jason Cong, Michael Gill, Beayna Grigorian, Glenn Reinman - Univ. of California, Los Angeles, CA

35.5 A QoS-Aware Memory Controller for Dynamically Balancing GPU and CPU Bandwidth Use in an MPSoC (5:00pm)

Min Kyu Jeong, Mattan Erez - Univ. of Texas, Austin, TXChander Sudanthi, Nigel Paver - ARM, Inc., Austin, TX

35.6 Metronome: Operating System-Level Performance Management via Self-Adaptive Computing (5:15pm)

Filippo Sironi, Davide Basilio Bartolini, Fabio Cancaré, Donatella Sciuto, Marco D. Santambrogio - Politecnico di Milano, Milano, ItalySimone Campanoni - Harvard Univ., Cambridge, MAHenry Hoffmann - Massachusetts Institute of Technology, Cambridge, MA

4:00 - 6:00pm

4:00 - 6:00pm

Room: 306

Room: 308


Embedded Architecture & Platforms



36 YIN AND YANG OF MEMORIES: THE POWER-PERFORMANCE TRADE-OFF

4:00 - 6:00pmChair

Yiran Chen - Univ. of Pittsburgh, PAEmerging memory technologies, along with their conventional counterparts (SRAM and DRAM,) present a plethora of options to design future memory hierarchies. A critical question to address is how to pick the right technologies and where to place them in the storage hierarchy. Answering this question demands a thorough exploration of power-performance tradeoffs. The papers in this session address different aspects of this problem, and explore a variety of solutions ranging from DRAM/PRAM based heterogeneous memory design, to multi-level STTRAMs, to power/performance tradeoffs in video memories. The session not only highlights efforts on these fronts and reveals interesting power-performance tradeoffs, but also highlights possible future directions.

36.1 Adaptive Power Management of On-Chip Video Memory for Multiview Video Coding (4:00pm)

Muhammad Shafique, Bruno Zatt, Joerg Henkel - Karlsruhe Institute of Technology, Karlsruhe, GermanyFábio Leandro Walter, Sergio Bampi - Univ. Federal do Rio Grande do Sul, Porto Alegre, Brazil

36.2 Heterogeneous Multi-Channel: Fine-Grained DRAM Control for Both System Performance and Power Efficiency (4:15pm)

Guangfei Zhang, Xinke Chen, Peng Li - Institute of Computing Tech., Beijing, ChinaHuandong Wang - Loongson Technology Corp., Ltd., Beijing, ChinaShuai Huang - Loongson Technology Corp., Ltd., Beijing, China

36.3 Joint Management of RAM and Flash Memory with Access Pattern Considerations (4:30pm)

Po-Chun Huang - National Taiwan Univ., Taipei, TaiwanYuan-Hao Chang - Academia Sinica, Taipei, TaiwanTei-Wei Kuo - National Taiwan Univ., Academia Sinica, Taipei, Taiwan

36.4 Hybrid DRAM/PRAM-Based Main Memory for Single-Chip CPU/GPU (4:45pm)

Dongki Kim, Sungkwang Lee, Sungjoo Yoo, Sunggu Lee - Pohang Univ. of Science and Technology, Pohang, Republic of KoreaJaewoong Chung, Dong Hyuk Woo - Intel Corp., Santa Clara, CADaeHyun Kim - Magma Design Automation, Inc., San Jose, CA

36.5 Write Performance Improvement by Hiding R Drift Latency in Phase-Change RAM (5:00pm)

Youngsik Kim, Sungjoo Yoo, Sunggu Lee - Pohang Univ. of Science and Technology, Pohang, Republic of Korea

36.6 Constructing Large and Fast Multi-Level Cell STT-MRAM Based Cache for Embedded Processors (5:15pm)

Lei Jiang, Bo Zhao, Youtao Zhang, Jun Yang - Univ. of Pittsburgh, PA

Room: 310 Embedded Architecture & Platforms


TECHNICAL SESSIONSTHURSDAY, JUNE 7

39 SIMULATION-BASED VERIFICATION: NEW WAYS TO HARNESS THE WORKHORSE

Chair Kerstin Eder - Univ. of Bristol, United Kingdom

As the complexity of designs grows and time-to-market shrinks, new (and old) verification problems arise. Simulation-based verification continues to be the main workhorse for dealing with these problems. This session introduces novel applications of simulation-based and hybrid techniques to address many of these problems including: improving simulation accuracy by eliminating extraneous don’t cares in 3-valued simulation, applying SAT solvers to assist in bug localization, extracting functionality from simulation runs, and adding checking capabilities to emulation and acceleration platforms.

39.1 Improving Gate-Level Simulation Accuracy when Unknowns Exist (9:00am)

Kai-hui Chang, Chris Browy - Avery Design Systems, Inc., Andover, MA

39.2 Automated Feature Localization for Hardware Designs Using Coverage Metrics (9:15am)

Jan Malburg, Alexander Finder - Univ. of Bremen, GermanyGoerschwin Fey - German Aerospace Center, Bremen, Germany

39.3 Path Directed Abstraction and Refinement in SAT-Based Design Debugging (9:30am)

Brian Keng, Andreas Veneris - Univ. of Toronto, Toronto, ON, Canada39.4 Checking Architectural Outputs Instruction-by-Instruction on Acceleration Platforms (9:45am)

Debapriya Chatterjee, Valeria Bertacco - Univ. of Michigan, Ann Arbor, MIAnatoly Koyfman, Ronny Morad, Avi Ziv - IBM Haifa Research Lab., Haifa, Israel

9:00 - 10:30am Room: 300 Verification and Test

37 PANEL: IS 3-D READY FOR THE NEXT LEVEL?

38 SPECIAL SESSION: PROBABILISTIC EMBEDDED COMPUTING

Chair Sachin Sapatnekar - Univ. of Minnesota, Minneapolis, MN

Speakers: Subramanian S. Iyer - IBM Corp., Fishkill, NYShekhar Borkar - Intel Corp., Hillsboro, ORA.J. Incorvaia - Cadence Design Systems, Inc., Chelmsford, MALiam Madden - Xilinx, Inc., San Jose, CASuk Lee - Taiwan Semiconductor Manufacturing Co., Ltd., San Jose, CA

Chair Vincent Mooney - Georgia Institute of Technology, Atlanta, GA

Probabilistic Embedded Computing (PEC) provides dramatic, low-cost performance boosts at the expense of guaranteed correctness and may even help overcome fundamental barriers that can otherwise not be resolved. Giving up guaranteed correctness opens up a vast challenge and solution space on all levels of embedded computing. The session presents the state of the art in PEC-related work involving hardware, hardware-software interfaces, and software.

38.1 Incorrect Systems: It’s not the Problem, It’s the SolutionChristoph Kirsch, Hannes Payer - Univ. of Salzburg, Austria

Early promises of 3-D IC integration - memory bandwidth and power (wide-IO memory stacks in consumer products), or yield and cost (FPGA die integrated with a silicon interposer) - have now been realized in volume production. What have the design and supply chains learned from the experience of enabling these applications? What will be the next killer applications for 3-D, how will these be enabled across the semiconductor industry, and what key technologies must the EDA industry contribute? Come hear the experts discuss how to “take 3-D to the next level.”

38.2 On Software Design for Stochastic ProcessorsRakesh Kumar, Joseph Sloan, John Sartori - Univ. of Illinois at Urbana-Champaign, Urbana, IL

38.3 What to Do About the End of Moore’s Law, Probably! Krishna Palem - Nanyang Technological Univ., Rice Univ., SingaporeAvinash Lingamneni - Rice Univ., Houston, TX

38.4 Obtaining and Reasoning About Good Enough SoftwareMartin Rinard - Massachusetts Institute of Technology, Boston, MA

9:00 - 10:30am

9:00 - 10:30am

Room: 305

Room: 304

General Interest




40

41

ULTRA-LOW POWER USING SUBTHRESHOLD AND NEARTHRESHOLD OPERATION

TOP PICKS OF RUN-TIME POWER MANAGEMENT TECHNIQUES

Chair Mahadev Nemani - Intel Corp., Hillsboro, OR

Ultra-low power operation can be achieved by aggressively scaling the supply voltage to values near or below the threshold voltage, but there are interesting trade-offs that show up in this regime. Designers need to revisit methodologies like in the first two papers in this session (circuit sizing and decoupling cap placement), or have to deal with the increased impact of process variations, as in the last two papers in the session (completion detection and trade-offs for SIMD architectures).

40.1 Standard Cell Sizing for Subthreshold Operation (9:00am)Bo Liu, Jose Pineda de Gyvez - Technische Univ. Eindhoven, The NetherlandsMaryam Ashouei, Jos Huisken - Holst Centre, Eindhoven, The Netherlands

Chair(s): Jian-Jia Chen - Karlsruhe Institute of Technology, Karlsruhe, Germany

Run-time adaptivity is facing increasing interest in application-specific embedded systems. Run-time monitoring and management of system resources are necessary to meet system-level requirements. This session explores advanced strategies for power and temperature management at run-time in several application scenarios.

41.1 Run-Time Power-Down Strategies for Real-Time SDRAM Memory Controllers (9:00am)

Karthik Chandrasekar - Delft Univ. of Technology, Delft, The NetherlandsBenny Akesson, Kees Goossens - Technische Univ. Eindhoven, The Netherlands

40.2 Decoupling Capacitor Design Strategy for Minimizing Supply Noise of Ultra-Low Voltage Circuits (9:15am)

Mingoo Seok - Columbia Univ., New York, NY40.3 Regaining Throughput Using Completion Detection for Error-Resilient, Near-Threshold Logic (9:30am)

Joseph Crop, Robert Pawlowski, Patrick Y. Chiang - Oregon State Univ., Corvallis, OR

40.4 Process Variation in Near-Threshold Wide SIMD Architectures (9:45am)Sangwon Seo, Ronald Dreslinski, Mark Woh, Yongjun Park, Scott Mahlke, David Blaauw, Trevor Mudge - Univ. of Michigan, Ann Arbor, MIChaitali Chakrabarti - Arizona State Univ., Tempe, AZ

41.2 Embedding Statistical Tests for On-Chip Dynamic Voltage and Temperature Monitoring (9:15am)

Lionel Vincent, Suzanne Lesecq, Edith Beigne - CEA-LETI Minatec, Grenoble, FranceMaurine Philippe - Univ. Montpellier 2, France

41.3 Quality-Retaining OLED Dynamic Voltage Scaling for Video Streaming Applications on Mobile Devices (9:30am)

Xiang Chen, Jian Zeng, Yiran Chen - Univ. of Pittsburgh, PAMengying Zhao, Chun Jason Xue - City Univ. of Hong Kong, Kowloon, Hong Kong

41.4 Traffic-Aware Power Optimization for Network Applications on Multicore Servers (9:45am)

Jilong Kuang, Laxmi Bhuyan, Raymond Klefstad - Univ. of California, Riverside, CA

9:00 - 10:30am

9:00 - 10:30am

Room: 306

Room: 308



42 THE DARK SIDE OF TEST

9:00 - 10:30am

Chair Shreyas Sen - Intel Corp., Portland, OR

Here are some things you don’t know: how are we going to test TSVs and how good are your analog and DRAM tests? This session presents innovative methods for dealing with TSV defects in 3-D ICs, testing DRAM memory, and verifying analog tests.

42.1 Alternate Hammering Test for Application-Specific DRAMs and an Industrial Case Study (9:00am)

Rei-Fu Huang - MediaTek, Inc., Hsinchu, TaiwanHao-Yu Yang, Mango C.-T. Chao - National Chiao Tung Univ., Hsinchu, TaiwanShih-Chin Lin - United Microelectronics Corp., Hsinchu, Taiwan

42.2 Goal-Oriented Stimulus Generation for Analog Circuits (9:15am)Seyed Nematollah Ahmadyan, Jayanand Asok Kumar, Shobha Vasudevan - Univ. of Illinois at Urbana-Champaign, Urbana, IL

42.3 TSV Open Defects in 3-D Integrated Circuits: Characterization, Test, and Optimal Spare Allocation (9:30am)

Fangming Ye, Krishnendu Chakrabarty - Duke Univ., Durham, NC42.4 Small Delay Testing for TSVs in 3-D ICs (9:45am)

Shi-Yu Huang, Yu-Hsiang Lin - National Tsing Hua Univ., HsinChu, TaiwanKun-Han Tsai, Wu-Tung Cheng, Stephen Sunter - Mentor Graphics Corp., Kanata, ON, CanadaYung-Fa Chou, Ding-Ming Kwai - Industrial Technology Research Institute, Hsinchu, Taiwan

Room: 310 Verification and Test



45 SURVIVING TIMING CHALLENGES IN NANOMETER DESIGNS

Chair Florentin Dartu - Synopsys, Inc., Hillsboro, OR

Technology scaling and escalation of design complexity has made assurance of timing performance under various process and environmental conditions an increasing challenge. Advances in design-time timing analysis and verification and in run-time timing failure detection are vital avenues for developing current and future nanometer designs. This session highlights recent advancements in functional and static timing analysis where novel techniques are developed to account for statistical and deterministic sources of timing variations and their interactions in an efficient and incremental manner. The session also recognizes research geared towards leveraging microarchitectural-level simulation and gate-level logic analysis for prediction and tolerance of timing violations in high performance processors.

45.1 Functional Timing Analysis Made Fast and General (1:30pm)Yi-Ting Chung, Jie-Hong Roland Jiang - National Taiwan Univ., Taipei, Taiwan

45.2 Timing Analysis with Nonseparable Statistical and Deterministic Variations (1:45pm)

Vladimir Zolotov, Jinjun Xiong - IBM T.J. Watson Research Ctr., Yorktown Heights, NYDebjit Sinha, Chandu Visweswariah, Jeffrey G. Hemmett, Jeremy Leitzen, Natesan Venkateswaran - IBM Systems and Technology Group, Hopewell Junction, NYEric Foreman - IBM Corp., Essex Junction, VT

45.3 Reversible Statistical Max/Min Operation: Concept and Applications to Timing (2:00pm)

Vladimir Zolotov, Jinjun Xiong - IBM T.J. Watson Research Ctr., Yorktown Heights, NYDebjit Sinha, Chandu Visweswariah - IBM Systems and Technology Group, Hopewell Junction, NYNatesan Venkateswaran - IBM Systems and Technology Group, Hopewell Junction, NY

45.4 Predicting Timing Violations Through Instruction-Level Path Sensitization Analysis (2:15pm)

Sanghamitra Roy, Koushik Chakraborty - Utah State Univ., Logan, UT

1:30 - 3:00pm Room: 300 Circuit and Interconnect Analysis

43

44

PANEL: IT’S THE SOFTWARE, STUPID! TRUTH OR MYTH?

SPECIAL SESSION: DESIGN CHALLENGES AND EDA SOLUTIONS FOR WIRELESS SENSOR NETWORKS

Chair Chris Edwards - Tech Design Forum, London, United Kingdom

Speakers: Serge Leef - Mentor Graphics Corp., Wilsonville, ORChris Rowen - Tensilica, Inc., Santa Clara, CADebashis Bhattacharya - FutureWei Technologies, Inc., Plano, TXKathryn S. McKinley - Microsoft Research, Univ. of Texas, Austin, TXEli Savransky - NVIDIA Corp., Santa Clara, CA

Chair Roman Hermida - Complutense Univ., Madrid, Spain

The objective of this session is to present a complete overview of the state-of-the-art technologies and key research challenges for the design and optimization of wireless sensor networks (WSN). Thus, it will specifically cover ultra-low-power (ULP) computing architectures and circuits, system-level design methods, power management, and energy-scavenging mechanisms for WSN. A key aspect of this special session is the interdisciplinary nature of the discussed challenges in WSN conception, which go from basic hardware components to software conception, which requires an active engagement of both academic and industrial professionals in the EDA field, computer and electrical engineering, computer science, and telecommunication engineering.

44.1 Circuit and System Design Guidelines for Ultra-Low Power Processing Dennis Sylvester, Yoonmyung Lee, Yejoong Kim, Dongmin Yoon, David Blaauw - Univ. of Michigan, Ann Arbor, MI

1:30 - 3:00pm

1:30 - 3:00pm

Room: 305

Room: 304

Embedded Software


It’s tough to differentiate products with hardware. Everyone uses the same processors, third party IP and foundries; now it’s all about software. But, is this true? Since user response, power consumption and support of standards rely on hardware, one camp claims software is only as good as the hardware it sits on. Opponents argue that software differentiates mediocre products from great ones. A third view says only exceptional design of both hardware and software creates great products - and the tradeoffs make great designers. Watch industry experts debate whether it’s really all about software.

44.2 Design Exploration of Energy-Performance Trade-Offs for Wireless Sensor Networks

Vincenzo Rana, Ivan Beretta, David Atienza - Ecole Polytechnique Fédérale de Lausanne, SwitzerlandFrancisco Rincon - Univ. Complutense Madrid, Spain Nadia Khaled - Nestlé Research Center, Lausanne, SwitzerlandPaolo R. Grassi - Politecnico di Milano, Italy

44.3 Energy Harvesting and Power Management for Autonomous Sensor Nodes

Edith Beigné, Jean-Frederic Christmann, Cyril Condemine, Jerome Willemin - CEA-LETI, Grenoble, FranceChristian Piguet - Centre Suisse d’Electronique et Microtechnique SA, Neuchatel, Switzerland



48 SPECIAL SESSION: HETEROGENOUS PLATFORMS: CHALLENGES AND OPPORTUNITIES

1:30 - 3:00pmChair

Norbert Wehn - Univ. of Kaiserslautern, GermanyDesigning heterogeneous multicore architectures provides many challenges at the hardware and software levels. This session will present three different solutions to some of these problems, in which the aim of power-efficiency is one of the driving factors, while approaching different application areas.

48.1 Is Dark Silicon Useful? Harnessing the Four Horsemen of the Coming Dark Silicon Apocalypse

Michael B. Taylor - Univ. of California at San Diego, La Jolla, CA

48.2 Platform 2012 - A Many-Core Computing Accelerator for Embedded SoCs: Performance Evaluation of Visual Analytics Applications

Diego Melpignano, Eric Flamand, Bruno Jego, Thierry Lepley, Germain Haugou - STMicroelectronics, Grenoble, FranceLuca Benini - Univ. di Bologna, STMicrolectronics, Bologna, ItalyFabien Clermidy, Denis Dutoit - STMicroelectronics, CEA-LETI, Grenoble, France

48.3 Big.LITTLE System Architecture from ARM: Saving Power through Heterogeneous Multiprocessing and Task Context Migration

Brian Jeff - ARM, Ltd., Austin, TX

Room: 310 Embedded Architecture & Platforms

46

47

SPECIAL DELIVERY: CHALLENGES IN PACKAGING

RENOVATE ANALOG AND MIXED-SIGNAL CIRCUIT SIMULATIONS

Chair Tan Yan - Synopsys, Inc., Mountain View, CA

Delivering the next generation technologies requires addressing PCB design, 3-D methodology, and most importantly, packaging. The first three papers in this session explore the collaborative design between the chip, package and board, as well as IP re-use in 3-D ICs. These methodologies deliver the promise of footprint scaling at the packaging level. Pin access can however limit the scaling at the chip level. The last paper in the session overcomes that limitation.

46.1 A Chip-Package-Board Co-Design Methodology (1:30pm)Hsu-Chieh Lee, Yao-Wen Chang - National Taiwan Univ., Taipei, Taiwan

Chair Chenjie Gu - Intel Corp., Hillsboro, OR

This session presents several advanced analysis methodologies for analog and mixed-signal circuits. The first topic is fast Monte Carlo analysis for parametric yield estimation. Two papers in this area aim to accurately estimate the failure rate with a minimum number of transistor-level simulation runs. The second topic is fast circuit simulation. This goal is pursued through two different avenues: novel pre-conditioning for iterative solvers and parallel simulation based on GPUs.

47.1 Yield Estimation via Multi-Cones (1:30pm)Rouwaida Kanj - American Univ. of Beirut, New York, NYRajiv Joshi - IBM T.J. Watson Research Ctr., Yorktown Heights, NYZhuo Li, Sani Nassif - IBM Research - Austin, TXJerry Hayes - IBM Research - Austin, TX

46.2 Obstacle-Avoiding Free-Assignment Routing for Flip-Chip Designs (1:45pm)

Po-Wei Lee, Hsu-Chieh Lee, Yao-Wen Chang, Yuan-Kai Ho - National Taiwan Univ., Taipei, TaiwanChen-Feng Chang, I-Jye Lin, Chin-Fang Shen - Synopsys, Inc., Taipei, Taiwan

46.3 Clock Tree Synthesis with Methodology of Re-Use in 3-D IC (2:00pm)Fu-Wei Chen, TingTing Hwang - National Tsing Hua Univ., Hsinchu, Taiwan

46.4 Can Pin Access Limit the Footprint Scaling? (2:15pm)Xiang Qiu, Malgorzata Marek-Sadowska - Univ. of California, Santa Barbara, CA

47.2 Efficient Trimmed-Sample Monte Carlo Methodology and Yield-Aware Design Flow for Analog Circuits (1:45pm)

Chin-Cheng Kuo, Yi-Hung Chen, Jui-Feng Kuan, Yi-Kan Cheng - Taiwan Semiconductor Manufacturing Co., Ltd., HsinChu, TaiwanWei-Yi Hu - Taiwan Semiconductor Manufacturing Co., Ltd., National Taiwan Univ., Hsinchu, Taiwan

47.3 Towards Efficient SPICE-Accurate Nonlinear Circuit Simulation with On-the-Fly Support-Circuit Preconditioners (2:00pm)

Xueqian Zhao, Zhuo Feng - Michigan Technological Univ., Houghton, MI47.4 Sparse LU Factorization for Parallel Circuit Simulation on GPU (2:15pm)

Ling Ren, Xiaoming Chen, Yu Wang, Chenxi Zhang, Huazhong Yang - Tsinghua Univ., Beijing, China

1:30 - 3:00pm

1:30 - 3:00pm

Room: 306

Room: 308

Physical Design


28



51 YIELDING IN AN UNCERTAIN WORLD

Chair Rob Aitken - ARM, Inc., San Jose, CA

As Moore’s Law marches into the sub-22nm regime, designers are surrounded by many uncertainties, such as lithography choices, new device architectures, and 3-D integration. These challenges have to be addressed by collective design and process integration techniques at multiple abstraction levels. EDA can play a pivotal role in bridging these disciplines. To improve yield in the uncertain world, this session covers new advancements in pattern recognition, triple patterning, EUV, novel memory, and 3-D architecture.

51.1 Accurate Process-Hotspot Detection Using Critical Design Rule Extraction (3:30pm)

Yen-Ting Yu, Iris Hui-Ru Jiang - National Chiao Tung Univ., Hsinchu, TaiwanYa-Chung Chan - Mstar Semiconductor, Chupei, TaiwanSubarna Sinha - Stanford Univ., Stanford, CACharles Chiang - Synopsys, Inc., Mountain View, CA

51.2 Improved Tangent Space-Based Distance Metric for Accurate Lithographic Hotspot Classification (3:45pm)

Jing Guo, Fan Yang, Xuan Zeng - Fudan Univ., Shanghai, ChinaSubarna Sinha - Stanford Univ., Stanford, CACharles Chiang - Synopsys, Inc., Mountain View, CA

51.3 Simultaneous Flare Level and Flare Variation Minimization with Dummification in EUVL (4:00pm)

Shao-Yun Fang, Yao-Wen Chang - National Taiwan Univ., Taipei, Taiwan51.4 A Novel Layout Decomposition Algorithm for Triple Patterning Lithography (4:15pm)

Shao-Yun Fang, Yao-Wen Chang, Wei-Yu Chen - National Taiwan Univ., Taipei, Taiwan

51.5 PS3-RAM: A Fast, Portable, and Scalable Statistical STT-RAM Reliability Analysis Method (4:30pm)

Wujie Wen, YaoJun Zhang, Yiran Chen - Univ. of Pittsburgh, PAYu Wang - Tsinghua Univ., Beijing, ChinaYuan Xie - Pennsylvania State Univ., University Park, PA

51.6 Exploiting Narrow-Width Values for Process Variation-Tolerant 3-D Microprocessors (4:45pm)

Joonho Kong, Sung Woo Chung - Korea Univ., Seoul, Republic of Korea

3:30 - 5:30pm Room: 300 Design for Manufacturability

49

50

PANEL: PARALLELIZATION AND SOFTWARE DEVELOPMENT: HOPE, HYPE, OR HORROR?

SPECIAL SESSION: HOT CHIPS RUNNING COOL - ENERGY EFFICIENT NEAR-THRESHOLD COMPUTING AND ITS BARRIERS

Chair Igor Markov - Univ. of Michigan, Ann Arbor, MI

Speakers: Anirudh Devgan - Magma Design Automation, Inc., Austin, TXKunle Olukotun - Stanford Univ., Stanford, CADaniel Beece - IBM Research, Yorktown Heights, NYJoao Geada - CLK Design Automation, Inc., Littleton, MAAlan J. Hu - Univ. of British Columbia, Vancouver, BC, Canada

With the fear that the death of scaling is imminent, hope is widespread that parallelism will save us. Many EDA applications are described as “embarrassingly parallel,” and parallel approaches have certainly been effectively applied in many

Chair David Brooks - Harvard Univ., Cambridge, MA

Transistor threshold voltages have stagnated in recent technologies, deviating from constant-voltage scaling theory and limiting voltage scalability. Consequently, power and energy no longer improve as expected and the semiconductor industry now faces a power wall. To overcome this barrier, energy-efficiency must radically improve by lowering supply voltage and operating “near threshold,” where appreciable energy gains are achieved with modest performance losses. Near-threshold computing (NTC) poses new circuit and architectural challenges, including performance loss and increased variability. This special session quantifies NTC benefits and limitations, offers opinions on its suitability to commercial ICs, and suggests techniques to overcome associated challenges.

50.1 Assessing the Performance Limits of Parallelized Near-Threshold Computing

David Blaauw, Nathaniel Pinckney, Kory Sewell, Ronald G. Dreslinski, David Fick, Dennis Sylvester, Trevor Mudge - Univ. of Michigan, Ann Arbor, MI

3:30 - 5:30pm

3:30 - 5:30pm

Room: 305

Room: 304

General Interest


areas. Before the panel begins, come hear perspective on software development and the challenges associated with writing good software that are only exacerbated by the growing need to write robust, testable, and efficient parallel applications. Then watch the panelists debate future productive directions and dead ends to developing and deploying parallel algorithms. Find out if claims to super speedups are exaggerated and if the investment in parallel algorithms is worth the high development cost.

49.1 PhD or MD - Who is Better Trained for Building Successful Software Development Tools? (3:30pm)

Andreas Kuehlmann - Coverity, Inc., San Francisco, CA

50.2 Near-Threshold Voltage (NTV) Design - Opportunities and Challenges Shekhar Borkar, Himanshu Kaul, Mark Anders, Steven Hsu, Amit Agarwal, Ram Krishnamurthy - Intel Corp., Hillsboro, OR

50.3 Near-Threshold Operation for Power Efficient Computing? It Depends... Leland Chang, Wilfried Haensch - IBM T.J. Watson Research Ctr., Yorktown Heights, NY

50.4 Not so Fast my Friend: Is Near-Threshold Computing the Answer for Power Reduction of Wireless Devices?

Matt Severson - Qualcomm, Inc., Austin, TXKendrick Yuen, Yang Du - Qualcomm, Inc., San Diego, CA



54 OPTIMIZING EMBEDDED SOFTWARE FOR HIGH PERFORMANCE AND RELIABILITY

Chair Rodric Rabbah - IBM Research, Hawthorne, NY

The need to consider multiple objectives is a characteristics of embedded systems. Average performance, precise timing, energy consumption, thermal behavior, and reliability are among objectives to consider. The multitude of objectives is a key challenge in embedded system design. The papers in this session push forward the state of the art in performance- and reliability-aware embedded software design, with an emphasis on code generation.

54.1 Communication-Aware Mapping of KPN Applications onto Heterogeneous MPSoCs (3:30pm)

Jeronimo Castrillon, Andreas Tretter, Rainer Leupers, Gerd Ascheid - RWTH Aachen Univ., Aachen, Germany

54.2 Unrolling and Retiming of Stream Applications onto Embedded Multicore Processors (3:45pm)

Weijia Che, Karam S. Chatha - Arizona State Univ., Tempe, AZ

3:30 - 5:30pm Room: 310

53 WILD AND CRAZY IDEAS

3:30 - 5:30pmChair

Farinaz Koushanfar - Rice Univ., Houston, TXIt cannot get any crazier! Your friends on Facebook verify your designs. Your sister is eavesdropping on your specification. Do not take “no” for implication. Build satisfying circuits with noise. Let spin-based synapses make your head spin. Use parasitics to build 3-D brains.

53.1 CrowdMine: Towards Crowdsourced Human-Assisted Verification (3:30pm)

Wenchao Li, Sanjit A. Seshia - Univ. of California, Berkeley, CASomesh Jha - Univ. of Wisconsin, Madison, WI

53.2 Extracting Design Information from Natural Language Specifications (3:45pm)

Ian G. Harris - Univ. of California, Irvine, CA

53.3 Material Implication in CMOS: A New Kind of Logic (4:00pm)Elkim Roa, Wu-Hsin Chen, Byunghoo Jung - Purdue Univ., West Lafayette, IN

53.4 Boolean Satisfiability Using Noise-Based Logic (4:15pm)Sunil Khatri, Pey-Chang Kent Lin, Ayan Mandal - Texas A&M Univ., College Station, TX

53.5 Cognitive Computing with Spin-Based Neural Networks (4:30pm)Charles Augustine - Intel Corp., Hillsboro, OR Mrigank Sharad, Georgios Panagopoulos, Kaushik Roy - Purdue Univ., West Lafayette, IN

53.6 Capacitance of TSVs in 3-D Stacked Chips a Problem? Not for Neuromorphic Systems! (4:45pm)

Rodolphe Héliot, Antoine Joubert, Bilel Belhadj - CEA-LETI Minatec, Grenoble, FranceMarc Duranton - CEA-LIST, Gif-sur-Yvette Cedex, FranceOlivier Temam - INRIA, Saclay, France

Room: 308 WACI

Embedded Software54.3 Exploiting Spatiotemporal and Device Contexts for Energy-Efficient Mobile Embedded Systems (4:00pm)

Brad K. Donohoo, Chris Ohlsen, Sudeep Pasricha, Charles W. Anderson - Colorado State Univ., Fort Collins, CO

54.4 EPIMap: Using Epimorphism to Map Applications on CGRAs (4:15pm)Mahdi Hamzeh, Aviral Shrivastava, Sarma Vrudhula - Arizona State Univ., Tempe, AZ

54.5 Instruction Scheduling for Reliability-Aware Compilation (4:30pm)Semeen Rehman, Muhammad Shafique, Joerg Henkel - Karlsruhe Institute of Technology, Karlsruhe, Germany

54.6 Compiling for Energy Efficiency on Timing Speculative Processors (4:45pm)

John Sartori, Rakesh Kumar - Univ. of Illinois at Urbana-Champaign, Urbana, IL

52 HIGH-LEVEL SYNTHESIS IS NOT JUST ABOUT TRANSLATION!

Chair Satnam Singh - Google, Inc., Mountain View, CA

High-level synthesis aims to improve the end result of hardware generation by allowing exploration of architecture and algorithm, rather than logic structure and connectivity. HLS is not just about translation: the interesting problems aim to convert designer intent into efficient and correct hardware realization. The papers in this session cover issues related to languages to express and generate hardware, synthesis of software constructs such as recursion, hardware check-pointing for resiliency, optimizing memory access, synthesizing layout-friendly hardware, and design-space exploration of sorting networks.

52.1 Hardware Synthesis of Recursive Functions through Partial Stream Rewriting (3:30pm)

Lars Middendorf, Christian Haubelt - Univ. of Rostock, Rostock-Warnemuende, GermanyChristophe Bobda - Univ. of Arkansas, Fayetteville, AR

52.2 Chisel: Constructing Hardware in a Scala Embedded Language (3:45pm)

Jonathan Bachrach, Huy Vo, Brian Richards, Yunsup Lee, Andrew Waterman, Rimas Avizienis, John Wawrzynek, Krste Asanovic - Univ. of California, Berkeley, CA

52.3 Specification and Synthesis of Hardware Checkpointing and Rollback Mechanisms (4:00pm)

Carven Chan, Daniel Schwartz-Narbonne, Divjyot Sethi, Sharad Malik - Princeton Univ., Princeton, NJ

52.4 Optimizing Memory Hierarchy Allocation with Loop Transformations for High-Level Synthesis (4:15pm)

Peng Zhang, Jason Cong, Yi Zou - Univ. of California, Los Angeles, CA52.5 A Metric for Layout-Friendly Microarchitecture Optimization in High-Level Synthesis (4:30pm)

Bin Liu, Jason Cong - Univ. of California, Los Angeles, CA52.6 Computer Generation of Streaming Sorting Networks (4:45pm)

Marcela Zuluaga, Markus Püschel - Eidgenössische Technische Hochschule, Zürich,SwitzerlandPeter Milder - Carnegie Mellon Univ., Pittsburgh, PA

3:30 - 5:30pm Room: 306 High-Level and Logic Synthesis

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TUESDAY, JUNE 5SOFTWARE AND FIRMWARE ENGINEERING FOR COMPLEX SOCS

10:00 - 11:30amChair:

Pat Brouillette - Roku, Inc., Scottsdale, AZEarly software development is crucial for today’s complex SoCs, where the overall software effort typically eclipses the hardware effort. Further, delays in software directly impact the time to market of the end product. The presentations in this session explore how to architect ASIPs for wireless applications, how to bridge RTL and firmware development, and approaches in pre-silicon software development.

1.1 Finding the Right mix of Parallelism in a Coarse-Grained Array Baseband Processor (10:00am)

Tom Vander Aa, Praveen Raghavan, Raf Appeltans, Martin Palkovic, Min Li, Antoine Dejonghe, Liesbet Van der Perre - IMEC, Leuven, Belgium

1.2 Two for the Price of One - An Affordable Solution That Bridges the gap Between Firmware and RTL Implementations (10:15am)

Alicia Strang, Robert C. Carden IV, Pei Suen - Marvell Semiconductor, Inc., Aliso Viejo, CA

1.3 Enabling SoC Products with Pre-Si SW Development (10:30am)Ken Knowlson - Intel Corp., Hillsboro, OR

User Track - Embedded Systems and SoftwareRoom: 106 - Exhibit Floor

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USER TRACK POSTER SESSION

Front-End Silicon Design Topics / Back-End Silicon Design Topics

2.1 An RTL Developers Guide to the HLS GalaxyStefen Boyd - TLM Systems, Morgan Hill, CASergio Ramirez - Cadence Design Systems, Inc., Austin, TX

2.2 Maximizing the Reuse of UVM Components by Leveraging UVM Configuration DB Mechanism

Manikandan S, Sunil Kumar, Ashish Kumar - LSI Corp., Bangalore, India2.3 Practical Application of Model Checking – A Taxonomy of Methodologies

Michael G. Bartley, Anthony McIsaac - Test and Verification Solutions, United KingdomLaurent Arditi, Bryan Dickman, Daryl Stewart - ARM, Inc., Cambridge, United KingdomLawrence Loh - Jasper Design Automation, Inc., Mountain View, CA

2.4 A Subsystem Design Methodology Using High Level SynthesisGagan Midha - STMicroelectronics, Greater Noida, IndiaNitin Chawla, Bryan Bowyer - Calypto Design Systems, Inc., Wilsonville, OR

2.5 Logic Power Reduction in Data Path Oriented Designs by Re-Structuring Standard Cells

Vinay S. Adavani - Infinera Corp., Bangalore, India2.6 SoC Power Budgeting and Optimization Using RTL-Spreadsheet Power Estimation of ASICs

Udupi Harisharan, Jaga Shanmugavadivelu - Cisco Systems, Inc., San jose, CANarayana Koduri - Atrenta, Inc., San jose, CA

2.7 Billion Gate Semiconductor Design and Simulation and the Next Phase of the Cloud Computing Evolution

James Colgan - Xuropa, Inc., San Francisco, CANaresh K. Sehgal, Mrittika Ganguli - Intel Corp., Bangalore, India

2.8 Effortless, Quick and Accurate Data Entry of IPXACT Based SoC Connectivity Information Using Exce-Based VBA Macros

Saurin Patel, Silvia Costantini, Sparsh Arun - STMicroelectronics, Greater Noida, India

2.9 Development of a Unified Platform for Accelerated SoC Verification and Validation

Maruthy Vedam, Suman Kasam - Qualcomm, Inc., San Diego, CAHemant K. Sharma, Anoop Saha, Hans van der Schoot - Mentor Graphics Corp., Ottawa, ON, Canada

2.10 UVM Based Configurable Testbench for Verifying a Configurable IPPusuluri V. Giri Kumar, Pramodh M. Kumar - Synopsys, Inc., Bangalore, India

2.11 An Efficient Design Approach of Control Logic with the Use of High Level Synthesis for a Video Signal Conversion FPGA

Ryo Yamamoto - Mitsubishi Electric Corp., Kamakura, Japan

2.12 RTL Restructuring with Atrenta GenSysCyril Vartanian, Olivier Florent - STMicroelectronics, Grenoble, France

2.13 Framework and Automation for Effective Adoption of a Third Party Verification IP

Abhisek Verma, Amit Sharma, Varun S - Synopsys, Inc., Bangalore, IndiaBhavik Vyas - Reliance Consulting, Sunnyvale, CA

2.14 Extending UVM Methodology for Verifying Mixed-Signal Components Abhisek Verma, Fabian Delguste, Adiel Khan - Synopsys, Inc., Mountain View, CA

2.15 Exploring AES Design Variants with C-to-Gates for FPGA at Gb/s Line Rates

Kees Vissers, Fernando Martinez Vallina, Stephen Neuendorffer - Xilinx, Inc., San Jose, CAKristof Denolf, Ronny Dewaele - Barco, Kortrijk, Belgium

2.16 Real Value Modeling Enables Metric Driven Verification of Mixed Signal Design

Kishore Karnane, Walter Hartong - Cadence Design Systems, Inc., Feldkirchen, GermanyThomas Fuchs, Ronald Nerlich - Texas Instruments, Inc., Freising, Germany

2.17 Verification of Massive Advanced Node SoCsDaeseo Cha - Samsung, Youngin, Republic of KoreaAdam Sherer - Cadence Design Systems, Inc., Chelmsford, MA

2.18 Challenges and Recommendations for Modeling Complex Verification IP

Imran Ali, Anuradha I. Tambad, Subashini Rajan, Shivani Upasani, Prashanth Srinivasa - LSI Corp., Bangalore, India

2.19 Electrostatic Discharge Analysis on a Fullchip SoC DesignNitin S. Navale, Warren Anderson - Advanced Micro Devices, Inc., Boxborough, MA

2.20 Advanced ESD Tool Flow, Testing, and Design Verification ResultsMujahid Muhammad, Nicholas Palmer, Souvick Mitra, James Montstream, Robert Gauthier - IBM Systems and Technology Group, Essex Junction, VT

2.21 Using Fast, High-Capacity, Attofarad-Accurate 3-D Extraction for Successful Design of High-Performance IPs in Advanced CMOS Nodes

Atul Bhargava, Chittoor Parthasarthy, Srisurya Konduri - STMicroelectronics, Greater Noida, IndiaKiran Joseph, Claudia Relyea - Mentor Graphics Corp., Wilsonville, OR

2.22 CirCAD: Technique of Intelligent Custom DesignSanjeev KR, Sumit Goswami - Intel Corp., Bangalore, India

2.23 Practical Optimization Method for Multi-Corner Multi-Mode Timing Closure in 32 nm

Xiaoyue Wang - STMicroelectronics, Ottawa, ON, Canada

12:30 - 1:30pm User TrackRoom: 105 - Exhibit Floor

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TUESDAY, JUNE 5

31

POWER ANALYSIS AND OPTIMIZATION

Chair: Laurent Chaouat - Samsung, Austin, TX

Power is now one of the most critical aspects of system design. Presentations in this session include a framework for design decision making and its application to power analysis, a power-aware verification framework, approaches to make gate-level power analysis easier, and a design and verification suite for clock gating.3.1 DesignDB - A Framework for Design Decision Making and its Application to Power Analysis (1:30pm)

Mosur K. Mohan, Eric Donkoh - Intel Corp., Hillsboro, OR

3.2 Proven Techniques for a Seamless Power-Aware Verification Framework (1:45pm)

Anees Sutarwala, Osama Neiroukh - Intel Corp., Haifa, Israel3.3 Taking the Pain out of Gate-Level Power Analysis (2:00pm)

Krishnan Sundaresan, Ke Zhong, Wei-Lun Hung, Jaewon Oh, Mohd Jamil Mohd, Rob Mains - Oracle, Santa Clara, CA

3.4 Clock Gating Design and Verification Suite (2:15pm)Masanori Kurimoto, Naoshi Ishikawa, Koichi Ishimi, Masaya Kitao, Teruyuki Ito, Satoshi Kaneko, Hiroyuki Kondo - Renesas Electronics Corp., Itami, Japan

1:30 - 3:00pm User Track - Front EndRoom: 106 - Exhibit Floor3

2.24 eClock: Easy Clock Generation via All-Digital Phase-Locked Loop Compiler

Shi-Yu Huang, Chao-Wen Tzeng - National Tsing Hua Univ., Hsinchu, TaiwanPei-Ying Chao, Ruo-Ting Ding - TinnoTek Inc., Hsinchu, TaiwanDing-Ming Kwai - Industrial Technology Research Institute, Hsinchu, TaiwanNian-Shyang Chang, Chien-Lin Huang - National Chip Implementation Center, Hsinchu, Taiwan

2.25 LDE (Layout Dependent Effects) Aware Design Solution in Advanced Technologies

M.J. Huang, Sharon Jiang, Steven Chen - Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TaiwanCliff Hung, Captain Liu - SpringSoft, Inc., Hsin-chu, Taiwan

2.26 Coupling-Aware Statistical Timing AnalysisHenry Chan, Nathan Buck, Brian Dreibelbis, John Dubuque, Eric Foreman, Peter A. Habitz, David J. Hathaway, Gregory M. Schaeffer - IBM Corp., Hopewell Junction, NYChandu Visweswariah - IBM Systems and Technology Group, Hopewell Junction, NY

2.27 3-D Transient Field Simulator for Chip-Level Analysis of Electro-Thermal Coupling

Dundar Dumlugol, Wim Schoenmaker, Peter Meuris, Olivier Dupuis - Magwel NV, Leuven, BelgiumAarnout Wieers, Joseph Rhayem, Yves Depret - ON Semiconductor, Oudenaarde, Belgium

2.28 Adoption of Static Timing Analysis with Advanced On-Chip Variation at 28nm

Steven C. Chan, Adrian Au Yeung, Tze Haw Liew, Karsten Matt - GLOBALFOUNDRIES, Milpitas, CANing Jin - Univ. of California, Los Angeles, CA

2.29 A Novel Power-Grid Early Analysis Capability and Flow for Ensuring Efficient, Robust, and Reliable Power-Grid Designs

Efrat Rachevsky - Marvell Semiconductor, Inc., Adanim, Israel2.30 Symbolic SRAM Layout Analysis for Design and Technology Exploration

Paul Zuber, Miguel Miranda, Petr Dobrovolny, Peter De Bisschop, Mustafa Badaroglu, Diederik Verkest - IMEC, Leuven, Belgium

2.31 Variation-Aware Design Techniques for the Advanced 28nm NodeSuresh Raman, Shashank Bhonge - Xilinx, Inc., Hyderabad, India

2.32 Prevention of Data Loss in Physical Implementation of FIFOs and Data Path Synchronizers

Ramesh Rajagopalan, Ajay Bhandari - Cisco Systems, Inc., San Jose, CANamit Gupta - Atrenta, Inc., San Jose, CA

2.33 Single Pass Stitched Metal Filling Technique for Multi-Power Domain SoCs

Dibyendu Goswami, Swami Gangadharan - Intel Corp., Bangalore, India2.34 Incremental Fill: Metal Fill Legalization for ECO Layout Convergence

Dibyendu Goswami, Suryanarayana Prekke, Rajesh Karturi - Intel Corp., Bangalore, India

2.35 Case Study on Diagnosing Intermittent Scan Chain Hold-Time DefectsWu-Tung Cheng, Yu Huang, Dragon Hsu - Mentor Graphics Corp., HsinChu, TaiwanAugusli Kifli, Yu-Wei Chen - Faraday Technology Corp., Hsinchu City, Taiwan

2.36 Clock Tree Synthesis Careabouts for Complex SoCsRivu Das, Vishweshwara R, Venkatraman Ramakrishnan, Santhosh Thiyagaraja, Mahita Nagabhiru - Texas Instruments, Inc., Bangalore, India

2.37 Modeling of Near-Device Parasitics in MOSFETs and BJTs Using 3-D Fieldsolver

Prasanna Bekal, Weiping Shi - Texas A&M Univ., College Station, TX

CIRCUIT ANALYSIS AND OPTIMIZATION

4:00 - 6:00pmChair:

Nagaraj NS - Texas Instruments, Inc., Dallas, TXVariability and other circuit effects constitute a significant challenge and optimization opportunity in deep submicron design. This session features circuit analysis and optimization for various electrical effects. These complex techniques extend the capabilities of existing design methods. Presentations discuss the effect of stress on variability, improving accuracy in extraction, early fast and efficient analysis for IR drop and dynamic voltage drop, and hierarchical robustness analysis.

4.1 40nm and 28nm Variability-Aware Digital Designs (4:00pm)Philippe Hurat, Chris Pitchford - Cadence Design Systems, Inc., Bracknell, United KingdomAndrew Appleby - Cambridge Silicon Radio, Cambridge, United KingdomMark Zwolinski, Yangang Wang - Univ. of Southampton, Southampton, United KingdomMark Scoones, Sonia Caldwell, Touqeer Azam - CSR, Cambridge, United Kingdom

4.2 Accuracy Analysis of Parasitic Extraction for Advanced Nodes (28nm) (4:15pm)

Hendrik T. Mau - GLOBALFOUNDRIES, Dresden, Germany4.3 HVCOM Model for Graphics IP IR Drop Analysis (4:30pm)

Anand Ananthanarayanan, Basavaraj Kanthi, Srikrishnan Venkataraman, Nitin Jain - Intel Corp., Folsom, CA

4.4 Rapid IR Hotspot Diffusion Using In-Design Power Grid Analysis (4:45pm)

Sumit Goswami, Mysore Sriram, Srikrishnan Venkataraman - Intel Corp., Bangalore, India

4.5 Hierarchical Thermal and Electromigration Analysis for Cell-Based Designs (5:00pm)

Srini Krishnamoorthy, Vishak Venkatraman, Thomas Burd, James Pistole, Yuri Apanovich, Rajit Chandra - Advanced Micro Devices, Inc., Sunnyvale, CA

4.6 A Novel Method for Effective Early Dynamic Voltage Drop Analysis (5:15pm)

Khusro Sajid, Sorin A. Dobre, Mamta Bansal, Karim Arabi - Qualcomm, Inc., San Diego, CA

User Track - Back EndRoom: 106 - Exhibit Floor

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WEDNESDAY, JUNE 6

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PACKAGING AND AUTOMATIC PLACE AND ROUTE MINI SESSIONS

USER TRACK POSTER SESSION

Chair: Thomas Brandtner - Infineon Technologies, Villach, Austria

With the increase in integration and smaller form factor products, package design is a hot topic. The first two presentations discuss embedded packaging and package level power models. Physical design optimization constitutes a significant part of the design process, particularly in the face of increasing rule complexity in advanced semiconductor processes. The final two presentations discuss place and route methods for hierarchical mixed-signal design and for structured designs.

5.1 Embedding Bare Die and Discrete Passives in an Organic Substrate Package Design, Assembly, and Fabrication (9:00am)

Charles Pfeil - Mentor Graphics Corp., Longmont, CO

Embedded Systems and Software, Front-End, and Back-End Silicon Design Topics

6.1 FPGA-Based ASIC PrototypingZied Marrakchi, Ramsis Farhat - FLEXRAS Technologies Sas., Saint-Denis, FranceRamine Roane - Xilinx, Inc., San Jose, CA

6.2 A Next Generation IP and SoC Development PlatformFergus Slorach, Simon M. Butler - Methodics, Inc., San Francisco, CABertrand Blanc - Altera Corp., San Jose, CA

6.3 Nexus 5001 - Instrumentation Architectures and the New SpecificationNeal Stollon - HDL Dynamics, Dallas, TX

6.4 Deployment of Virtual Technology for Cave Creek Network ConnectionQun Wan, Alan Carew - Intel Corp., Shannon, Ireland

6.5 Reusable XML-Based Methodology and Tool Chain for Concept Development and Product Verification

Bas Arts - NXP Semiconductors, Eindhoven, The Netherlands6.6 Cloud-Based Parallel Design Space Exploration Using EDAxtend

Harnhua Ng - Plunify, Inc., Sunnyvale, CACristopher Magalang - Plunify Pte., Ltd., Singapore

6.7 Making Verification Environment Performance Efficient - Case Studies and Guidelines

Sarath C. Valapala, Prashanth Srinivasa - LSI Corp., Bangalore, India6.8 Register Verification on a Fast Lane: Using Automation to Converge on UVM REG Coverage Models

Abhisek Verma, Varun S, Amit Sharma - Synopsys, Inc., Bangalore, India6.9 Automated Monitoring and Checking of Real-Valued Behavior in Mixed-Signal Designs Using UVM

Alexander W. Rath, Volkan Esen, Wolfgang Ecker - Infineon Technologies AG, Neubiberg, Germany

6.10 Using Higher-Level VHDL Style in High-End Processor DesignAriel J. Birnbaum, Ilia Averbouch, Gil Shurek, Ilan Beer - IBM Haifa Research Lab., Haifa, Israel

6.11 A Unified Design and Simulation Environment Using SpreadsheetYoung-Il Kim, Wooseung Yang, Ju Hwan Yi, Hoon Choi - Silicon Image, Inc., Sunnyvale, CA

6.12 Functional and Performance Verification of a Rate-Controlled QoS-Based Arbiter Using Formal Methods

Yirng-An Chen, Saeed Shamshiri, Michael Hsieh - Marvell Semiconductor, Inc., Santa Clara, CA

5.2 Package Modeling and Verification for On-Chip Power Integrity Analysis (9:15am)

Hang Li, Eileen You, Harpreet Gill - Samsung, San Jose, CA5.3 Hierarchical APR Approach for Mixed Signal Designs (9:30am)

Atul Walimbe,Sumit Goswami, Victoria Kolesov, Raj Varada - Intel Corp., Santa Clara, CA

5.4 Structured APR: A Hybrid Approach for Efficient Custom Design (9:45am)

Sumit Goswami, Atul Walimbe, Victoria Kolesov, Raj Varada - Intel Corp., Santa Clara, CA

6.13 Challenges in Verifying USB3.0 Host and Device ControllerAbbas Khalili, Ryan Rhodes, Adrian Yu - Broadcom Corp., Richmond, BC, Canada

6.14 Utilizing Acceleration Platforms Using Off-Platform Generated Test-Cases

Dmitry Krestyashyn, Wisam Kadry, Shimon Landa, Vitali Sokhin - IBM Haifa Research Lab., Haifa, IsraelAmir Nahir - IBM Corp., Haifa, Israel

6.15 Are You Managing Your Registers Data or Barely Striving to Manage...(Or: Executable Specification of Registers Data)

Arik Shmayovitsh - Sigma Designs, Inc., Tel Aviv, IsraelDoron Meiraz - Synopsys, Inc., Herzelia, Israel

6.16 Architectural Coverage for Post-Silicon ExercisersNirmal M. Kumar, Varun Mallikarjunan, Subrat K. Panda - IBM Systems and Technology Group, Bangalore, IndiaAmir Nahir - IBM Corp., Haifa, IsraelVitali Sokhin, Avi Ziv - IBM Haifa Research Lab., Haifa, Israel

6.17 Coverage Driven Requirements ManagementAndre Winkelmann - Wolfson Microelectronics plc, Edinburgh, United KingdomJason Sprott - Verilab, Inc., Glasgow, United Kingdom

6.18 Effective Functional Vectors in a Partial Scan Paradigm – Challenges and Learning

Ballori Banerjee - LSI Corp., Bangalore, India6.19 Starting CDC from SDC

YoungChan Lee, Namdo Kim, Byeong Min - Samsung, Yongin-City, Republic of KoreaWesley Park - Mentor Graphics Corp., San Jose, CA

6.20 Facilitating Debug in ESL Design with Automated Root-Cause AnalysisKatsunobu Natori, Yuichi Soejima, Tetsuya Nakajima - Hitachi Ltd., Yokohama-shi, Japan

6.21 Property Checking of Datapath Using Word-Level Formal Equivalency Tools

Theo Drane - Imagination Technologies Ltd., Kings Langley, United KingdomHimanshu Jain - Synopsys, Inc., Hillsboro, OR

6.22 Integration of Enterprise Manager SQL Database in Verification CockpitMickael M. Moreau - STMicroelectronics, Grenoble, France

6.23 A Structured Power Grid Design Methodology and Analysis Considerations for a Low Cost, High Performance SoC

Siva Srinivas Kothamasu, Stalin SM - Texas Instruments, Inc., Bangalore, India

9:00 - 10:30am

12:30 - 1:30pm

User Track - Back End

User Track

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6.24 Full-Chip ESD Network Extraction and VerificationDundar Dumlugol, Jiri Ocenasek, Wim Schoenmaker, Bart De Smedt, Peter Meuris, Olivier Dupuis - Magwel NV, Leuven, BelgiumEdgardo Laber - Intersil Americas, Inc., Milpitas, CA

6.25 Understanding and Designing for Variation in GLOBALFOUNDRIES 28-nm Technology

Pei Yao, Richard Trihy - GLOBALFOUNDRIES, Milpitas, CAJiandong Ge, Kristopher Breen, Trent McConaghy - Solido Design Automation, Inc., Saskatoon, SK, Canada

6.26 Sensitivity Analysis of CMOS Devices Using a Field SolverKaren Chow, Yasu Nariki - Mentor Graphics Corp., Tokyo, JapanKunihiko Tsuboi - STARC, Yokohama, Japan

6.27 Congestion Analysis at Various Design Phases of a Complex Multi-Domain SoC and Avoidance Techniques to Improve Design Convergence and Cycle Time Improvement

Rivu Das, Stalin SM, Arun Koithyar - Texas Instruments, Inc., Bangalore, India6.28 Qualcomm DSP Tool Agnostic Relative Placement Design Flow

Nadeem Eleyan, Shahid Imam, Tung Pham, Dwight Galbi, Ken Lin, Paul Bassett - Qualcomm, Inc., Austin, TXDan Bui - Ciranova, Inc., Santa Clara, CA

6.29 Design Workflow Management for SoC ImplementationAlbert Li, Louis Liu, Reed Lee, Neil Liang, Chien-Chu(Alex) Kuo, Mei-Lin Liang - Global Unichip Corp., Yokohama, Japan

6.30 Novel Inizialization and Implementation Method for HBM ESD Compliance Automated Check on Smart Power ICs

Mauro Fragnoli, Eleonora Gevinti, Antonio Bogani, Lorenzo Cerati - STMicroelectronics, Agrate Brianza, Italy

6.31 Performance Path Test Statistical MethodologyJinjun Xiong, Vladimir Zolotov - IBM T.J. Watson Research Ctr., Yorktown Heights, NY Jeanne P. Bickford, Anthony Polson, Pamela S. Gillis, Jose M. Martinez, Francis Woytowich - IBM Systems and Technology Group, Essex Junction, VTVikram Iyengar - IBM Systems and Technology Group, Pittsburgh, PAKevin Bercaw - IBM Systems and Technology Group, Research Triangle Park, NCChandu Visweswariah - IBM Systems and Technology Group, Hopewell Junction, NY

6.32 Impact of Lithography and Stress on 28nm Design Performance Edward Teoh, Jianhao Zhu - GLOBALFOUNDRIES, SingaporePhilippe Hurat - Cadence Design Systems, Inc., San Jose, CA

6.33 On-Chip Noise Coupling Analysis Jacob Bakker, Sergei Kapora, Marcel Pelgrom, Boris Ljevar, Andries van der Veen - NXP Semiconductors, Eindhoven, The NetherlandsKeith A. Sabine - ANSYS, Inc, Chinnor, United KingdomJerome Toublanc - Apache Design, Inc. a subsidiary of ANSYS, Inc., Grenoble, FranceYing-Shiun Li - Apache Design, Inc. a subsidiary of ANSYS, Inc., San Jose, CA

6.34 Substrate and Metal Layer Noise “Heat Maps” Generated with Apache Totem Predict Improved Noise Performance in a Mass-Produced Image Sensor Chip

Kenneth F. Boorom - Aptina Imaging Corp., Corvallis, ORShaan Awasthi - ANSYS, Inc, San Jose, CA

6.35 Design and Use of Stress Managing Cells for Timing ClosurePuneet Sharma - Freescale Semiconductor, Inc., Austin, TX

6.36 Stable Physical Synthesis for Design IterationsCliff Sze, Gi-Joon Nam - IBM Research - Austin, TXPaul Villarrubia - IBM Corp., Austin, TXNatarajan Viswanathan - IBM Systems and Technology Group, Austin, TX

PRACTICAL FORMAL METHODS

4:00 - 6:00pm

1:30 - 3:00pm

Chair: Krishnan Sundaresan - Oracle, Santa Clara, CA

Formal methods are now successfully deployed in a variety of practical applications. But, significant challenges must be overcome to enable wider adoption. Presentations include verification of arbitration logic and bypass logic, a case study of formal versus structural verification, engineers’ suggestions for FV research, verification of a complex design with just three assertions, and formal equivalence checking challenges of a supercomputer on chip.

8.1 Formal Verification of Arbitration Logic (4:00pm)Gadiel Auerbach, Fady Copty, Katia Patkin - IBM Haifa Research Lab., Haifa, IsraelKrishnan Kailas - IBM T.J. Watson Research Ctr., Yorktown Heights, NYViresh Paruthi - IBM Systems and Technology Group, Austin, TX

8.2 Deploying Model Checking for Bypass Verification (4:15pm)Vigyan Singhal, Prashant Aggarwal - Oski Technology, Inc., Gurgaon, IndiaMichelle Liu, Wanli Wu - Cisco Systems, Inc., San Jose, CA

Chair:Gary Smith - Gary Smith EDA, Santa Clara, CA

Speakers:Joshua Friedrich - IBM Server and Technology Group, Austin, TXViresh Paruthi - IBM Server and Technology Group, Austin, TXStephen Shuma - IBM Server and Technology Group, Austin, TXBrad Heaney - Intel Corp., Folsom, CAMadhu Ponnada - Intel Corp., Folsom, CARama Ramakrishnan - Intel Corp., Folsom, CAArtour Levin - Intel Corp., Folsom, CAOmar Malik - Intel Corp., Folsom, CA

8.3 Functional vs. Structural Verification - Case Study (4:30pm)Gadiel Auerbach, Hana Chocler, Shiri Moran - IBM Haifa Research Lab., Haifa, IsraelViresh Paruthi - IBM Systems and Technology Group, Austin, TX

8.4 The Wiggler’s Manifesto: What Formal Verification Engineers Really Need from EDA Research (4:45pm)

Erik Seligman, Prakash Math, Tom Schubert - Intel Corp., Hillsboro, OR8.5 How we Verified 5000 Lines of a Complex Multiplexing Code with Three Assertions (5:00pm)

Nalin Nimavat - Cisco Systems, Inc., San Jose, CAVigyan Singhal - Oski Technology, Inc., Mountain View, CA

8.6 Formal Equivalence Verification (FEV) Challenges of a Supercomputer-On-A-Chip (5:15pm)

Amrendra Kumar, Pei-Wen Wu, Joonyoung Kim - Intel Corp., Santa Clara, CA

This special session is an interactive follow-up to the morning keynotes by Joshua Friedrich (IBM) and Brad Heaney (Intel). Senior leaders from both design teams will sit for a moderated Q/A panel session with the audience. The first half of the session will be with the IBM team; the second half will be with the Intel team. Take advantage of this unusual opportunity!

User Track - Front End

User Track



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7 DESIGNER PANEL - INTERACTIVE KEYNOTE QUESTION AND ANSWER SESSION

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THURSDAY, JUNE 7

www.DAC.com

CLOCKS AND TIMING

3:30 - 5:30pmChair:

Srinivas Nori - GLOBALFOUNDRIES, Sunnyvale, CAComplex clocking design and timing convergence continue to be top priorities in IC design. IBM, Samsung, and Juniper Networks showcase their approaches and successes in clock network design and timing analysis/convergence for advanced nodes. Presentations in this session include clock grid construction, clock mesh tuning, SSTA topics on pessimism removal and flexibility, and two convergence approaches for ECO routing and timing window reduction.

11.1 Robust Clock Grid Construction for Non-Uniform Clock Loads (3:30pm)Nancy Y. Zhou, Joseph Palumbo, Joseph Kozhaya - IBM Systems and Technology Group, Durham, NCZhuo Li, Cliff Sze - IBM Research - Austin, TXHaifeng Qian, Phillip Restle - IBM T.J. Watson Research Ctr., Yorktown Heights, NY

11.2 Design and Tuning of a Tree-Mesh Clock Distribution (3:45pm)Nikhil Jayakumar, Dave Murata, Valery Kugel - Juniper Networks, Inc., Sunnyvale, CA

11.3 Pessimism Reduction in Statistical Timing Analysis Using Liberty Standard Extensions to Model OCV (4:00pm)

Dileep Netrabile, Eric A. Foreman, Jeffrey G. Hemmett, Hemlata Gupta - IBM Systems and Technology Group, Hopewell Junction, NY

11.4 The Flexibility of Statistical Timing (4:15pm)Stephen Shuma, Eric Foreman - IBM Corp., Essex Junction, VT

11.5 ECO Routing Methodology for Timing Improvement (4:30pm)Gi-Joon Nam, Zhuo Li - IBM Research - Austin, TXNancy Zhou, Mike Kazda - IBM Server and Technology Group, Hopewell Junction, NY

11.6 A New Design Closure Methodology for Semicustom Circuit by Window Reduction (4:45pm)

Hyung-Ock Kim - Samsung, Yongin, Republic of Korea

User Track - Back EndRoom: 30311

VERIFICATION METHODOLOGIES

APPLICATIONS OF VIRTUAL PLATFORMS

Chair: Rob Aitken - ARM, Inc., San Jose, CA

As the scope of system integration increases, functional verification consumes an increasing percentage of design resources. This session includes presentations on several verification Methodologies. Topics include a discussion on what can be gained in moving from OVM to UVM, dealing with the lack of written specifications, solving SoC verification challenges with a UVM configuration mechanism, and optimizing transaction-based co-emulation performance.

9.1 The Big Question - Stay with OVM or Move to UVM? (9:00am)Manikandan S, Suleesh Rajendran, Sunil Kumar - LSI Corp., Bangalore, India

Chair: Ismed Hartanto - Xilinx, Inc., San Jose, CA

Virtual platforms are crucial for pre-silicon software development. They can also be used for architectural evaluation and exploration, as well as power modeling and optimization. This session includes two different ways of combining virtual platforms with a power modeling tool, along with a methodology for allowing reuse of models across both Simics and SystemC/TLM, and a system for creating and evaluating multiprocessor SoC platforms.

10.1 An ESL Power Flow for Optimizing and Validating the Power Management Strategy on a MultiCore SoC (1:30pm)

Xiaotao Chen - Huawei Technologies Co., Ltd., Bridgewater, NJPhilippe Garrault, Sylvian Kaiser - DOCEA Power SAS, Moirans, France

10.2 SyMX -- Model Crossover between Simics and SystemC/TLM Virtual System Platforms (1:45pm)

Christian Sauer, Hans-Peter Loeb - Cadence Design Systems, Inc., Munich, Germany

9.2 “Spec is in Designer’s Head!” Problem Demystified (9:15am)Terry Lam, Viba Viswanathan, Yirng-An Chen - Marvell Semiconductor, Inc., Santa Clara, CANitin Mhaske - NextOp Software, Inc., Santa Clara, CA

9.3 Advanced Applications of Resources: How we Solved our SoC Verification Challenges with UVM Configuration Mechanism (9:30am)

Abhisek Verma, Parag Goel, Amit Sharma - Synopsys, Inc., Bangalore, India9.4 Optimizing Transaction-Based Co-Emulation Performance (9:45am)

Takashi Kawabe - Konica Minolta Holdings, Inc., Hachioji-shi, JapanMitsuhiro Matsumoto - Nihon EVE K.K., Yokohama-shi, Japan

10.3 SiMPLiFy: An Abstract MPSoC Platform Framework for Enabling Fast Functional/Behavioral Simulation (2:00pm)

Michael Huebner - Ruhr - Univ. of Bochum, GermanyGabriel M. Almeida, Jurgen Becker - Karlsruhe Institute of Technology, Karlsruhe, GermanyOliver B. Longhi, Fabiano Hessel - Pontifíca Univ. Católica do Rio Grande do Sul, Porto Alegre, Brazil

10.4 Co-Simulation of a SystemC TLM Virtual Platform with a Power Simulator at the Architectural Level: Case of a Set-Top Box (2:15pm)

Jerome Cornet, Laurent Maillet-Contoz - STMicroelectronics, Grenoble Cedex, FranceIlija Materic, Hela Boussetta - DOCEA Power, Moirans, FranceSylvian Kaiser - DOCEA Power SAS, Moirans, FranceTayeb Bouhadiba - Verimag, Gieres, FranceMatthieu Moy, Florence Maraninchi - Grenoble Institute of Technology, Verimag, Gieres, France

9:00 - 10:30am

1:30 - 3:00pm

User Track - Front End

User Track - Embedded Systems and Software

Room: 303

Room: 303

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PERSPECTIVE PAPERS AT DAC“Perspectives” is a new submission category that solicits content traditionally not present in the conference: surveys, new problem formulations, critiques, comparative studies, and position papers. A Perspectives presentation provides a broader view than a traditional presentation, and brings excellent speakers to the conference. This year’s Perspectives include:

DESIGN AUTOMATION FOR THINGS WET, SMALL, SPOOKY, AND TAMABLE

FACING DEPENDABILITY: SYSTEM-LEVEL SOLUTIONS AND CYBERCAR CHALLENGES

IS FORMAL VERIFICATION READY FOR THE SYSTEM LEVEL?

DESIGN, THE NEXT GENERATION: FROM ROUTING TO CAPTURING DESIGN EXPERTISE

SOS: SPECIFICATION, OPTIMIZATION, AND SYNTHESIS IN SYSTEM-LEVEL DESIGN

PANEL: PARALLELIZATION AND SOFTWARE DEVELOPMENT: HOPE, HYPE, OR HORROR?

3.5 A Microgrid View of Energy Efficient Systems (11:00am)Rajesh Gupta - Univ. of California at San Diego, La Jolla, CA

11.5 EDA for Secure and Dependable Cybercars: Challenges and Opportunities (2:30pm)Farinaz Koushanfar - Rice Univ., Houston, TXIng. Ahmad-Reza Sadeghi, Hervé Seudié - Technische Univ. Darmstadt, Germany

16.5 Sciduction: Combining Induction, Deduction, and Structure for Verification and Synthesis (5:00pm)Sanjit A. Seshia - Univ. of California, Berkeley, CA

27.5 Avoiding Game Over: Bringing Design to the Next Level (2:30pm)Mark Horowitz, Ofer Shacham, Megan Wachs, Andrew Danowitz, Sameh Galal, John Brunhaver, Wajahat Qadeer, Sabarish Sankaranarayanan, Artem Vassillev, Steve Richardson - Stanford Univ., Stanford, CA

29.5 Embedded Systems - The Neural Backbone of Society (2:30pm)Rolf Ernst - Technische Univ. Braunschweig, Germany

49.1 PhD or MD - Who is Better Trained for Building Successful Software Development Tools? (2:45pm)Andreas Kuehlmann - Coverity, Inc., San Francisco, CA

Tuesday, June 5 - 10:00 - 11:30am

Tuesday, June 5 - 1:30 - 3:00pm

Tuesday, June 5 - 4:00 - 6:00pm

Wednesday, June 6 - 1:30 - 3:00pm

Wednesday, June 6 - 1:30 - 3:00pm

Thursday, June 7 - 3:30 - 5:30pm




Physical Design


General Interest

Room: 300

Room: 308

Room: 306

Room: 300

Room: 308

Room: 305

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MONDAY, JUNE 4

Each tutorial below is presented multiple times to allow you to cover multiple topics. Additional Registration Fees Apply

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TUTORIALS

SYNTHESIZING SYSTEMC TO LAYOUT

ENOUGH TALK! PRACTICAL APPROACHES TO 3-D IC - TSV/SILICON INTERPOSER AND WIDE IO IMPLEMENTATION FROM PEOPLE WHO HAVE BEEN THERE AND DONE THAT

SYSTEM-LEVEL EXPLORATION OF POWER, TEMPERATURE, PERFORMANCE, AND AREA FOR MULTICORE ARCHITECTURES

Speaker: Michael A. Bohm - Intel Corp., Hillsboro, OR

Capturing digital designs as RTL and synthesizing to layout has been the defacto standard for thirty years. Over the years our industry has been quite successful refining this process, driving industrial growth in SoC, ASIC, and FPGA implementations. At this point, significant further refinements of the RTL methodology are difficult to achieve. Further advancements in our design efficiency will require employing new methods.

Speakers: Frank Lee - Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TaiwanMarc Greenberg - Cadence Design Systems, Inc., Austin, TX

3-D IC and Silicon Interposer with Through Silicon Via (TSV) and wide IO type of DRAMs have been hot topics for the last few years, because they offer a revolutionary increase in bandwidth and reduction in power for inter-chip communication especially for the critical GPU/CPU to DRAM connection. While there is some information available on what could be achieved with 3-D IC, the question is what is the most practical approach to utilizing the best of both worlds - 3-D IC and Silicon Interposer with TSVs and wide IO technology. Given challenges with designing 3-D stacks with TSVs, testing 3-D stacks, the production process and the state of the ecosystem, the most practical solution today may be using Silicon Interposers to integrate wide IO memory with the logic device.

Speakers: Houman Homayoun - Univ. of California at San Diego, La Jolla, CAManish Arora - Univ. of California at San Diego, La Jolla, CAAmin Ansari - Univ. of Illinois at Urbana-Champaign, Urbana, IL

With the proliferation of multicore architectures, system designers critically need simulation tools to perform early design space exploration of different architectural configurations. Designers typically need to evaluate the effect of different applications on power, performance, temperature, area, and reliability of multicore architectures.

While architectural simulators such as Simplescalar integrated with HotSpot and Wattch have been used in the past to perform design space evaluation, several factors drive the need for new tools to address both changes in technology as well as the proliferation of multicore processor architectures. Many new simulation frameworks are emerging that attempt to accurately model power, temperature,

Many companies have had success building chips using the current third generation High-Level Synthesis (HLS) tools which accept SystemC as the input language. Leveraging these quite robust HLS tools facilitates an automated approach for developing digital designs where the HLS scheduling engine accepts the timing, power, and physical constraint information early in the design process, allowing efficient semi-automatic exploration of a circuits design space with tight correlation to the final layout.

Building further on this process, we are moving test, power, and reliability issues earlier into the design flow in order to optimize a design directly for manufacturability.

This tutorial will demonstrate a methodology that defines a recommended flow and identifies the issues and pitfalls involved in synthesizing a High-Level SystemC model to a placed gates layout.

This tutorial session walks participants through what they really need to know to be successful in their first 3-D design project. We present a practical approach to helping them prepare for and execute a successful TSV design project utilizing Silicon Interposer and wide IO memory. We start at chip planning, die, IP, and tool selection, continue through thermal planning, chip design, inter-chip routing and/or silicon interposer design, and finish with physical verification, manufacturing, assembly, packaging, and test.

area, and timing characteristics. These tools allow accurate modeling the effects of deep-submicron technologies, as well as all accurately model the various subcomponents of these complex multicore platforms.

This tutorial first briefly reviews the state of the art in simulators and modeling tools including; SMTSIM, GEM5, SESC as representative cycle accurate processor core performance simulators; DARSIM for cache interconnection network modeling and evaluation; HotSpot for thermal estimation; and CACTI and NVSIM for power and area modeling of various SRAM and NVM memory technologies and McPAT (Multicore Power, Area, and Timing) to model power, area, and timing of multicore architectures. The tutorial then presents example frameworks and workflows integrating these tools to allow the accurate modeling of various parameters of interest for state of the art multicore architectures.



General Interest

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Room: 310

Room: 302

Room: 305

8:30 - 10:30am, 11:30am - 1:30pm, 3:30 - 5:30pm

8:30 - 10:30am, 11:30am - 1:30pm, 3:30 - 5:30pm

8:30 - 10:30am, 11:30am - 1:30pm, 3:30 - 5:30pm

2

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MONDAY, JUNE 4

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TUTORIALS Each tutorial below is presented multiple times to allow you to cover multiple topics. Additional Registration Fees Apply

UNDERSTANDING AND OVERCOMING PATTERNING-INDUCED DESIGN CHALLENGES IN THE 20NM AND 14NM TECHNOLOGY NODES

ANALOG AND MIXED-SIGNAL DESIGN AT ADVANCED PROCESS NODES

PRE-SILICON, NATIVE EMBEDDED SOFTWARE DEVELOPMENT SOLUTIONS

Speakers: Kuang-Kuo Lin - Samsung, San Jose, CAVassilios Gerousis - Cadence Design Systems, Inc., San Jose, CALars Liebmann - IBM Corp., Hopewell Junction, NYAndres Torres - Mentor Graphics Corp., Wilsonville, OR

Speakers: Jim McMahon - Cadence Design Systems, Inc., San Jose, CAErik Wanta - Freescale Semiconductor, Inc., Tempe, AZ Robert (Bob) Mullen - Taiwan Semiconductor Manufacturing Co., Ltd., San Jose, CAStacy Whiteman - Cadence Design Systems, Inc., San Jose, CAFang-Cheng Chang - Cadence Design Systems, Inc., San Jose, CA

To take advantage of area and power reduction in advanced process node, analog designers must consider many issues not required in the past to be successful in realizing analog and mixed-signal circuits in silicon. Parametric variation, parasitic, layout dependent effects, and double patterning have a significant impact on performance of circuits at these geometries. Previously these were secondary, post design clean up issues; now they must be addressed from the earliest stages of the design in order to predict performance of the circuits in silicon and avoid costly design iterations.Scaling the devices down to 28/20nm and meeting specifications requires an advanced design flow which enables designers to explore the impact of the different effects during circuit design and make educated tradeoffs leading to design convergence through the layout and signoff stage. The flow must provide acceptable productivity and turn-around-time to meet the demanding-time-to-market schedules.

Speakers: Robert Kaye - ARM, Inc., Cambridge, United KingdomJon McDonald - Mentor Graphics Corp., Wilsonville, ORMark Mitchell - Mentor Graphics Corp., San Jose, CA

Emulation and virtual platforms enable hardware design teams to begin verification ahead of silicon. However, embedded software development and verification is increasingly a bottleneck. The challenge is to find a way for software developers to work within their native software environment, while relying on virtual and emulated representations of the design.

This session will detail a process that enables the software and hardware teams to work in parallel, without requiring them to become experts in each other’s domain.

With the delayed availability of extreme ultraviolet (EUV) lithography and other non-optical patterning techniques, the semiconductor industry is faced with having to manufacture deep below the resolution limit of existing lithography tools. Much attention is given to wafer cost increase for these aggressively scaled technologies, but the potential loss of design efficiency is equally daunting. This tutorial will provide insight into patterning challenges, the computational scaling techniques used to overcome these challenges, and the design implications resulting from these techniques, helping designers become more efficient with these leading-edge technology nodes. The tutorial will also review design and enablement infrastructure being put in place to minimize the impact that resolution-challenged technology nodes have on design efficiency and quality.

This tutorial will present methodologies and techniques for:• Advanced statistical analysis• Early parasitic estimation and parasitic-aware implementation• Circuit sensitivity to Layout Dependent Effects (LDE) and LDE-aware layout• Identifying and addressing device reliability issues• Digitally assisted analog design

Results of a 28/20nm analog/mixed signal flow validation as part of TSMC AMS initiative will be presented, as well.

Participants completing this tutorial will understand the issues impacting scaling of analog circuits and a methodology to address them in order to be successful designing analog and mixed signal circuits at these advanced process nodes.

Specifically, the tutorial will cover:

Hardware: defining a system based on platform subsystem IP, the development and integration of hardware acceleration blocks, analyzing hardware performance criteria, verification of the SoC functionality, leveraging the embedded software to drive hardware verification.

Software: the parallel development and validation of software within a native software development (ide, compile, debug) environment, enabling software developers to move seamlessly between various representations of the hardware flow, including virtual prototypes, emulation, simulation, prototypes, and real hardware.




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Room: 307

Room: 306

Room: 309

8:30 - 10:30am, 11:30am - 1:30pm, 3:30 - 5:30pm

8:30 - 10:30am, 11:30am - 1:30pm, 3:30 - 5:30pm

8:30 - 10:30am, 11:30am - 1:30pm, 3:30 - 5:30pm

www.DAC.com

Additional Registration Fees Apply

38

SUNDAY, JUNE 3WORKSHOPS

DAC INTERNATIONAL WORKSHOP ON SYSTEM-LEVEL DESIGN OF AUTOMOTIVE ELECTRONICS/SOFTWARE8:30am - 5:30pmOrganizers:

Paolo Giusto - General Motors Company, Palo Alto, CAArkadeb Ghosal - National Instruments Corp., Berkeley, CAHaibo Zeng - McGill Univ., Montreal, Quebec, Canada

Workshop Chair: Alberto Sangiovanni-Vincentelli- Univ. of California, Berkeley, CA

Workshop Advisory Board:Raj Rajkumar - Carnegie Mellon Univ., Pittsburgh, PA Rolf Ernst - Technische Univ. Braunschweig, Germany Marco Di Natale - Scuola Superiore Sant’Anna, Pisa, Italy

Speakers: Roger Melen - Toyota Motor Corp., Mountain View, CAChristopher Oster - Lockheed Martin Corp., Philadelphia, PARaj Rajkumar - Carnegie Mellon Univ., Pittsburgh, PAMarco Di Natale - Scuola Superiore Sant’Anna, Pisa, ItalyGraham Hellestrand - EST Embedded Systems Technology, Los Altos, CA

In the last two decades, in-vehicle electronics and software content have increased at a faster rate than ever to address market demands for increasingly complex customer features (e.g., lane keeping) as well as tighter government regulations (e.g., fuel economy). The entire in-vehicle electronics and software eco-system (industry and academia) has been impacted. The automotive industry has faced

design and business challenges to address the market and government regulations, while maintaining profitability. The challenges include changing supply chain roles (e.g., adding new AUTOSAR software providers), increasing the amount of software integration with several parties involved, and providing the ability to control the system-level requirements in the context of IP-protected/black-box supply chains. While some of these challenges have been addressed in other markets (such as in aerospace and by the EDA/ESL tool industry) in the past, others are quite automotive-specific. Academia has researched and developed methods and tools in this area for many years.Standardization efforts to enable competition on customer features and remove it from infrastructure software and networking have emerged (e.g., FlexRay, AUTOSAR, and ISO26262). Standards can enable re-use of software components, and enable system-level modeling, analysis, simulation, and optimization of hardware and software for in-vehicle architectures prior to the availability of the actual components.

This workshop focuses on the past, present, and potential future landscape of system-level design with emphasis on the potential opportunities for the EDA/ESL industry and academia in providing tool support for modeling, analysis, simulation, and optimization of hardware and software automotive architectures. The workshop will cover the automotive industry requirements, the relationships and similarities with the aerospace industry, as well as the EDA/ESL industry and academia efforts in this area.

System Level Design and CommunicationRoom: 306

DAC WORKSHOP ON THE FOURTH INTERNATIONAL WORKSHOP ON BIO-DESIGN AUTOMATION AT DAC

General Chair: Natasa Miskov-Zivanov - Univ. of Pittsburgh, PA

General Secretary: Laura Adam - Virginia Polytechnic Institute and State Univ., Blacksburg, VA

Program Committee Chairs: Xiling Shen - Cornell Univ., Ithaca, NY, Deepak Chandran - Univ. of Washington, Seattle, WALeonidas Bleris - Univ. of Texas, Dallas, TX

Publication Chair: Chris Myers - Univ. of Utah, Salt Lake City, UT

Industry Liaison Chair: Jonathan Babb - Massachusetts Institute of Technology, Cambridge, MA

Finance Chair: Aaron Adler - BBN Technologies, Cambridge, MAFusun Yaman - BBN Technologies, Cambridge, MA

DAC Liaison: Smita Krishnaswamy - Columbia Univ., New York, NY

Speakers: Jasmin Fisher - Microsoft Corp., Cambridge, United KingdomWilliam Shih - Harvard Univ., Boston, MAMilan Stojanovic - Columbia Univ., New York, NY

The Fourth International Workshop on Bio-Design Automation (IWBDA) brings together researchers from the synthetic biology, systems biology, and design automation communities. The focus is on concepts, methodologies and software tools for the computational analysis of biological systems and the synthesis of novel biological systems. Still in its early stages, the field of synthetic biology has been driven by experimental expertise; much of its success has been attributable to the skill of the researchers in specific domains of biology. There has been a concerted effort to assemble repositories of standardized components. However, creating and integrating synthetic components remains an ad hoc process. The field has now reached a stage where it calls for computer-aided design tools. The electronic design automation (EDA) community has unique expertise to contribute to this endeavor. This workshop offers a forum for cross-disciplinary discussion, with the aim of seeding collaboration between the research communities. Topics of interest include: • Design methodologies for synthetic biology. • Standardization of biological components. • Automated assembly techniques. • Computer-aided modeling and abstraction techniques. • Engineering methods inspired by biology.

Sunday, 9:00am - 5:00pm - Monday, 10:30am - 6:30pm

Room: 308 Bio Design Automation

DAC WORKSHOP ON CMOS DESIGN AT 60 GHZ AND BEYOND: CAPABILITIES AND CHALLENGES

Organizers: Sotiris Bantas - Helic, Inc., San Francisco, CARobert Mullen - Taiwan Semiconductor Manufacturing Co., Ltd., San Jose, CA

Speakers: Robert Mullen - Taiwan Semiconductor Manufacturing Co., Ltd., San Jose, CASohrab Emami - Silicon Image, Inc., Sunnyvale, CASotiris Bantas - Helic, Inc., San Francisco, CAGeorges Gielen - Katholieke Univ. Leuven, BelgiumSharad Kapur - Integrand Software, Inc., Berkeley Heights, NJ

The anticipated proliferation of multi-gigabit applications in the 60GHz band (e.g. uncompressed video transmission, rapid file transfers) marks an uptick in millimeter-wave CMOS design. But are EDA vendors and silicon foundries ready to resolve the related challenges? This workshop brings together stakeholders from across the silicon design ecosystem to provide the audience with a comprehensive treatment of the subject.The workshop will address the challenges posed by CMOS design in the 60-GHz band and beyond, as well as the techniques being developed to address them by the ecosystem of IC designers, silicon providers, EDA tool vendors and research institutions. Presenters will offer examples from real silicon cases, discuss system-level aspects, outline design tool methodologies and address areas for further research.

8:30am - 12:30pm Room: 305 Analog/Mixed-Signal/RF Design

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SUNDAY, JUNE 3

Additional Registration Fees ApplyWORKSHOPS

DAC WORKSHOP ON THE FOURTH INTERNATIONAL WORKSHOP ON BIO-DESIGN AUTOMATION AT DAC

DAC WORKSHOP ON MORE THAN MOORE TECHNOLOGIES

DAC WORKSHOP ON COMPUTING IN HETEROGENEOUS, AUTONOMOUS ‘N’ GOAL-ORIENTED ENVIRONMENTS - (CHANGE)

8:30am - 6:00pm

8:30am - 6:00pm

Organizer: Rasit Topaloglu - IBM Corp., East Fishkill, NY

Speakers: Kaushik Roy - Purdue Univ., Lafayette, INTim Cheng - Univ. of California, Santa Barbara, CAAndrew Kahng - Univ. of California at San Diego, La Jolla, CASung Kyu Lim - Georgia Institute of Technology, Atlanta, GAYuan Xie - Pennsylvania State Univ., University Park, PAYiyu Shi - Missouri Univ. of Science and Technology, Rolla, MOPaul Franzon - North Carolina State Univ., Raleigh, NCMike Garner - Stanford Univ., Stanford, CALuca Carloni - Columbia Univ., New York, NYRajiv Joshi - IBM Corp., Yorktown Heights, NYSeung Kang - Qualcomm, Inc., San Diego, CAKeren Bergman - Columbia Univ., New York, NYOnur Mutlu - Carnegie Mellon Univ., Pittsburgh, PA

In order to align with system and device performance roadmaps and expectations, semiconductor devices scale to smaller dimensions with each generation. During scaling, electrical performance such as drive current needs to improve as well. While engineers have been successful to help devices scale, various innovations have been implemented along with algorithmic, computational, modeling solutions to the problems that they bring along. Examples of such important innovations that have been most relevant to the EDA and modeling domain have been stress modeling and optimization since 65 nm or double patterning since 22 nm.

Reaching 10 nm technology may require extreme ultra violet lithography and there is not much certainty into what may lead us below 10 nm. Even if such a transition occurs, there seems to be an increasing gap between what can be achieved with traditional scaling versus system-level expectations. For example, memory latencies and hierarchies are lagging due to large interconnect delays in larger systems. Such system-level challenges cannot be targeted by traditional Moore scaling.

Organizers: Marco Santambrogio - Politecnico di Milano, ItalyHank Hoffmann - Massachusetts Institute of Technology, Boston, MASimone Campanoni - Harvard Univ., Boston, MAMartina Maggio - Lund Univ., Sweden

Speakers: Satnam Singh - Google, Inc., Mountain View, CAJonathan Eastep - Intel Corp., Portland, ORJohn Kubiatowicz - Univ. of California, Berkeley, CAJian Li - IBM Research - Austin, TXXiaoyuan Zhu - VMware, Inc., San Francisco, CA

Heterogeneous, adaptable multicore systems can be considered the established trend in modern computing architectures. Silicon resources are increasingly abundant, runtime reconfigurable elements can be combined together with heterogeneous processing elements and many cores on a chip by processor designers. Such architectures provide important improvements in system performance, but also pose new research questions to be answered, i.e. will current processor interconnection mechanisms scale to thousands of cores? How can the runtime behavior, which cannot be fully understood at design time, be captured to be reflected into a physical implementation to extract high performance from the underlying hardware architecture?

In this scenario, imagine a revolutionary computing system that can observe its own execution and optimize its behavior around a user’s or application’s needs. Imagine a programming capability by which users can specify their desired goals rather than how to perform a task, along with constraints in terms of an energy budget, accuracy and execution time. Imagine further a computing system that

We propose a workshop with the key goal of discussing about potential More-than-Moore solutions and modeling and EDA challenges they bring. After identifying such challenges, we then discuss about potential solutions to such EDA problems. The workshop enables multiple More-than-Moore solutions to be discussed in the same place, thereby giving the opportunity to evaluate their impact at the system level.

For this workshop, we have identified three particular areas to focus on based on their likelihood and potential impact. These are 1) 3-D integration, 2) Novel memories, and 3) On-chip optics. From each area, we invite leading experts from industry and academia for presentations. These presentations are followed by a panel and a poster session, where additional contributions outside our invitee list will have a chance to be represented.

Presented papers and posters will be considered for a special issue magazine or journal at a later date.

Panel: “Are Models and Design Flows Ready for More than Moore?”

Panelists:Samta Bansal - Cadence Design Systems, Inc., San Jose, CAHerb Reiter - eda2asic Consulting, Inc., San Jose, CASeung Kang - Qualcomm, Inc., San Diego, CALeon Stok - IBM Corp., Hopewell Junction, NYValeriy Sukharev - Mentor Graphics Corp., San Jose, CANoel Menezes - Intel Corp., Hillsboro, OR

executes more efficiently the longer it runs an application. Such a system will enable, for example, a handheld radio or a cell phone that can run cooler the longer the connection time, a computer-farm that save energy autonomously based on the computation, a recycling spot that improve its way of managing and treating different kind of waste the longer it works.

Self-aware computer systems are the key technology to succeed in doing this. They will be able to configure, heal, optimize, improve interaction and protect themselves without the need for human intervention, exploiting abilities that allow them to automatically find the best way to accomplish a given goal with the resources at hand. Within this context, imagine a revolutionary computing system that can observe its own execution and optimize its behavior around the external environment, user’s and application’s needs.

The Self-aware computing research leverages the new balance of resources to improve performance, utilization, reliability and programmability. Within this context, the proposed workshop is intended to present innovative works describing:• Self-aware Operating Systems• Autonomous self-aware computer architecture• Adaptive algorithm and distributed self-training algorithms• Biologically inspired systems• Surveys and/or prospective papers in self-aware computing systems



Room: 309

Room: 307

www.DAC.com

Additional Registration Fees Apply

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SUNDAY, JUNE 3WORKSHOPS

DAC WORKSHOP ON EDA ON PROCESS AUTOMATION9:00am - 4:00pmOrganizer:

Michael Hübner - Ruhr - Univ. of Bochum, Germany Speakers:

Joris Pascal - ABB Group, Daetwil, SwitzerlandDiana Göhringer - Karlsruhe Institute of Technology, Karlsruhe, GermanyDagan White - Xilinx, Inc., San Jose, CA

Process automation is a worldwide growing topic in industrial and academic research and development. Especially the hard constraints for power consumption, real-time, extreme high reliability and low costs lead to a nearly unlimited design space which needs to be handled with novel design methodologies from EDA.

This workshop is about the latest technologies for highly energy efficient hardware and the required design tools. Design and technology in process automation is at its limit. Novel technologies coming from ultra low power multicore technologies, also reconfigurable hardware are a relevant topic in industrial and academic research and development.

The design space, even if limited by hard constraints, are no longer manageable by the designer. Especially if also novel processor cores, sometimes a number of heterogeneous cores are used to run a system. Hardware / software codesign will be in future a topic in this domain and opens a variety of scientific questions to be answered.

Embedded Architecture & PlatformsRoom: 310

YOUNG FACULTY WORKSHOP AT DAC

Organizers: Steven Levitan - Univ. of Pittsburgh, PASoha Hassoun - Tufts Univ., Medford, MAKartik Mohanram - Univ. of Pittsburgh, PA

This is a special workshop organized for current, or soon to be, young faculty in the fields of electronic design automation (EDA). The workshop will be organized as presentations by EDA senior professionals around six themes, with additional opportunities to network with some of the established researchers and funding officers in the field of Electronic Design Automation.

The themes this year include: Getting an Academic Job, Research - papers, conferences and grants, The NSF proposal process for CAREER and other programs, Teaching - Best practices, Special Issues and a “Speed Networking” lunch event. There is a limited budget for travel support for attendees.

Visit DAC website for additional event details.

9:00am - 6:00pm Room: 301 Other

DAC WORKSHOP ON POST-SILICON DEBUG: TECHNOLOGIES, METHODOLOGIES, AND BEST-PRACTICES

Moderator:Harry Foster - Mentor Graphics Corp., Plano, TX

Organizer:Amir Nahir - IBM Haifa Research Lab., Haifa, Israel

Speakers: Alan Hu - Univ. of British Columbia, Vancouver, BC, CanadaSubhasish Mitra - Stanford Univ., Stanford, CAValeria Bertacco - Univ. of Michigan, Ann Arbor, MISharad Kumar - Freescale Semiconductor, Inc., Noida, IndiaBradley Quinton - Tektronix, Inc., Vancouver, BC, CanadaEric Rentschler - Advanced Micro Devices, Inc., Fort Collins, COKeshavan Tiruvallur - Intel Corp., Portland, ORNagib Hakim - Intel Corp., Santa Clara, CAKevin Reick - IBM Corp., Austin, TXWisam Kadry - IBM Haifa Research Lab., Haifa, Israel

As the complexity of digital systems grow, designing and manufacturing a fully functional system becomes harder and harder. Despite on-going improvements to pre-silicon verification practices and technologies, they alone can no longer meet the verification goals. As a result, a significant part of the verification is now executed on actual silicon, as part of the system’s bring-up.

Performing verification on real silicon introduces new and different challenges. On the one hand, real silicon offers great execution speed; on the other hand, it is lacking the controllability and observability which serve an important role in pre-silicon verification.

The lack of observability into the design makes the task of debugging a fail observed in the lab to be of extreme complexity. Current practice significantly relies on designer expertise, tremendous labor, and is in many cases - pure luck.In recent years several methods and mechanisms have been proposed for the sake of easing the debug task. Since adding debug logic to the actual silicon is costly (in area and power), this brings about the challenge of determining the optimal way of instrumenting the design for silicon debug while using the minimal amount of required additions to the logic.

This workshop brings together experts from academia and industry to present different instrumentation strategies, as well as the methods of using the data collected by the debug logic to facilitate fast and efficient debug.

9:00am - 3:00pm Room: 309 Verification and Test

THURSDAY, JUNE 7

special interest group on

design automation

www.DAC.com 41

WEDNESDAY, JUNE 6 - 6:00 - 7:00pm - Esplanade Foyer

ROUTABILITY-DRIVEN PLACEMENT CONTEST POSTER PRESENTATION

YOUNG FACULTY WORKSHOP AT DAC

1. Team Name: RippleTeam Affiliation: The Chinese University of Hong KongTeam Members: Xu He, Tao Huang, Wing-Kai,Chow, Yuan Jiang, Evangeline F.Y. Young

2. Team Name: mPL12Team Affiliation: UCLA / Beijing UniversityTeam Members: Jason Cong, Guojie Luo, Kalliopi Tsota, Bingjun Xiao

3. Team Name: SimPLRTeam Affiliation: The University of Michigan, Ann ArborTeam Members: Myung-Chul Kim, Jin Hu, Igor Markov

4. Team Name: NTUplace4Team Affiliation: National Taiwan UniversityTeam Members: Meng-Kai Hsu, Yao-Wen Chang

5. Team Name: NCKU-PlacerTeam Affiliation: National Cheng Kung UniversityTeam Members: Chung-Lin Lee, Sheng-Wen Chen, Kai-Chung Chan, Jing-Chang Wang

6. Team Name: VDAPlaceTeam Affiliation: National Chiao Tung UniversityTeam Members: Sean Shih-Ying Liu, Ching-Yu Chin, Sheng-De Hu

7. Team Name: LUCASTE_PDTTeam Affiliation: Politecnico di TorinoTeam Members: Luca Sterpone

8. Team Name: AlleconTeam Affiliation: Tsinghua UniversityTeam Members: Zhongdong Qi, Wenchao Gao, Sifei Wang, Zekun Wu

9. Team Name: UIPlacerTeam Affiliation: University of Illinois at Urbana-ChampaignTeam Members: Haitong Tian, Zigang Xiao

10. Team Name: GoalTeam Affiliation: Department of Computer Science, National Chiao Tung UniversityTeam Members: Tsung-Han Wu, Shih-Tsang Liao, Ke-Ren Dai

11. Team Name: NCUplacerTeam Affiliation: Department of Electrical Engineering, National Central UniversityTeam Members: Tai-Chen Chen, Kuo-Ting Liu, Pei-Yu Lee

Co-Sponsored by:

www.DAC.com42

WORK-IN-PROGRESS (WIP)WEDNESDAY, JUNE 6 6:00 - 7:00pm Esplanade Foyer

55.1 CaaS: Core as a ServiceBring SOA to Reconfigurable MPSoC for Chip Level ParallelizationChao Wang, Peng Chen, Xi Li, Junneng Zhang, Xiaojing Feng, Xuehai Zhou - Univ. of Science and Technology of China, Suzhou, China

55.2 TSV-Based On-Chip Spiral Inductor and Near-Field Wireless CommunicationsKhaled Mohamed, Alaa E. El-Rouby - Mentor Graphics Corp., Cairo, EgyptYehea Ismail, Hani Ragai - American Univ. of Cairo, Egypt

55.3 Splogd: An Open Source Hardware Description Language for Android OS PlatformAnirban Chatterjee - BITS Pilani, Bangalore, India

55.4 Systematic Comparison of Analog Circuits Through Dual Topological-Symbolic MatchingAlex Doboli, Cristian Ferent - State Univ.of New York, Stony Brook, NY

55.5 Two New Finite-State Machine-Based Topologies for Synthesizing Target Functions in Stochastic ComputingPeng Li, David J. Lilja, Marc Riedel, Kia Bazargan - Univ. of Minnesota, Minneapolis, MNWeikang Qian - Shanghai Jiao Tong Univ., Shanghai, China

55.6 A Multicore Architecture for Control and Emulation of Power Electronics and Smart Grid SystemsMichel A. Kinsy, Jason Poon, Ivan Celanovic, Omer Khan, Srinivas Devadas - Massachusetts Institute of Technology, Cambridge, MA

55.7 Addressing FPGA Design, Verification, and Debug Productivity Challenges through Increased AbstractionBradley R. Quinton, Steven Wilton - Tektronix, Inc., Vancouver, BC, CanadaEddie Hung - Univ. of British Columbia, Vancouver, BC, Canada

55.8 Breaking the Curse of High Dimensionality: An Efficient Rare-Event Estimation Algorithm in High DimensionYiyu Shi - Missouri Univ. of Science and Technology, Rolla, MOFang Gong, Lara Dolecek, Lei He - Univ. of California, Los Angeles, CA

55.9 Co-Synthesis of Data Paths and Clock Control Paths for Clock Period MinimizationWen-Pin Tu, Shih-Hsu Huang, Chun-Hua Cheng - Chung Yuan Christian Univ., Chung Li, Taiwan

55.10 ODT - Dependence Tracking in Multicore Processors for Post-Silicon DebugMatteo Monchiero, Intel Corp., Santa Clara, CAJavier Carretero Casado,Tanausu Ramirez, Enric Herrero, Xavier Vera- Intel Corp., Barcelona, SpainCharan Sundararaman - Intel Corp., Hillsboro, OR

55.11 Register and Thread Parallelism Optimization for GPGPUYun Liang, Zheng Cui, Kyle Rupnow - Advanced Digital Sciences Center, SingaporeDeming Chen - Univ. of Illinois at Urbana-Champaign, Urbana, IL

55.12 A Regression-Based Entropy Distiller for RO PUFsChi-En Yin, Gang Qu - Univ. of Maryland, College Park, MD

55.13 LASIC: Loop-Aware Sleepy Instruction Caches Based on STT-RAM TechnologyJunwhan Ahn, Kiyoung Choi - Seoul National Univ., Seoul, Republic of Korea

55.14 Vertical Arbitration-free 3-D NoCsAnkit More, Baris Taskin - Drexel Univ., Philadelphia, PA

55.15 Compiler Techniques for Energy Efficiency and Real-Time GuaranteesEmilio Wuerges, Romulo Silva de Oliveira, Luiz C.V. Santos - Univ. Federal de Santa Catarina, Florianopolis, Brazil

55.16 Extend Amdahl?s Law to Achieve Loading Balance in Heterogeneous On-Chip ClustersChao Wang, Xi Li, Junneng Zhang, Xuehai Zhou - Univ. of Science and Technology of China, Suzhou, China

55.17 Segmented and Adaptive NoC Architecture for Multi-Systems on Chip with Scalable MulticoreHsiang-Jen Tsai, Tien-Fu Chen, Chien-Chih Chen - National Chiao Tung Univ., HsinChu, Taiwan

55.18 Using a Hardware Description Language as an Alternative to Printed Circuit Board Schematic CaptureBradley Riching, Brent E. Nelson, Richard Black - Brigham Young Univ., Provo, UT

55.19 Towards Symbolic Loop Parallelization for Tightly-Coupled Processor ArraysFrank Hannig, Alexandru Tanase, Jürgen Teich - Univ. of Erlangen-Nuremberg, Germany

55.20 Interactive Host-Assisted Execution Framework for Wireless Sensor NodesAhmad Abiri, Pai H. Chou - Univ. of California, Irvine, CA

55.21 TinySPICE: A Parallel SPICE Simulator on GPU for Massively Repeated Small Circuit SimulationsLengfei Han, Xueqian Zhao, Zhuo Feng - Michigan Technological Univ., Houghton, MI

55.22 Domain Wall Memory Based CacheRangharajan Venkatesan, Vivek Kozhikkottu, Kaushik Roy, Anand Raghunathan - Purdue Univ., West Lafayette, INCharles Augustine, Arijit Raychowdhury - Intel Corp., Hillsboro, OR

55.23 Symbolic Analysis-Based Iterative Memory Partitioning for Generating Custom, Multi-Level Cache HierarchiesEmre Kultursay, Mahmut Kandemir - Pennsylvania State Univ., University Park, PAKemal Ebcioglu - Global Supercomputing, Yorktown Heights, NY

Chair: Tajana Simunic - Univ. of California at San Diego, La Jolla, CA

www.DAC.com 43


55.24 Pin Density-Driven Placement for Routing Congestion ReductionKalliopi Tsota, Jason Cong, Bingjun Xiao - Univ. of California, Los Angeles, CAGuojie Luo - Peking Univ., Beijing, China

55.25 Relaxing Writes in Non-Volatile Processor Cache using Frequent Value LocalityMohammad Arjomand, Hamid Sarbazi-Azad, Amin Jadidi - Sharif Univ. of Technology, Tehran, Iran

55.26 A Fine-Grained Dynamic Power Management of DRAM/PRAM-Based Main MemoryHyunsun Park, Sungjoo Yoo - Pohang Univ. of Science and Technology, Pohang, Republic of Korea

55.27 Retiming for Soft Error Optimization Under Error-Latching Window ConstraintsYinghai Lu - Synopsys, Inc., Mountain View, CAHai Zhou - Northwestern Univ., Evanston, IL

55.28 ARGO: An Application-Specific Run-Time Goal Management Framework for Multiprocessors ArchitecturesVittorio Zaccaria, Cristina Silvano, Vincenzo Consales, Gianluca Palermo, Andrea Di Gesare, Iyad Al Khatib - Politecnico di Milano, ItalyChantal Ykman-Couvreur - IMEC, Leuven, Belgium

55.29 On Flexible Trace Interconnection Fabric Design for Silicon DebugQiang Xu, Xiao Liu - The Chinese Univ. of Hong Kong, Shatin, Hong Kong

55.30 Towards Cost Effective Multi-Core Processor Platforms Using 3-D Stacking TechnologyAlessandro Cevrero, Giulia Beanato, Panagiotis Athanasopoulos, Yusuf Leblebici - Ecole Polytechnique Fédérale de Lausanne, Switzerland

55.31 DMR3D: Dynamic Memory Relocation in 3-D Multicore SystemsKoushik Chakraborty, Dean Michael Ancajas, Sanghamitra Roy - Utah State Univ., Logan, UT

55.32 Parallel Preconditioners Based on Fast Poisson Solvers for Efficient Large-Scale Power Grid AnalysisKonstantis Daloukas, Maria-Aikaterini Rammou, George A. Drasidis, Michalis Tsiampas, Nestoras Evmorfopoulos, Panagiota Tsompanopoulou, George Stamoulis - Univ. of Thessaly, Volos, Greece

55.33 Interval Arithmetic Based Input Vector Control for RTL Subthreshold Leakage MinimizationShilpa Pendyala, Srinivas Katkoori - Univ. of South Florida, Tampa, FL

55.34 QoS-Aware Real-Time Scheduling for Energy Harvesting SystemsHessam Kooti, Nga Dang, Deepak Mishra, Eli Bozorgzadeh - Univ. of California, Irvine, CA

55.35 A Multi-Controller Design for Solid-State DrivesChin-Hsien Wu, Jhih-Jian Liao - National Taiwan Univ. of Science and Technology, Taipei, Taiwan

55.36 Automatic TLM Model Generation for Cycle-Count-Accurate Bus SimulationChen-Kang Lo, Mao-Lin Li, Shu-Yung Chen, Ren-Song Tsay - National Tsing Hua Univ., HsinChu, TaiwanJen-Chieh Yeh - Industrial Technology Research Institute, Hsinchu, Taiwan

55.37 An RSM-Guided Exploration Framework for Custom Coprocessor SynthesisVittorio Zaccaria, Cristina Silvano, Sotirios Xydis, Gianluca Palermo - Politecnico di Milano, Italy

55.38 A Design Space Exploration Prototype for Run-Time Support on Manycore ArchitecturesCristina Silvano, Vittorio Zaccaria, Sotirios Xydis, Gianluca Palermo, Iyad Al Khatib - Politecnico di Milano, ItalyChantal Ykman-Couvreur - IMEC, Leuven, BelgiumAlex Bartzas, Dimitrios Soudris - National Technical Univ. of Athens, Greece

55.39 A Methodology for the High-Level Synthesis of Iterative AlgorithmsAlessandro A. Nacci, Francesco Bruschi, Vincenzo Rana - Politecnico di Milano, Italy

55.40 VeriTrust: Verification for Hardware TrustJie Zhang, Qiang Xu, Feng Yuan - The Chinese Univ. of Hong Kong, Shatin, Hong Kong

55.41 Scalable Parallel Event-Driven HDL Simulation for Multi CoresSeiyang Yang - Pusan Univ., Pusan, Republic of KoreaTariq B. Ahmad, Maciej Ciesielski - Univ. of Massachusetts, Amherst, MANamdo Kim, Byeong Min - Samsung, Yongin-City, Republic of KoreaApurva Kalia - Cadence Design Systems, Inc., Noida, India

55.42 Electro-Thermal Analysis of 3-D Power Delivery NetworksAida Todri, Patrick Girard, Alberto Bosio, Luigi Dillilo, Arnaud Virazel - LIRMM, Montpellier, FranceSandip Kundu - Univ. of Massachusetts, Amherst, MA

55.43 Automated Architectural Synthesis of Flow-Based Microfluidic Large-Scale Integration BiochipsWajid H. Minhass, Paul Pop, Jan Madsen - Technical Univ. of Denmark, Kongens Lyngby, Denmark

55.44 Efficient Software-Based Fault Tolerance Approach on Multicore PlatformsKoen Bertels, Hamid Mushtaq - Delft Univ. of Technology, Delft, The Netherlands

55.45 Detecting Delay Faults with Logic ImplicationsKundan Nepal - Univ. of St. Thomas, St. Paul, MNJennifer Dworak - Southern Methodist Univ., Dallas, TXIris Bahar - Brown Univ., Providence, RI

55.46 A Virtual Write Buffer in Last Level Cache for STT-RAM Based Main MemoryYounggeun Choi, Sungjoo Yoo - Pohang Univ. of Science and Technology, Pohang, Republic of Korea

www.DAC.com44


55.47 Layout Small-Angle Rotation and Shift for EUV Defect MitigationHongbo Zhang, Yuelin Du, Martin D. F. Wong - Univ. of Illinois at Urbana-Champaign, Urbana, ILYunfei Deng - GLOBALFOUNDRIES, Sunnyvale, CA Pawitter Mangat - GLOBALFOUNDRIES, Malta, NY

55.48 Detecting Systematic Defects with Diagnosis-Based ComparisonBharath Seshadri, Puneet Gupta, Bruce Cory - NVIDIA Corp., Santa Clara, CA

55.49 Exploiting the Task-Pipelined Parallelism of Stream Programs on Many-Core GPUsShuai Mu, Yubei Chen, Yangdong Deng - Tsinghua Univ., Beijing, ChinaDongdong Li - Beihang Univ., Beijing, China

55.50 Multi-Target Design Space Exploration for FPGA-Based MultiprocessorsPeng Chen, Chao Wang, Xi Li, Junneng Zhang, Xiaojing Feng, Xuehai Zhou - Univ. of Science and Technology of China, Suzhou, China

55.51 Game-Driven Discovery of New Mapping Strategies for Custom Domain-Specific ArchitecturesGayatri Mehta, Samuel Cook, Krunalkumar Patel, Brandon J. Rodgers, Anil Yadav - Univ. of North Texas, Denton, TXCarson Crawford - Univ. of Nebraska, Lincoln, NEAdeola Odunsi - Jackson State Univ., Decatur, IL

55.52 SIMD Performance and Yield Optimization with Multi-Granularity RedundancyBrett H. Meyer - McGill Univ., Montréal, QC, CanadaDaniel A. Epstein, Kevin Skadron - Univ. of Virginia, Charlottesville, VA

55.53 Single Pin Redundancy for Robust Power Grid DeliverySheldon Logan, Matthew Guthaus - Univ. of California, Santa Cruz, CA

55.54 Emulating Analog/Mixed-Signal Circuits with a 45nm Discrete-Sized Programmable Device ArrayNaveen Suda, Cheng Xu, Jounghyuk Suh, Yu Cao, Bertan Bakkaloglu - Arizona State Univ., Tempe, AZNagib Hakim - Intel Corp., Santa Clara, CA

55.55 OpenMP-Based Synergistic Parallelization and Hardware Acceleration for On-Chip Multi-Core Shared-Memory ClustersAndrea Marongiu, Paolo Burgio, Luca Benini - Univ. di Bologna, ItalyCyrille Chavet, Dominique Heller, Philippe Coussy - Univ. de Bretagne SUD, Lorient, France

55.56 Deadline-Constrained Scheduling of Charge Migration Tasks in Hybrid Electrical Energy Storage SystemsDi Zhu, Qing Xie, Yangzhi Wang, Massoud Pedram - Univ. of Southern California, Los Angeles, CAYounghyun Kim, Naehyuck Chang - Seoul National Univ., Seoul, Republic of Korea

55.57 Kendall Syndrome Coding (KSC) for Group-Based Ring-Oscillator Physical Unclonable FunctionsChi-En Yin, Gang Qu - Univ. of Maryland, College Park, MD

55.58 Bias Runaway: An Emerging Reliability Threat in Scaled Analog and Mixed Signal DesignKetul B. Sutaria, Jyothi B. Velamala, Sule Ozev, Yu Cao - Arizona State Univ., Tempe, AZ

55.59 InTimeFix: A Low-Cost and Scalable Technique for In-Situ Timing Error Masking in Logic CircuitsFeng Yuan, Qiang Xu - The Chinese Univ. of Hong Kong, Shatin, Hong Kong

55.60 Self-Aligned Double and Quadruple Patterning Aware Grid Routing MethodsChikaaki Kodama, Hirotaka Ichikawa, Koichi Nakayama, Toshiya Kotani, Shigeki Nojima, Shoji Mimotogi, Shinji Miyamoto - Toshiba Corp., Yokohama, Japan

55.61 Redundancy and ECC Mechanisms to Improve Energy Efficiency of On-Die InterconnectsAlaa R. Alameldeen - Intel Corp., Hillsboro, ORAmr Helmy - American Univ. of Cairo, Egypt

55.62 Modeling and Synthesis of Energy-Optimal Approximate AddersJin Miao, Ku He, Andreas Gerstlauer, Michael Orshansky - Univ. of Texas, Austin, TX

55.63 The Effects of Temperature on Timing in 3-D Integrated CircuitsSravan K. Marella, Sanjay V. Kumar, Sachin S. Sapatnekar - Univ. of Minnesota, Minneapolis, MN

55.64 Efficient Retention Register Assignment for Power Gated DesignsYiyu Shi - Missouri Univ. of Science and Technology, Rolla, MOYu-Guang Chen, Kuan-Yu Lai, Shih-Chieh Chang - National Tsing Hua Univ., Hsinchu, Taiwan

55.65 A Fair Main Memory Subsystem for CPU/GPUSungkwang Lee, Sungjoo Yoo - Pohang Univ. of Science and Technology, Pohang, Republic of Korea

55.66 Watermark-Based Identification and Implementation Efficiency of IP Embedded Processor CoresJedrzej J. Kufel, Peter R. Wilson, Bashir Al-Hashimi - Univ. of Southampton, United KingdomStephen Hill - ARM, Ltd., Cambridge, United Kingdom

55.67 Hybrid 3-D IC Cooling System Using Micro-Fluidic Cooling and Thermal TSVsAnkur Srivastava, Bing Shi - Univ. of Maryland, College Park, MD

www.DAC.com 45

ADJUNCT EVENTS

IEEE CEDA PRESENTS: DIGITAL ANALOG DESIGNTuesday, June 5 - 11:45am - 1:30pm

Organizer: Joel Phillips - Cadence Design Systems, Inc., Berkeley, CA

Speaker: Mark Horowitz - Stanford Univ., Stanford, CA

The past 30 years have seen an enormous growth in the power and sophistication of digital design tools, while progress in analog tools has been much more modest. Digital tools use many abstractions to allow them to validate that implementations match the functional models and the composition of cells matches the composition of the functional models.

While there are many reasons why this is more difficult for analog circuits, it can be done. To prove this point, this talk presents how to leverage the fact that the result surface of analog designs is smooth to create ways to formally validate analog models to instances, define analog fault models, and even efficiently explore the effect of process variations.

Room: 303

15TH ANNUAL SIGDA PH.D. FORUM/MEMBER MEETINGTuesday, June 5 - 7:00pm - 8:30pmSIGDA invites you to attend our 15th annual Ph.D. Forum and Member Meeting at DAC 2012. SIGDA members are invited, as are all members of the EDA Community. We will begin with an overview of SIGDA programs, including newly created programs, followed by the presentation of this year’s ACM/SIGDA Awards.

However, the main focus of the meeting will be the Ph.D. Forum. Aimed at strengthening ties between academia and industry, students will present posters and discuss their Ph.D. dissertation research with interested attendees. The Ph.D. Forum gives students feedback on their research and gives the EDA community a preview of work in progress. Light refreshments will be served.

General InterestRoom: 303

General Interest

25TH ACM SIGDA UNIVERSITY BOOTH AT THE 49TH DESIGN AUTOMATION CONFERENCETuesday, June 5 - Wednesday, June 610:00am - 5:00pm Booth Coordinators:

Naehyuck ChangBaris Taskin Joe Zambreno

South Lobby General Interest

This year marks the 25th University Booth at the Design Automation Conference. The booth is an opportunity for university researchers to display their results and to interact with participants at DAC. Presenters and attendees at DAC are especially encouraged to participate, but participation is open to all members of the university community. The demonstrations include new EDA tools, EDA tool applications, design projects, and instructional materials.

www.DAC.com

In addition to DAC’s comprehensive technical program, there are other conferences hosting their events at DAC. There is a separate registration fee to attend these meetings. If you are attending one of the conferences below, your registration does include entrance to the DAC Exhibit Hall Monday-Wednesday. Please note that a DAC Conference Registration does not include the colocated conferences.

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COLOCATED CONFERENCESAdditional Registration Fees Apply

INTERNATIONAL WORKSHOP ON LOGIC AND SYNTHESIS (IWLS)Friday, June 1- Sunday, June 3: 8:00am - 6:00pmOrganizers:

Ilya Wagner - Intel Corp., Hillsboro, ORPhilip Brisk - Univ. of California, Riverside, CA

The International Workshop on Logic and Synthesis is the premier forum for research in synthesis, optimization, and verification of integrated circuits. Research on logic synthesis for emerging technologies and for novel computing platforms, such as nanoscale systems and biological systems, is also strongly encouraged. The workshop accepts complete papers as well as abstracts, highlighting important new problems in the early stages of development, without providing complete solutions. The emphasis is on novelty and intellectual rigor.

Topics of interest include (but are not limited to): synthesis and optimization; power and timing analysis; testing, validation and verification; architectures and compilation; and design experiences. Submissions on modeling, analysis and synthesis for emerging technologies and platforms are also encouraged. Both complete papers as well as extended abstracts highlighting new problems and new topics of research are welcomed. Only original and previously unpublished material is permitted.

Accepted papers are distributed only to IWLS participants. The workshop format includes paper presentations, posters, invited talks, social lunch and dinner gatherings, and recreational activities.

High-Level and Logic SynthesisUniv. of California, Berkeley

SYSTEM-LEVEL INTERCONNECT PREDICTION (SLIP)

ESLsyn 2012 - THE 2012 ELECTRONIC SYSTEM LEVEL SYNTHESIS CONFERENCESaturday, June 2 - Sunday, June 3: 9:00am - 5:00pmOrganizers:

Philippe Coussy - Lab-STICC, Lorient Cedex, FranceSandeep Shukla - Virginia Polytechnic Institute and State University, Blacksburg, VAJens Brandt - Technische Univ. Kaiserslautern, GermanyAchim Rettberg - Univ. of Oldenburg, GermanyAdam Morawiec - ECSI, Gieres, France

The ever-increasing need for enhanced productivity in designing highly complex electronic systems drives the evolution of design methods beyond the traditional approaches. Virtual prototyping, design space exploration and system synthesis with the goal of optimized and functionally correct product implementations are needed for designing both HW and SW parts. ESL design does not only provide system architects with the right tools to make the right decisions about the system

architecture, it includes the methodologies and techniques that correlate the ESL model. A well-connected ESL-to-implementation design flow is needed.

The system design teams expect newer and more efficient methods and tools supporting better management of the design complexity and reduction of the design cycle time all together, breaking the trend to compromise on the evaluation of various design implementation options. Designing at higher levels of abstraction is a viable way to better cope with the system design complexity, to verify earlier in the design process and to increase code reuse.The Electronic System Level Synthesis Conference ESLsyn focuses on automat-ed system design methods that enable efficient modelling of systems to provide the capability to synthesize HW platforms and embedded software with particular aspects related to synthesis.


Organizers:Deming Chen - Univ. of Illinois at Urbana-Champaign, Urbana, ILMustafa Ozdal - Intel Corp., Portland, ORRasit Topaloglu - IBM Corp., New York, NY

The 14th International Workshop of System Level Interconnect Prediction (SLIP) will be colocated with the 49th IEEE/ACM Design Automation Conference on June 3, 2012 at the Moscone Center, San Francisco, California.

The general technical scope of the workshop is the design, analysis and prediction of interconnect and communication fabrics in electronic systems. The workshop themes would include keynote speech, regular paper sessions with paper

discussion panels, interactive poster sessions, panels on hot research topics, and embedded tutorials and invited talks. Representative technical topics include, but are not limited to: interconnect prediction and optimization at various IC design stages, interconnect design challenges and system-level NoC design, design and analysis of power and clock networks, interconnect architecture of structural designs and FPGAs, interconnect fabrics of many-core architectures, design-for-manufacturing (DFM) techniques for interconnects, high speed chip-to-chip interconnect design, design and analysis of chip-package interfaces, interconnect topologies of multiprocessor systems, 3-D interconnect design and prediction, emerging interconnect technologies, sensor networks, and synergies between chip communication networks and networks arising in other contexts such as social networks, system biology, etc.

Sunday, June 3: 8:00am - 5:00pm System Level Design and CommunicationRoom: 300

Room: 303

IEEE INTERNATIONAL SYMPOSIUM ON HARDWARE- ORIENTED SECURITY AND TRUST (HOST 2012)Sunday, June 3 - Monday, June 4: 8:30am - 6:00pmOrganizers:

Ken Mai - Carnegie Mellon Univ., Pittsburgh, PARamesh Karri - Polytechnic Institute of New York Univ., New York, NY

A wide range of applications, from secure RFID tagging to high-end trusted computing, relies on dedicated and trusted hardware platforms. The security and trustworthiness of such hardware designs are critical to their successful deployment and operation. Recent advances in tampering and reverse engineering show that important challenges lie ahead.

For example, secure electronic designs may be affected by malicious circuits, Trojans that alter system operation. Furthermore, dedicated secure hardware implementations are susceptible to novel forms of attack that exploit side-channel leakage and faults. Third, the globalized, horizontal semiconductor business model raises concerns of trust and intellectual-property protection.HOST 2012 is a forum for novel solutions to address these challenges. Innova-tive test mechanisms may reveal Trojans in a design before they are able to do harm. Implementation attacks may be thwarted using side-channel resistant design or fault-tolerant designs. New security- aware design tools can assist a designer in implementing critical and trusted functionality, quickly and efficiently.


www.DAC.com


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IEEE DESIGN FOR MANUFACTURING AND YIELD (DFM&Y) WORKSHOP

SI2 ROUND-UP @ DAC: STANDARDS IN ACTION

SI2 OPEN LUNCHEON, A CELEBRATION OF THE 10TH ANNIVERSARY OF OPENACCESS

SI2 OPEN NETWORKING RECEPTION

Monday, June 4 - 8:30am - 7:00pm

Monday, June 4 - 9:00am - 6:00pm

Monday, June 4 -12:15 - 1:30pm

Organizers:Nagaraj NS - Texas Instruments, Inc., Dallas, TXAmith Singhee - IBM T.J. Watson Research Ctr., Yorktown Heights, NYWill Conley - Dynamic Intelligence, Austin, TX

Increased manufacturing susceptibility in today’s nanometer technologies requires up to date solutions for yield optimization. In fact, designing an SoC for manufacturability and yield aims at improving the manufacturing process and consequently its yield by enhancing communications across the “design”manufacturing interface.

A wide range of Design-for-Manufacturability (DFM), Design-for-Yield (DFY) and Design-for-Test (DFT) methodologies and tools are proposed today. Some of

Organizers:Sumit DasGupta - Si2, Austin, TXNick English - Si2, Austin, TXJake Buurma - Si2, Austin, TX

Speaker(s): Jim Culp - IBM Corp., Hopewell Junction, NYVito Dai - GLOBALFOUNDRIES, Sunnyvale, CAS.W. Paek - Samsung, Yongin-City, Republic of KoreaConcetta Riccobene - LSI Corp., San Jose, CACathy Rogers - Synopsys, Inc., Mountain View, CARiko Radojcic - Qualcomm, Inc., San Diego, CAArif Rahman - Altera Corp., San Jose, CAAveek Sarkar - Apache Design, Inc. a subsidiary of ANSYS, Inc., San Jose, CAKeith Felton - Cadence Design Systems, Inc., San Jose, CADusan Petranovic - Mentor Graphics Corp., San Jose, CAGilles Namur - STMicroelectronics, Crolles, FranceJames Masters - Intel Corp., Folsom, CAGilles Lamant - Cadence Design Systems, Inc., San Jose, CA

This complimentary lunch will celebrate the 10th Anniversary of the first release of OpenAccess and will also serve as the annual open Si2 meeting that will include a short presentation on the “state-of-the-union” at Si2 and announcement of the results of the annual election of Si2’s board of directors.

This complimentary reception will continue the celebration for the 10th Anniversary of OpenAccess. Free hors d’oeuvres and refreshments will be provided.

these are leveraged during the back-end design stages, and others have post design utilization, from lithography up to 3-D integration, wafer sort, packaging, final test and failure analysis. These solutions can dramatically impact the business performance of chip manufacturers. They can also significantly affect age-old chip design flows.

Using a DFM/DFY/DFT solution is an investment and thus choosing the most cost effective one(s) requires trade-off analysis. The workshop will analyze key trends and challenges in DFM, DFY and DFT methodologies, and provide an opportunity to discuss a range of DFM, DFT and DFY solutions for SoC designs now and in the future, including practical case studies that demonstrate the successes and failures of such solutions.

Design for Manufacturability

General Interest

General Interest

Room: 300

Room: 301

Room: 303

Room: 301

Standards have been proven to reduce cost of operations, drive greater process efficiencies and offer greater opportunities for start-up companies to infuse fresh technology in the design and manufacturing of IC’s. Si2 standards have been targeted to resolve “pinch-points” in the overall semiconductor food-chain with a steadfast focus on rapid adoption of these standards.

This day-long program, consisting of 4 individual events, will showcase activities currently underway with an eye towards demonstrating the value of these programs to the program participants and to the overall semiconductor industry. Therefore, this day-long session should entice engineers and technologists working at both current and cutting-edge technology nodes and also managers responsible for driving both design and manufacturing strategy, and related financial and staffing decisions. A featured part of the program will celebrate the 10th Anniversary of OpenAccess. A complimentary luncheon and an afternoon reception will highlight this occasion.

Monday, June 4 - 4:30 - 6:00pm General Interest

www.DAC.com


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ACM STUDENT RESEARCH COMPETITION AT DESIGN AUTOMATION CONFERENCETuesday, June 5 - Wednesday, June 6: 2:00 - 4:00pmOrganizers:

Naehyuck Chang - Seoul National Univ., Seoul, Republic of KoreaSrinivas Katkoori - Univ. of South Florida, Tampa, FL

Sponsored by Microsoft Research, the ACM Student Research Competition is an internationally recognized venue enabling undergraduate and graduate students who are ACM members to:

• Experience the research world -- for many undergraduates this is a first!

• Share research results and exchange ideas with other students, judges, and conference attendees

• Rub shoulders with academic and industry luminaries• Understand the practical applications of their research• Perfect their communication skills• Receive prizes and gain recognition from ACM

and the greater computing community.

The ACM Special Interest Group on Design Automation is organizing such an event in conjunction with the Design Automation Conference.

Authors of accepted submissions will get travel grants from ACM/Microsoft to attend the event at DAC. The event consists of several rounds, as described here and also here, where you can also find more details on student eligibility and timeline.

Research projects from all areas of design automation are encouraged. The author submitting the abstract must still be a student at the time the abstract is due. Each submission should be made on the EasyChair submission link available here where details on submission format can also be found here.


CELUG/EDAC ENTERPRISE LICENSING CONFERENCE

Organizers:Lee Levenson - CELUG, Tarzana, CA

EDA Licensing providers, ISVs, and users will come together at an event colocated with the Design Automation Conference in San Francisco, June 5, 6 & 7, 2012. CELUG (Centralized Enterprise Licensing Users Group) and EDAC (EDA Consortium) are co-hosting this three-day event at DAC 2012. This interactive event will focus on Enterprise Licensing, with presentations and panels addressing current and future challenges to making high technology tools and users more productive.

Wednesday, June 6 - Thursday, June 7: 9:00am - 6:00pm

General InterestRoom: 236-238

This colocated event will bring together Licensing Solution Providers, Independent Software Vendors face to face for interactive sessions with Enterprise Customers from key industries, including:• Academia• Aerospace• Automotive• Oil and Gas• Semiconductor• Life Sciences• Chemical Analysis• Electronic Test• Electronic Measurement

The day-long program will be divided into 4 sessions, a luncheon, and a reception. Attendees can register for individual sessions or for the entire program. The sessions are considered colocated events; please click here to register.

special interest group on

design automation

www.DAC.com

Sponsored by:

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PAVILION PANELSMONDAY, JUNE 4 BOOTH #310

GARY SMITH ON EDA: TRENDS AND WHAT’S HOT AT DAC9:15 - 10:15am General Interest

Moderator:Robert Gardner - EDA Consortium, San Jose, CA

Panelist: Gary Smith - Gary Smith EDA, Santa Clara, CA

Longtime EDA analyst Gary Smith of Gary Smith EDA will give us his take on the EDA’s hottest technology trends. How will the dramatic changes in EDA, the semiconductor market and the design community affect you? What are the hot ‘must sees’ at this year’s conference? Find out here!

LOW POWER TO THE PEOPLE!

IS “LIFECARE” THE NEXT KILLER APP?

THE MECHANICS OF CREATIVITY

10:30 - 11:15am

11:30am - 12:15pm

3:15 - 4:15pm


Business

General Interest

Moderator:John Donovan - Low-Power Design, Austin, TX

Panelists: Aveek Sarkar - Apache Design, Inc. a subsidiary of ANSYS, Inc., San Jose, CAClive Bittlestone - Texas Instruments, Inc., Dallas, TXRobert Patti - Tezzaron Semiconductor, Naperville, IL

Moderator:Rick Merritt - EE Times, San Jose, CA

Panelists: James Bates - Maxim Integrated Products, Inc., Sunnyvale, CAFabrice Hoerner - Qualcomm, Inc., San Diego, CAGreg Fawcett - Palo Alto Research Center, Inc., Palo Alto, CA

Moderator:Karen Bartleson - Synopsys, Inc., Colorado Springs, CO

Panelists: Dee McCrorey - Risktaking for Success LLC, Santa Clara, CASherry Hess - AWR Corp., El Segundo, CALillian Kvitko - Oracle, Santa Clara, CA

Power management has become the single biggest design challenge. Methods used to manage power will depend on the interaction among process technologies, IP, hardware design, and embedded software for the targeted application. New technologies such as 3-D present further power management opportunities and challenges. Come hear these experts discuss power management struggles and solutions.

The world population hit 7 billion last fall, with a billion more expected in a dozen years. “Lifecare” represents an incredible opportunity for the semiconductor industry to promote health, energy conservation, safety and productivity. From smart city infrastructure to medical care advances, from sensors and controls to nanotechnology, what new EDA ecosystems will emerge to better model the real world?

What does it take to be an idea machine? Design is an inherently creative process, but how can we be creative on demand? How can we rise above mundane tasks with flashes of brilliance? Discover secrets of technical and business creativity and calculated risk taking, and share stories of innovation. Sponsored by Women in Electronic Design.

INTERVIEW WITH DR. BELLE W. Y. WEI, 2012 MARIE R. PISTILLI AWARD RECIPIENT4:30 - 5:15pm General Interest

Moderator:Daya Nadamuni - Gary Smith EDA, San Jose, CA

Panelist: Dr. Belle W. Y. Wei - San Jose State Univ., San Jose, CA

Women have made important contributions and strides in the EDA industry. The DAC Executive Committee presents an annual award to honor an individual who has made significant contributions in helping women advance in EDA technology. Please join us for a conversation with this year’s 2012 Marie R. Pistilli Award recipient, Dr. Belle W. Y. Wei, Don Beall Dean of Engineering, San Jose State University. Since her 2002 appointment as Don Beall Dean of SJSU’s Charles W. Davidson College of Engineering, Dr. Belle W. Y. Wei has led a College dedicated to educating engineers who can take on today’s problems and produce tomorrow’s solutions.

Dr. Wei began her career at SJSU in 1987 as an assistant professor in the Department of Electrical Engineering after completing an engineering M.S. from Harvard and an electrical engineering Ph.D. from U.C. Berkeley with specialties in VLSI circuit theory, special architectures, and sensor networks. Following a 1993-94 Stanford visiting associate professorship, Dr. Wei returned to SJSU where she was later elected Electrical Engineering Department Chair from 1998-2002. Thereafter, she accepted her current position as Dean (reappointed for a second six-year term in 2009). Dr. Wei is the first person in her College’s history to hold an endowed deanship.

www.DAC.com

Sponsored by:

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PAVILION PANELSTUESDAY, JUNE 5 BOOTH #310

HOGAN’S HEROES: LEARNING FROM APPLE

CHEVY VOLT TEARDOWN: AUTOMOTIVE ELECTRONICS

HERITAGE SERIES: INTERVIEW WITH JIM SOLOMON, 1997 PHIL KAUFMAN AWARD RECIPIENT

CONQUERING NEW FRONTIERS IN ANALOG DESIGN - PLUNGING BELOW 28NM

10:00 - 11:00am

1:30 - 2:30pm

3:00 - 3:45pm

4:00 - 4:45pm

Business

General Interest



Moderator: Jim Hogan - Tela Innovation, Inc., Campbell, CA

Panelists: Jack Guedj - Tensilica, Inc., Santa Clara, CATom Collopy - Aggios, Inc., Irvine, CAJan Rabaey - Univ. of California, Berkeley, CA

Moderator: Brian Fuller - EE Times, San Francisco, CA

Panelists: Al Steier - Munro & Associates, Inc., Troy, MIJohn Scott-Thomas - TechInsights, Ottawa, ON, Canada

Moderator: Steve Ohr - Gartner, Inc., San Jose, CA

Panelist: Jim Solomon - Xulu Entertainment, Milpitas, CA

Moderator: Mar Hershenson - Revel Touch, Inc., Los Altos, CA

Panelists: Jose Alvarez - Freescale Semiconductor, Inc., Austin, TXKT Moore - Synopsys, Inc., Mountain View, CAMahesh R. Tirupattur - Analog Bits, Inc., Mountain View, CA

Apple. We admire their devices, worship their creators and praise their stock in our portfolios. Apple is synonymous with creative thinking, new opportunities, perseverance and wild success. Along the road, Apple set new technical and business standards. But how much has the electronics industry, in particular EDA, “where electronics begins,” learned from Apple? It depends.

FOUNDRY, EDA AND IP: SOLVE TIME-TO-MARKET ALREADY!

11:30am - 12:15pm General Interest

Moderator: Ron Wilson - Altera Corp., San Jose, CA

Panelists: Dr. Naveed Sherwani - Open-Silicon, Inc., Milpitas, CARitesh Saraf - MoSys, Inc., Santa Clara, CAJohn Koeter - Synopsys, Inc., Mountain View, CA

Designing billion+ transistor SoCs for 20nm and below in 22 months is not fast enough! Challenges include qualifying and integrating IP blocks, custom logic, and achieving design closure. This panel will discuss what foundry, IP and EDA vendors are doing to step up and finally deliver plug-and-play solutions.

The analog design tool segment has long lived in the shadow of its dazzling digital tool counterpart. But without analog, countless consumer electronics devices would not exist. No one has been more closely associated with the advances in analog tool creation than Jim Solomon, Phil Kaufman Award Recipient. Hear Jim illuminate the mystic world of analog.

Analog design flows have not changed much in the past two decades, yet analog IP has been at the forefront of every new technology node breakthrough. This panel will discuss some of the major electrical, physical and process design challenges at 28nm and below, and what adjustments can be made in the design ecosystem to facilitate first-pass silicon success.

The Chevy Volt, the most talked-about automotive innovation in recent years, has been peeled apart down to the board level. Watch and listen as experts analyze the Volt’s amazing design--assembly, boards, components, sensors and chips, not to mention its 360V lithium-ion battery--and offer a glimpse at the automobile’s future.

www.DAC.com

Sponsored by:

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PAVILION PANELSWEDNESDAY, JUNE 6 BOOTH #310

TOWN HALL: DARK SIDE OF MOORE’S LAW

REAL WORLD HETEROGENEOUS MULTICORE

TEENS TALK TECH

HARDWARE-ASSISTED PROTOTYPING AND VERIFICATION: MAKE VS. BUY?

9:15 - 10:15am

2:30 - 3:15pm

3:30 - 4:15pm

4:30 - 5:15pm

Business


General Interest


Moderator: Lucio Lanza

Panelists: John Chilton - Synopsys, Inc., Mountain View, CABehrooz Abdi - Consultant, San Diego, CASteve Glaser - Xilinx, Inc., San Jose, CA

Moderator: Tom Halfhill - The Linley Group, Mountain View, CA

Panelists: Ted Vucurevich - Enconcert, Inc., Los Gatos, CAPaul Tobin - Advanced Micro Devices, Inc., Boston, MADavid Kramer - Freescale Semiconductor, Inc., Austin, TX

Moderator: Kathryn Kranen - Jasper Design Automation, Inc., Mountain View, CA

Panelists: Josh Godfrey - Menlo High School, Atherton, CASummer Schoof - Menlo High School, Atherton, CAShuhei Nakata - Menlo High School, Atherton, CATara Basu-Trivedi - Menlo High School, Atherton, CA

Moderator: Gabe Moretti - Gabe on EDA, Venice, FL

Panelists: Albert Camilleri - Qualcomm, Inc., San Diego, CAAustin Lesea - Xilinx, Inc., San Jose, CAMike Dini - The Dini Group, Inc., La Jolla, CA

Semiconductor companies double transistor counts every 22 months, yet device prices stay relatively the same. This has been a windfall for customers but not for chip makers, who have exponentially increasing design costs every new cycle. Venture capitalist Lucio Lanza and panelists will discuss what it will take to bring design costs and profitability back into harmony with Moore’s Law.

DIVIDE AND CONQUER - INTELLIGENT PARTITIONING

1:30 - 2:15pm Physical Design

Moderator: Paul McLellan - SemiWiki, San Francisco, CA

Panelists: Santosh Santosh - NVIDIA Corp., Santa Clara, CAJonathan DeMent - IBM Systems and Technology Group, Austin, TXHao Nham - eSilicon Corp., Sunnyvale, CA

If you were assigned a 100+ million-instance 28-nm chip, what would you do? Hire more engineers, push out the delivery date, quit? Not if you could help it. Partition it! But how many blocks? This panel will discuss what’s needed from synthesis, verification and physical design tools to make partitioning work for today’s designs, budgets, resources and delivery schedules.

High school students tell us how they use the latest tech gadgets, and what they expect to be using in three to five years. They give insights into the next killer applications and what they would like to see in the next generation of hot new electronics products that we should be designing now.

As ASIC and ASSP designs reach billions of gates, hardware-assisted verification and/or prototyping is becoming essential, but what is the best approach? Should you buy an off-the-shelf system or build your own? What criteria – time-to-market, cost, performance, resources, quality, ease of use – are most important? Panelists will share their real world design trade-offs.

What does heterogeneous multicore mean to you? Come hear experts discuss the challenges when implementing heterogeneous multicores describing real world experiences using both different core sizes and types as well as techniques and tools to develop systems that take advantage of these multicore architectures.

CONQUERING NEW FRONTIERS IN ANALOG DESIGN - PLUNGING BELOW 28NM

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ADDITIONAL MEETINGS Access to these meetings is controlled by the organizing entity

Monday, June 4: 9:00am - 6:00pm

HIGH PERFORMANCE DESIGN SUCCESS WITH SYNOPSYS GALAXYTM IMPLEMENTATION PLATFORM

Synopsys invites you to join us for highly informative sessions covering the latest high performance design trends, challenges and solutions. Listen to leading industry experts present best practices and their success designing for high performance using Synopsys implementation products. Learn about innovations in high performance technology that help address your Gigascale, GigaHz and advanced geometry design challenges. If you are a design engineer or manager, you won’t want to miss these special events. *Please stop by Synopsys Booth 1130 for presentation access.

General Interest

DESIGN AND IP MANAGEMENT SYMPOSIUMMonday, June 4: 1:30 - 2:30pmChair(s):

Dean Drako - IC ManageSpeaker(s):

Vincent Ross - Advanced Micro Devices, Inc.Jacob Rael - Broadcom Corp.Gary Smith - Gary Smith EDAShiv Sikand - IC ManageDoug Quist - NVIDIA Corp.

General Interest

COOLEY’S TROUBLEMAKER PANELMonday, June 4: 3:00 - 4:00pmChair(s):

John Cooley - DeepchipSpeaker(s):

Doug Aitelli - Calypto Design Systems, Inc.Joe Sawicki - Mentor Graphics Corp.Lauro Rizzatti - EVE-USA, Inc.Ravi Subramanian - Berkeley Design AutomationYunshan Zhu - NextOp Software, Inc.Jim Hogan - Vista Ventures LLCGary Smith - Gary Smith EDA

General Interest

Room: 220

BOOST PRODUCTIVITY USING SYNOPSYS’ AMS VERIFICATION SOLUTIONMonday, June 4: 11:30am - 1:30pm

At this event, you will hear what industry leaders have to say about using Synopsys’ AMS verification solution in some of today’s most challenging designs. Panelists will also discuss their future verification needs as well as the methodology and tool requirements to support modern AMS verification.

Analog/Mixed-Signal/RF DesignSan Francisco Marriott Marquis

Room: 200

Room: 256

PRIMETIME SPECIAL INTEREST GROUP (SIG) RECEPTION FEATURING NEXT GENERATION HIERARCHICAL TIMING TECHNOLOGY - HYPERSCALEMonday, June 4: 7:00 - 8:30pmSynopsys hosts an annual dinner event for the PrimeTime Special Interest Group at DAC, providing an opportunity for PrimeTime users to stay connected with the latest developments in timing analysis. This year, the event will feature Synopsys’ next generation hierarchical timing technology, HyperScale. Synopsys’ R&D team will unveil the new underlying engines and industry experts will share their experience on this innovative new technology resulting in up to 10X faster and smaller full-chip timing analysis runs, with the same signoff quality results compared to flat analysis. The event will be held at the San Francisco Marriott Marquis.

Physical DesignSan Francisco Marriott Marquis

Panelists will discuss development goals, the Design and IP Management methodologies and best practices they use to support those goals, and the results achieved.

Topics to include productivity improvements, bug management, and multi-site data exchange and collaboration. Audience Q&A to follow panel discussion.

Come watch EDA vendors squirm as they answer no-holds-barred, edgy, user-sub-mitted questions about their businesses and tools. It’s an old style open Q&A from the days before corporate marketing took over every aspect of EDA company images.

www.DAC.com 53

ADDITIONAL MEETINGS Access to these meetings is controlled by the organizing entity

SAMSUNG-GLOBALFOUNDRIES - SYNOPSYS BREAKFAST

BIRDS-OF-A-FEATHER MEETING: AT A CROSSROADS – DEVELOPING THE NEXT GENERATION ANALOG/MIXED-SIGNAL LANGUAGE STANDARD(S)

Tuesday, June 5: 7:00 - 8:30pmOrganizer(s):

Martin Barnasconi - NXP Semiconductors, Eindhoven, The NetherlandsLynn Bannister - Accellera Systems Initiative, Napa, CA

Today’s embedded and integrated systems interact more and more tightly with the analog physical environment, where digital HW/SW subsystems become functionally interwoven with analog/mixed-signal (AMS) blocks such as radio frequency (RF) interfaces, power electronics, or sensors and actuators. Examples are software defined radios, wireless sensor networks, and automotive applications, in which analog electronics are controlled, configured, or calibrated using digital techniques in hardware or software.

Historically, the hardware description languages Verilog-AMS and VHDL-AMS have addressed the analog implementation aspects but have limited capabilities to address the system-level design and verification challenges. From the digital perspective, SystemC and SystemVerilog focus on system-level design and verification, respectively. The SystemC AMS extensions are positioned to address the mixed-signal architectural design challenges, whereas SystemVerilog extensions are under development to include abstract analog signal representation in functional verification. Obviously, we are at a crossroads, where Verilog-

Analog/Mixed Signal

INDUSTRY LEADERS VERIFY WITH SYNOPSYS

Tuesday, June 5: 11:30am - 1:00pmSynopsys hosts an annual lunch event at DAC, providing an opportunity for verification engineers, manager, and executives to stay connected with the latest developments in the verification landscape and advanced technology. This year, the event will cover the latest verification trends, challenges and solutions. You

San Francisco Marriott Marquis Verification and Test

IPL ALLIANCE LUNCHEON - REAPING THE BENEFITS OF IPDKS

NORTH AMERICAN SYSTEMC USERS GROUP MEETING - NASCUG 18

Tuesday, June 5: 12:00 - 1:30pm

Wednesday, June 6: 1:00 - 5:00pm

Interoperable PDKs (iPDKs) benefit the entire custom design ecosystem. Semiconductor foundries and IDMs create iPDKs to reduce their PDK development, validation, support and distribution costs while enabling advanced design flows and multiple EDA tool support. All leading foundries today are delivering iPDKs. Chip designers now enjoy access to best-in-class tools, interoperable flows, and

The North American SystemC Users Group (NASCUG) accelerates the use of SystemC for both new and established users by providing open venues for users to contribute, learn, and interact. A central component of the half-day meeting is a number of user experience presentations discussing techniques of design, modeling and verification using SystemC. Topics include (but not limited



San Francisco Marriott Marquis: Golden Gate Ballroom

Room: 250 & 262

Room: 300

Industry experts from Samsung, GLOBALFOUNDRIES and Synopsys discuss our unique design enablement collaboration that delivers proven design, IP and manufacturing solutions for advanced high-k metal-gate (HKMG) process technologies.

Tuesday, June 5: 7:15 - 8:25am Design for ManufacturabilitySan Francisco Marriott Marquis: Golden Gate Ballroom

will hear leading industry experts share their viewpoints on what is driving SoC complexity and how their teams have achieved success. The event will be held at the San Francisco Marriott Marquis.

improved productivity. At the 6th Annual IPL Luncheon, presenters from multiple foundries will highlight the benefits of iPDK standard and their experiences in developing and deploying foundry iPDKs. The IPL Alliance will present an update on current and future IPL projects.

to) architectural modeling; transaction-level modeling; virtual prototypes; analog modeling with SystemC AMS; integrating SystemC into the design flow; and platform design using SystemC. To find out more and register for this free event, visit www.nascug.org

AMS and VHDL-AMS are being updated and at the same time SystemC and SystemVerilog are expanding to support abstract AMS modeling styles. Should all of these AMS extensions remain compatible? Which elements are not yet addressed in the mixed-signal modeling and simulation domain but are essential for a next generation mixed-signal language? Can we focus on only one “mother HDL”, or do we need more?

We would like to discuss and answer these questions, to explore viable directions for the next step in AMS standards, at this Birds-of-a-Feather session. We invite AMS and RF system-level designers, circuit designers, verification engineers, and EDA vendors to discuss the requirements and needs for the next-generation AMS languages.

Accellera Systems Initiative, the independent non-profit organization focused on the creation and adoption of electronic design automation (EDA) and intellectual property (IP) standards for design and verification, will moderate this session to emphasize the importance of standardization in this domain. The intent is to foster the creation of next generation mixed-signal languages standards to describe hardware as well as system-level behavior.

Documents

TUESDAY KEYNOTE - Design Automation Conference · 6 TUESDAY KEYNOTE Room: 102/103 General Interest SUMMARY: Comparing the original ARM design of 1985 to those of today’s latest